1 ; RUN: llc -march=hexagon -disable-hexagon-shuffle=0 -O2 < %s | FileCheck %s 2 3 ; Generate vmemu (unaligned). 4 ; CHECK: vmemu 5 ; CHECK: vmemu 6 ; CHECK: vmemu 7 ; CHECK-NOT: vmem 8 9 target triple = "hexagon" 10 11 ; Function Attrs: nounwind 12 define void @f0(i8* nocapture readonly %a0, i8* nocapture readonly %a1, i8* nocapture %a2) #0 { 13 b0: 14 %v0 = bitcast i8* %a0 to <16 x i32>* 15 %v1 = load <16 x i32>, <16 x i32>* %v0, align 4, !tbaa !0 16 %v2 = bitcast i8* %a1 to <16 x i32>* 17 %v3 = load <16 x i32>, <16 x i32>* %v2, align 4, !tbaa !0 18 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v1, <16 x i32> %v3) 19 %v5 = bitcast i8* %a2 to <16 x i32>* 20 store <16 x i32> %v4, <16 x i32>* %v5, align 4, !tbaa !0 21 ret void 22 } 23 24 ; Function Attrs: nounwind readnone 25 declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1 26 27 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 28 attributes #1 = { nounwind readnone } 29 30 !0 = !{!1, !1, i64 0} 31 !1 = !{!"omnipotent char", !2, i64 0} 32 !2 = !{!"Simple C/C++ TBAA"} 33
