1 ; RUN: llc -march=hexagon -disable-hexagon-shuffle=1 -O2 < %s | FileCheck %s 2 ; Generate vshuff with 3rd param as an Rt8. 3 ; v1:0=vshuff(v0,v1,r7) 4 ; CHECK: vshuff(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]}}) 5 6 target triple = "hexagon" 7 8 @g0 = common global [15 x <16 x i32>] zeroinitializer, align 64 9 @g1 = common global <32 x i32> zeroinitializer, align 128 10 11 ; Function Attrs: nounwind 12 define i32 @f0() #0 { 13 b0: 14 %v0 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @g0, i32 0, i32 0), align 64, !tbaa !0 15 %v1 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @g0, i32 0, i32 1), align 64, !tbaa !0 16 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v0, <16 x i32> %v1, i32 -2147483648) 17 store <32 x i32> %v2, <32 x i32>* @g1, align 128, !tbaa !0 18 %v3 = tail call i32 bitcast (i32 (...)* @f1 to i32 (i32, <32 x i32>*)*)(i32 1024, <32 x i32>* @g1) #0 19 ret i32 0 20 } 21 22 ; Function Attrs: nounwind readnone 23 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1 24 25 declare i32 @f1(...) #0 26 27 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 28 attributes #1 = { nounwind readnone } 29 30 !0 = !{!1, !1, i64 0} 31 !1 = !{!"omnipotent char", !2, i64 0} 32 !2 = !{!"Simple C/C++ TBAA"} 33
