1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 ; CHECK: vmem 3 ; CHECK: vmem 4 ; CHECK-NOT: r{{[0-9]*}} = add(r30,#-256) 5 ; CHECK: vmem 6 ; CHECK: vmem 7 8 target triple = "hexagon" 9 10 ; Function Attrs: nounwind 11 define void @f0(i8* %a0, i8* %a1, i32 %a2, i8* %a3, i32 %a4) #0 { 12 b0: 13 %v0 = alloca i8*, align 4 14 %v1 = alloca i8*, align 4 15 %v2 = alloca i32, align 4 16 %v3 = alloca i8*, align 4 17 %v4 = alloca i32, align 4 18 %v5 = alloca <16 x i32>, align 64 19 %v6 = alloca <32 x i32>, align 128 20 store i8* %a0, i8** %v0, align 4 21 store i8* %a1, i8** %v1, align 4 22 store i32 %a2, i32* %v2, align 4 23 store i8* %a3, i8** %v3, align 4 24 store i32 %a4, i32* %v4, align 4 25 %v7 = load i8*, i8** %v0, align 4 26 %v8 = bitcast i8* %v7 to <16 x i32>* 27 %v9 = load <16 x i32>, <16 x i32>* %v8, align 64 28 %v10 = load i8*, i8** %v0, align 4 29 %v11 = getelementptr inbounds i8, i8* %v10, i32 64 30 %v12 = bitcast i8* %v11 to <16 x i32>* 31 %v13 = load <16 x i32>, <16 x i32>* %v12, align 64 32 %v14 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v9, <16 x i32> %v13) 33 store <32 x i32> %v14, <32 x i32>* %v6, align 128 34 %v15 = load i8*, i8** %v3, align 4 35 %v16 = bitcast i8* %v15 to <16 x i32>* 36 %v17 = load <16 x i32>, <16 x i32>* %v16, align 64 37 store <16 x i32> %v17, <16 x i32>* %v5, align 64 38 ret void 39 } 40 41 ; Function Attrs: nounwind readnone 42 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 43 44 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 45 attributes #1 = { nounwind readnone } 46
