1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2 ; CHECK-DAG: v{{[0-9]+}} = vsplat(r{{[0-9]+}}) 3 ; CHECK-DAG: v{{[0-9]+}} = vsplat(r{{[0-9]+}}) 4 ; CHECK-DAG: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}}) 5 ; CHECK: v{{[0-9]+}} = vmux(q{{[0-3]}},v{{[0-9]+}},v{{[0-9]+}}) 6 7 target triple = "hexagon" 8 9 @g0 = common global <16 x i32> zeroinitializer, align 64 10 @g1 = common global <16 x i32> zeroinitializer, align 64 11 @g2 = common global <16 x i32> zeroinitializer, align 64 12 @g3 = common global <16 x i32> zeroinitializer, align 64 13 14 ; Function Attrs: nounwind 15 define i32 @f0() #0 { 16 b0: 17 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 11) 18 store <16 x i32> %v0, <16 x i32>* @g1, align 64, !tbaa !0 19 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 12) 20 store <16 x i32> %v1, <16 x i32>* @g2, align 64, !tbaa !0 21 %v2 = load <16 x i32>, <16 x i32>* @g0, align 64, !tbaa !0 22 %v3 = bitcast <16 x i32> %v2 to <512 x i1> 23 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v3, <16 x i32> %v0, <16 x i32> %v1) 24 store <16 x i32> %v4, <16 x i32>* @g3, align 64, !tbaa !0 25 ret i32 0 26 } 27 28 ; Function Attrs: nounwind readnone 29 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 30 31 ; Function Attrs: nounwind readnone 32 declare <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1>, <16 x i32>, <16 x i32>) #1 33 34 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 35 attributes #1 = { nounwind readnone } 36 37 !0 = !{!1, !1, i64 0} 38 !1 = !{!"omnipotent char", !2} 39 !2 = !{!"Simple C/C++ TBAA"} 40
