1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s 2 ; CHECK: vmem(r{{[0-9]*}}+#1) = 3 4 target triple = "hexagon" 5 6 ; Function Attrs: nounwind 7 define i32 @f0(<16 x i32>* %a0, <32 x i32>* %a1) #0 { 8 b0: 9 %v0 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 10 store <16 x i32> %v0, <16 x i32>* %a0, align 64 11 %v1 = load <16 x i32>, <16 x i32>* %a0, align 64 12 %v2 = call <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32> %v1) 13 store <32 x i32> %v2, <32 x i32>* %a1, align 64 14 ret i32 0 15 } 16 17 ; Function Attrs: nounwind readnone 18 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 19 20 ; Function Attrs: nounwind readnone 21 declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #1 22 23 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 24 attributes #1 = { nounwind readnone } 25
