1 ; RUN: llc -march=hexagon -O3 < %s | FileCheck %s 2 ; CHECK-NOT: vsplat 3 ; CHECK: call f2 4 ; CHECK: v{{[0-9]+}} = vsplat 5 ; CHECK: v{{[0-9]+}} = vsplat 6 ; CHECK: v{{[0-9]+}} = vsplat 7 ; CHECK: v{{[0-9]+}} = vsplat 8 9 target triple = "hexagon" 10 11 @g0 = common global [2 x <32 x i32>] zeroinitializer, align 128 12 @g1 = common global <32 x i32> zeroinitializer, align 128 13 @g2 = common global [2 x <16 x i32>] zeroinitializer, align 64 14 15 ; Function Attrs: nounwind 16 define i32 @f0() #0 { 17 b0: 18 tail call void @f1() #2 19 %v0 = tail call i32 @f2(i8 zeroext 0) #2 20 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) #2 21 store <16 x i32> %v1, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 0), align 64, !tbaa !0 22 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) #2 23 store <16 x i32> %v2, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 1), align 64, !tbaa !0 24 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v1, <16 x i32> %v2) #2 25 store <32 x i32> %v3, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 0), align 128, !tbaa !0 26 store <32 x i32> %v3, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 1), align 128, !tbaa !0 27 %v4 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v3, <32 x i32> %v3, i32 -2147483648) 28 store <32 x i32> %v4, <32 x i32>* @g1, align 128, !tbaa !0 29 ret i32 0 30 } 31 32 declare void @f1() #0 33 34 declare i32 @f2(i8 zeroext) #0 35 36 ; Function Attrs: nounwind readnone 37 declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #1 38 39 ; Function Attrs: nounwind 40 define void @f3() #0 { 41 b0: 42 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 43 store <16 x i32> %v0, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 0), align 64, !tbaa !0 44 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) 45 store <16 x i32> %v1, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 1), align 64, !tbaa !0 46 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v0, <16 x i32> %v1) 47 store <32 x i32> %v2, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 0), align 128, !tbaa !0 48 store <32 x i32> %v2, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 1), align 128, !tbaa !0 49 ret void 50 } 51 52 ; Function Attrs: nounwind readnone 53 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 54 55 ; Function Attrs: nounwind readnone 56 declare <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32>, <16 x i32>) #1 57 58 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 59 attributes #1 = { nounwind readnone } 60 attributes #2 = { nounwind } 61 62 !0 = !{!1, !1, i64 0} 63 !1 = !{!"omnipotent char", !2, i64 0} 64 !2 = !{!"Simple C/C++ TBAA"} 65
