1 ; RUN: llc -march=hexagon < %s 2 ; REQUIRES: asserts 3 ; Check that llc does not crash. 4 5 @g0 = private unnamed_addr constant [7 x i8] c"%d\09\09%d\00", align 1 6 @g1 = common global <4 x i32> zeroinitializer, align 16 7 8 declare i32 @f0(...) 9 10 ; Function Attrs: nounwind 11 define i32 @f1() #0 { 12 b0: 13 %v0 = alloca i32, align 4 14 %v1 = alloca i32, align 4 15 %v2 = alloca [0 x <4 x i32>], align 16 16 store i32 0, i32* %v0 17 store i32 0, i32* %v1, align 4 18 %v3 = bitcast [0 x <4 x i32>]* %v2 to i8* 19 call void @llvm.memset.p0i8.i32(i8* align 16 %v3, i8 0, i32 0, i1 false) 20 %v4 = load i32, i32* %v1, align 4 21 %v5 = add nsw i32 %v4, 1 22 store i32 %v5, i32* %v1, align 4 23 %v6 = load <4 x i32>, <4 x i32>* @g1, align 16 24 %v7 = call i32 bitcast (i32 (...)* @f0 to i32 (i8*, i32, <4 x i32>)*)(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @g0, i32 0, i32 0), i32 %v5, <4 x i32> %v6) 25 ret i32 0 26 } 27 28 ; Function Attrs: argmemonly nounwind 29 declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1) #1 30 31 attributes #0 = { nounwind "target-cpu"="hexagonv60" } 32 attributes #1 = { argmemonly nounwind } 33
