1 ; RUN: llc -O0 -march=hexagon < %s | FileCheck %s 2 3 ; Make sure we generate stack alignment. 4 ; CHECK: [[REG1:r[0-9]*]] = and(r29,#-64) 5 ; CHECK: = add([[REG1]],#128) 6 ; CHECK: = add([[REG1]],#64) 7 ; Make sure we do not generate another -64 off SP. 8 ; CHECK: vmem( 9 ; CHECK-NOT: r{{[0-9]*}} = add(r29,#-64) 10 11 target triple = "hexagon" 12 13 @g0 = common global <16 x i32> zeroinitializer, align 64 14 15 ; Function Attrs: nounwind 16 define i32 @f0() #0 { 17 b0: 18 %v0 = alloca i32, align 4 19 %v1 = alloca <16 x i32>, align 64 20 %v2 = alloca <16 x i32>, align 64 21 store i32 0, i32* %v0 22 %v3 = call i32 @f1(i8 zeroext 0) 23 %v4 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 24 store <16 x i32> %v4, <16 x i32>* %v1, align 64 25 %v5 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 12) 26 store <16 x i32> %v5, <16 x i32>* %v2, align 64 27 %v6 = load <16 x i32>, <16 x i32>* %v1, align 64 28 %v7 = load <16 x i32>, <16 x i32>* %v2, align 64 29 %v8 = call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v6, <16 x i32> %v7) 30 store <16 x i32> %v8, <16 x i32>* @g0, align 64 31 call void bitcast (void (...)* @f2 to void ()*)() 32 ret i32 0 33 } 34 35 declare i32 @f1(i8 zeroext) #0 36 37 ; Function Attrs: nounwind readnone 38 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 39 40 ; Function Attrs: nounwind readnone 41 declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1 42 43 declare void @f2(...) #0 44 45 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 46 attributes #1 = { nounwind readnone } 47
