1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2 ; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}}) 3 ; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}}) 4 ; CHECK: q{{[0-3]}} = and(q{{[0-3]}},q{{[0-3]}}) 5 6 target triple = "hexagon" 7 8 @g0 = common global <16 x i32> zeroinitializer, align 64 9 10 ; Function Attrs: nounwind 11 define i32 @f0() #0 { 12 b0: 13 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 14 %v1 = bitcast <16 x i32> %v0 to <512 x i1> 15 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) 16 %v3 = bitcast <16 x i32> %v2 to <512 x i1> 17 %v4 = tail call <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1> %v1, <512 x i1> %v3) 18 %v5 = bitcast <512 x i1> %v4 to <16 x i32> 19 store <16 x i32> %v5, <16 x i32>* @g0, align 64, !tbaa !0 20 ret i32 0 21 } 22 23 ; Function Attrs: nounwind readnone 24 declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1 25 26 ; Function Attrs: nounwind readnone 27 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 28 29 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 30 attributes #1 = { nounwind readnone } 31 32 !0 = !{!1, !1, i64 0} 33 !1 = !{!"omnipotent char", !2, i64 0} 34 !2 = !{!"Simple C/C++ TBAA"} 35
