1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; Verify __builtin_HEXAGON_V6_vd0 maps to vxor 4 ; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}}) 5 6 @g0 = common global <16 x i32> zeroinitializer, align 64 7 8 ; Function Attrs: nounwind 9 define i32 @f0(i32 %a0) #0 { 10 b0: 11 %v0 = alloca i32, align 4 12 store i32 %a0, i32* %v0, align 4 13 %v1 = call <16 x i32> @llvm.hexagon.V6.vd0() 14 store <16 x i32> %v1, <16 x i32>* @g0, align 64 15 ret i32 ptrtoint (<16 x i32>* @g0 to i32) 16 } 17 18 ; Function Attrs: nounwind readnone 19 declare <16 x i32> @llvm.hexagon.V6.vd0() #1 20 21 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 22 attributes #1 = { nounwind readnone } 23
