1 ; RUN: llc -march=hexagon < %s | FileCheck %s 2 3 ; CHECK-LABEL: test_00 4 ; CHECK: [[L00:r[0-9:]+]] = vsxtbh(r0) 5 ; CHECK: [[R00:r[0-9:]+]] = vsxtbh(r1) 6 ; CHECK: [[P00:p[0-3]+]] = vcmph.eq([[L00]],[[R00]]) 7 ; CHECK-NOT: not([[P00]]) 8 define <4 x i8> @test_00(<4 x i8> %a0, <4 x i8> %a1) #0 { 9 %v0 = icmp eq <4 x i8> %a0, %a1 10 %v1 = sext <4 x i1> %v0 to <4 x i8> 11 ret <4 x i8> %v1 12 } 13 14 ; CHECK-LABEL: test_01 15 ; CHECK: [[L01:r[0-9:]+]] = vsxtbh(r0) 16 ; CHECK: [[R01:r[0-9:]+]] = vsxtbh(r1) 17 ; CHECK: [[P01:p[0-3]+]] = vcmph.eq([[L01]],[[R01]]) 18 ; CHECK: not([[P01]]) 19 define <4 x i8> @test_01(<4 x i8> %a0, <4 x i8> %a1) #0 { 20 %v0 = icmp ne <4 x i8> %a0, %a1 21 %v1 = sext <4 x i1> %v0 to <4 x i8> 22 ret <4 x i8> %v1 23 } 24 25 ; CHECK-LABEL: test_02 26 ; CHECK: [[L02:r[0-9:]+]] = vsxtbh(r0) 27 ; CHECK: [[R02:r[0-9:]+]] = vsxtbh(r1) 28 ; CHECK: [[P02:p[0-3]+]] = vcmph.gt([[R02]],[[L02]]) 29 ; CHECK-NOT: not([[P02]]) 30 define <4 x i8> @test_02(<4 x i8> %a0, <4 x i8> %a1) #0 { 31 %v0 = icmp slt <4 x i8> %a0, %a1 32 %v1 = sext <4 x i1> %v0 to <4 x i8> 33 ret <4 x i8> %v1 34 } 35 36 ; CHECK-LABEL: test_03 37 ; CHECK: [[L03:r[0-9:]+]] = vsxtbh(r0) 38 ; CHECK: [[R03:r[0-9:]+]] = vsxtbh(r1) 39 ; CHECK: [[P03:p[0-3]+]] = vcmph.gt([[L03]],[[R03]]) 40 ; CHECK: not([[P03]]) 41 define <4 x i8> @test_03(<4 x i8> %a0, <4 x i8> %a1) #0 { 42 %v0 = icmp sle <4 x i8> %a0, %a1 43 %v1 = sext <4 x i1> %v0 to <4 x i8> 44 ret <4 x i8> %v1 45 } 46 47 ; CHECK-LABEL: test_04 48 ; CHECK: [[L04:r[0-9:]+]] = vsxtbh(r0) 49 ; CHECK: [[R04:r[0-9:]+]] = vsxtbh(r1) 50 ; CHECK: [[P04:p[0-3]+]] = vcmph.gt([[L04]],[[R04]]) 51 ; CHECK-NOT: not([[P04]]) 52 define <4 x i8> @test_04(<4 x i8> %a0, <4 x i8> %a1) #0 { 53 %v0 = icmp sgt <4 x i8> %a0, %a1 54 %v1 = sext <4 x i1> %v0 to <4 x i8> 55 ret <4 x i8> %v1 56 } 57 58 ; CHECK-LABEL: test_05 59 ; CHECK: [[L05:r[0-9:]+]] = vsxtbh(r0) 60 ; CHECK: [[R05:r[0-9:]+]] = vsxtbh(r1) 61 ; CHECK: [[P05:p[0-3]+]] = vcmph.gt([[R05]],[[L05]]) 62 ; CHECK: not([[P05]]) 63 define <4 x i8> @test_05(<4 x i8> %a0, <4 x i8> %a1) #0 { 64 %v0 = icmp sge <4 x i8> %a0, %a1 65 %v1 = sext <4 x i1> %v0 to <4 x i8> 66 ret <4 x i8> %v1 67 } 68 69 ; CHECK-LABEL: test_06 70 ; CHECK: [[L06:r[0-9:]+]] = vsxtbh(r0) 71 ; CHECK: [[R06:r[0-9:]+]] = vsxtbh(r1) 72 ; CHECK: [[P06:p[0-3]+]] = vcmph.gtu([[R06]],[[L06]]) 73 ; CHECK-NOT: not([[P06]]) 74 define <4 x i8> @test_06(<4 x i8> %a0, <4 x i8> %a1) #0 { 75 %v0 = icmp ult <4 x i8> %a0, %a1 76 %v1 = sext <4 x i1> %v0 to <4 x i8> 77 ret <4 x i8> %v1 78 } 79 80 ; CHECK-LABEL: test_07 81 ; CHECK: [[L07:r[0-9:]+]] = vsxtbh(r0) 82 ; CHECK: [[R07:r[0-9:]+]] = vsxtbh(r1) 83 ; CHECK: [[P07:p[0-3]+]] = vcmph.gtu([[L07]],[[R07]]) 84 ; CHECK: not([[P07]]) 85 define <4 x i8> @test_07(<4 x i8> %a0, <4 x i8> %a1) #0 { 86 %v0 = icmp ule <4 x i8> %a0, %a1 87 %v1 = sext <4 x i1> %v0 to <4 x i8> 88 ret <4 x i8> %v1 89 } 90 91 ; CHECK-LABEL: test_08 92 ; CHECK: [[L08:r[0-9:]+]] = vsxtbh(r0) 93 ; CHECK: [[R08:r[0-9:]+]] = vsxtbh(r1) 94 ; CHECK: [[P08:p[0-3]+]] = vcmph.gtu([[L08]],[[R08]]) 95 ; CHECK-NOT: not([[P08]]) 96 define <4 x i8> @test_08(<4 x i8> %a0, <4 x i8> %a1) #0 { 97 %v0 = icmp ugt <4 x i8> %a0, %a1 98 %v1 = sext <4 x i1> %v0 to <4 x i8> 99 ret <4 x i8> %v1 100 } 101 102 ; CHECK-LABEL: test_09 103 ; CHECK: [[L09:r[0-9:]+]] = vsxtbh(r0) 104 ; CHECK: [[R09:r[0-9:]+]] = vsxtbh(r1) 105 ; CHECK: [[P09:p[0-3]+]] = vcmph.gtu([[R09]],[[L09]]) 106 ; CHECK: not([[P09]]) 107 define <4 x i8> @test_09(<4 x i8> %a0, <4 x i8> %a1) #0 { 108 %v0 = icmp uge <4 x i8> %a0, %a1 109 %v1 = sext <4 x i1> %v0 to <4 x i8> 110 ret <4 x i8> %v1 111 } 112 113 114 ; CHECK-LABEL: test_10 115 ; CHECK: [[L10:r[0-9:]+]] = vsxthw(r0) 116 ; CHECK: [[R10:r[0-9:]+]] = vsxthw(r1) 117 ; CHECK: [[P10:p[0-3]+]] = vcmpw.eq([[L10]],[[R10]]) 118 ; CHECK-NOT: not([[P10]]) 119 define <2 x i16> @test_10(<2 x i16> %a0, <2 x i16> %a1) #0 { 120 %v0 = icmp eq <2 x i16> %a0, %a1 121 %v1 = sext <2 x i1> %v0 to <2 x i16> 122 ret <2 x i16> %v1 123 } 124 125 ; CHECK-LABEL: test_11 126 ; CHECK: [[L11:r[0-9:]+]] = vsxthw(r0) 127 ; CHECK: [[R11:r[0-9:]+]] = vsxthw(r1) 128 ; CHECK: [[P11:p[0-3]+]] = vcmpw.eq([[L11]],[[R11]]) 129 ; CHECK: not([[P11]]) 130 define <2 x i16> @test_11(<2 x i16> %a0, <2 x i16> %a1) #0 { 131 %v0 = icmp ne <2 x i16> %a0, %a1 132 %v1 = sext <2 x i1> %v0 to <2 x i16> 133 ret <2 x i16> %v1 134 } 135 136 ; CHECK-LABEL: test_12 137 ; CHECK: [[L12:r[0-9:]+]] = vsxthw(r0) 138 ; CHECK: [[R12:r[0-9:]+]] = vsxthw(r1) 139 ; CHECK: [[P12:p[0-3]+]] = vcmpw.gt([[R12]],[[L12]]) 140 ; CHECK-NOT: not([[P12]]) 141 define <2 x i16> @test_12(<2 x i16> %a0, <2 x i16> %a1) #0 { 142 %v0 = icmp slt <2 x i16> %a0, %a1 143 %v1 = sext <2 x i1> %v0 to <2 x i16> 144 ret <2 x i16> %v1 145 } 146 147 ; CHECK-LABEL: test_13 148 ; CHECK: [[L13:r[0-9:]+]] = vsxthw(r0) 149 ; CHECK: [[R13:r[0-9:]+]] = vsxthw(r1) 150 ; CHECK: [[P13:p[0-3]+]] = vcmpw.gt([[L13]],[[R13]]) 151 ; CHECK: not([[P13]]) 152 define <2 x i16> @test_13(<2 x i16> %a0, <2 x i16> %a1) #0 { 153 %v0 = icmp sle <2 x i16> %a0, %a1 154 %v1 = sext <2 x i1> %v0 to <2 x i16> 155 ret <2 x i16> %v1 156 } 157 158 ; CHECK-LABEL: test_14 159 ; CHECK: [[L14:r[0-9:]+]] = vsxthw(r0) 160 ; CHECK: [[R14:r[0-9:]+]] = vsxthw(r1) 161 ; CHECK: [[P14:p[0-3]+]] = vcmpw.gt([[L14]],[[R14]]) 162 ; CHECK-NOT: not([[P14]]) 163 define <2 x i16> @test_14(<2 x i16> %a0, <2 x i16> %a1) #0 { 164 %v0 = icmp sgt <2 x i16> %a0, %a1 165 %v1 = sext <2 x i1> %v0 to <2 x i16> 166 ret <2 x i16> %v1 167 } 168 169 ; CHECK-LABEL: test_15 170 ; CHECK: [[L15:r[0-9:]+]] = vsxthw(r0) 171 ; CHECK: [[R15:r[0-9:]+]] = vsxthw(r1) 172 ; CHECK: [[P15:p[0-3]+]] = vcmpw.gt([[R15]],[[L15]]) 173 ; CHECK: not([[P15]]) 174 define <2 x i16> @test_15(<2 x i16> %a0, <2 x i16> %a1) #0 { 175 %v0 = icmp sge <2 x i16> %a0, %a1 176 %v1 = sext <2 x i1> %v0 to <2 x i16> 177 ret <2 x i16> %v1 178 } 179 180 ; CHECK-LABEL: test_16 181 ; CHECK: [[L16:r[0-9:]+]] = vsxthw(r0) 182 ; CHECK: [[R16:r[0-9:]+]] = vsxthw(r1) 183 ; CHECK: [[P16:p[0-3]+]] = vcmpw.gtu([[R16]],[[L16]]) 184 ; CHECK-NOT: not([[P16]]) 185 define <2 x i16> @test_16(<2 x i16> %a0, <2 x i16> %a1) #0 { 186 %v0 = icmp ult <2 x i16> %a0, %a1 187 %v1 = sext <2 x i1> %v0 to <2 x i16> 188 ret <2 x i16> %v1 189 } 190 191 ; CHECK-LABEL: test_17 192 ; CHECK: [[L17:r[0-9:]+]] = vsxthw(r0) 193 ; CHECK: [[R17:r[0-9:]+]] = vsxthw(r1) 194 ; CHECK: [[P17:p[0-3]+]] = vcmpw.gtu([[L17]],[[R17]]) 195 ; CHECK: not([[P17]]) 196 define <2 x i16> @test_17(<2 x i16> %a0, <2 x i16> %a1) #0 { 197 %v0 = icmp ule <2 x i16> %a0, %a1 198 %v1 = sext <2 x i1> %v0 to <2 x i16> 199 ret <2 x i16> %v1 200 } 201 202 ; CHECK-LABEL: test_18 203 ; CHECK: [[L18:r[0-9:]+]] = vsxthw(r0) 204 ; CHECK: [[R18:r[0-9:]+]] = vsxthw(r1) 205 ; CHECK: [[P18:p[0-3]+]] = vcmpw.gtu([[L18]],[[R18]]) 206 ; CHECK-NOT: not([[P18]]) 207 define <2 x i16> @test_18(<2 x i16> %a0, <2 x i16> %a1) #0 { 208 %v0 = icmp ugt <2 x i16> %a0, %a1 209 %v1 = sext <2 x i1> %v0 to <2 x i16> 210 ret <2 x i16> %v1 211 } 212 213 ; CHECK-LABEL: test_19 214 ; CHECK: [[L19:r[0-9:]+]] = vsxthw(r0) 215 ; CHECK: [[R19:r[0-9:]+]] = vsxthw(r1) 216 ; CHECK: [[P19:p[0-3]+]] = vcmpw.gtu([[R19]],[[L19]]) 217 ; CHECK: not([[P19]]) 218 define <2 x i16> @test_19(<2 x i16> %a0, <2 x i16> %a1) #0 { 219 %v0 = icmp uge <2 x i16> %a0, %a1 220 %v1 = sext <2 x i1> %v0 to <2 x i16> 221 ret <2 x i16> %v1 222 } 223 224 attributes #0 = { nounwind readnone } 225
