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      1 ; REQUIRES: asserts
      2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr --stats -o - 2>&1 < %s | FileCheck %s
      3 
      4 ; Check that store is post-incremented.
      5 ; CHECK-NOT: extractu(r{{[0-9]+}},#32,
      6 ; CHECK-NOT: insert
      7 ; CHECK-NOT: Number of node order issues found
      8 ; CHECK: Number of loops software pipelined
      9 ; CHECK-NOT: Number of node order issues found
     10 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
     11 target triple = "hexagon"
     12 
     13 define i32 @foo(i16* noalias nocapture %src, i16* noalias nocapture %dstImg, i32 %width, i32 %idx, i32 %flush) #0 {
     14 entry:
     15   %0 = tail call i64 @llvm.hexagon.A2.combinew(i32 %flush, i32 %flush)
     16   %1 = bitcast i64 %0 to <2 x i32>
     17   br label %polly.loop_body
     18 
     19 polly.loop_after:                                 ; preds = %polly.loop_body
     20   ret i32 0
     21 
     22 polly.loop_body:                                  ; preds = %entry, %polly.loop_body
     23   %p_arrayidx35.phi = phi i16* [ %dstImg, %entry ], [ %p_arrayidx35.inc, %polly.loop_body ]
     24   %p_arrayidx.phi = phi i16* [ %src, %entry ], [ %p_arrayidx.inc, %polly.loop_body ]
     25   %polly.loopiv56 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
     26   %polly.next_loopiv = add nsw i32 %polly.loopiv56, 4
     27   %vector_ptr = bitcast i16* %p_arrayidx.phi to <4 x i16>*
     28   %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2
     29   %_high_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
     30   %_low_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
     31   %2 = zext <2 x i16> %_low_half to <2 x i32>
     32   %3 = zext <2 x i16> %_high_half to <2 x i32>
     33   %add33p_vec = add <2 x i32> %2, %1
     34   %add33p_vec48 = add <2 x i32> %3, %1
     35   %4 = trunc <2 x i32> %add33p_vec to <2 x i16>
     36   %5 = trunc <2 x i32> %add33p_vec48 to <2 x i16>
     37   %_combined_vec = shufflevector <2 x i16> %4, <2 x i16> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
     38   %vector_ptr49 = bitcast i16* %p_arrayidx35.phi to <4 x i16>*
     39   store <4 x i16> %_combined_vec, <4 x i16>* %vector_ptr49, align 2
     40   %6 = icmp slt i32 %polly.next_loopiv, 1024
     41   %p_arrayidx35.inc = getelementptr i16, i16* %p_arrayidx35.phi, i32 4
     42   %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 4
     43   br i1 %6, label %polly.loop_body, label %polly.loop_after
     44 }
     45 
     46 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
     47 
     48 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
     49 attributes #1 = { nounwind readnone }
     50 
     51 
     52