1 ; RUN: llc -march=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s 2 3 define i64 @cins_zext(i32 signext %n) { 4 entry: 5 %shl = shl i32 %n, 5 6 %conv = zext i32 %shl to i64 7 ret i64 %conv 8 9 ; CHECK-LABEL: cins_zext: 10 ; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 26 11 12 } 13 14 define i64 @cins_and_shl(i64 zeroext %n) { 15 entry: 16 %and = shl i64 %n, 8 17 %shl = and i64 %and, 16776960 18 ret i64 %shl 19 20 ; CHECK-LABEL: cins_and_shl: 21 ; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 15 22 23 } 24 25 define i64 @cins_and_shl32(i64 zeroext %n) { 26 entry: 27 %and = shl i64 %n, 38 28 %shl = and i64 %and, 18014123631575040 29 ret i64 %shl 30 31 ; CHECK-LABEL: cins_and_shl32: 32 ; CHECK: cins32 $[[R0:[0-9]+]], $[[R1:[0-9]+]], 6, 15 33 34 } 35 36 define zeroext i16 @cins_and_shl_16(i16 zeroext %n) { 37 entry: 38 %0 = shl i16 %n, 2 39 %1 = and i16 %0, 60 40 ret i16 %1 41 42 ; CHECK-LABEL: cins_and_shl_16: 43 ; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 3 44 45 } 46 47 define zeroext i8 @cins_and_shl_8(i8 zeroext %n) { 48 entry: 49 %0 = shl i8 %n, 2 50 %1 = and i8 %0, 12 51 ret i8 %1 52 53 ; CHECK-LABEL: cins_and_shl_8: 54 ; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 1 55 56 } 57 58 define i32 @cins_i32(i32 signext %a) { 59 entry: 60 %and = shl i32 %a, 17 61 %shl = and i32 %and, 536739840 62 ret i32 %shl 63 64 ; CHECK-LABEL: cins_i32: 65 ; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 17, 11 66 67 } 68 69 define i64 @cins_shl_and(i32 signext %n) { 70 entry: 71 %and = and i32 %n, 65535 72 %conv = zext i32 %and to i64 73 %shl = shl nuw nsw i64 %conv, 31 74 ret i64 %shl 75 76 ; CHECK-LABEL: cins_shl_and: 77 ; CHECK: cins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 31, 15 78 79 } 80 81 82 define i64 @cins_shl_and32(i32 signext %n) { 83 entry: 84 %and = and i32 %n, 65535 85 %conv = zext i32 %and to i64 86 %shl = shl nuw nsw i64 %conv, 47 87 ret i64 %shl 88 89 ; CHECK-LABEL: cins_shl_and32: 90 ; CHECK: cins32 $[[R0:[0-9]+]], $[[R1:[0-9]+]], 15, 15 91 92 } 93
