1 ; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ 2 ; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2 3 ; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \ 4 ; RUN: | FileCheck %s -check-prefix=MIPS32R2 5 ; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \ 6 ; RUN: | FileCheck %s -check-prefix=MIPS16 7 ; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ 8 ; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32 9 10 ; #include <stdint.h> 11 ; #include <stdio.h> 12 ; struct cvmx_buf_ptr { 13 14 ; struct { 15 ; unsigned long long addr :37; 16 ; unsigned long long addr1 :15; 17 ; unsigned int length:14; 18 ; uint64_t total_bytes:16; 19 ; uint64_t segs : 6; 20 ; } s; 21 ; } 22 ; 23 ; unsigned long long foo(volatile struct cvmx_buf_ptr bufptr) { 24 ; bufptr.s.addr = 123; 25 ; bufptr.s.segs = 4; 26 ; bufptr.s.length = 5; 27 ; bufptr.s.total_bytes = bufptr.s.length; 28 ; return bufptr.s.addr; 29 ; } 30 31 ; Testing of selection INS/DINS instruction 32 33 define i64 @f123(i64 inreg %bufptr.coerce0, i64 inreg %bufptr.coerce1) local_unnamed_addr #0 { 34 entry: 35 %bufptr.sroa.0 = alloca i64, align 8 36 %bufptr.sroa.4 = alloca i64, align 8 37 store i64 %bufptr.coerce0, i64* %bufptr.sroa.0, align 8 38 store i64 %bufptr.coerce1, i64* %bufptr.sroa.4, align 8 39 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load = load volatile i64, i64* %bufptr.sroa.0, align 8 40 %bf.clear = and i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load, 134217727 41 %bf.set = or i64 %bf.clear, 16508780544 42 store volatile i64 %bf.set, i64* %bufptr.sroa.0, align 8 43 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2 = load volatile i64, i64* %bufptr.sroa.4, align 8 44 %bf.clear3 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2, -16911433729 45 %bf.set4 = or i64 %bf.clear3, 1073741824 46 store volatile i64 %bf.set4, i64* %bufptr.sroa.4, align 8 47 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6 = load volatile i64, i64* %bufptr.sroa.4, align 8 48 %bf.clear7 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6, 1125899906842623 49 %bf.set8 = or i64 %bf.clear7, 5629499534213120 50 store volatile i64 %bf.set8, i64* %bufptr.sroa.4, align 8 51 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11 = load volatile i64, i64* %bufptr.sroa.4, align 8 52 %bf.lshr = lshr i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11, 50 53 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load13 = load volatile i64, i64* %bufptr.sroa.4, align 8 54 %bf.shl = shl nuw nsw i64 %bf.lshr, 34 55 %bf.clear14 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load13, -1125882726973441 56 %bf.set15 = or i64 %bf.clear14, %bf.shl 57 store volatile i64 %bf.set15, i64* %bufptr.sroa.4, align 8 58 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17 = load volatile i64, i64* %bufptr.sroa.0, align 8 59 %bf.lshr18 = lshr i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17, 27 60 ret i64 %bf.lshr18 61 } 62 63 ; CHECK-LABEL: f123: 64 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 123 65 ; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37 66 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 4 67 ; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6 68 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5 69 ; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14 70 ; MIPS64R2: dsrl $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50 71 ; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16 72 ; MIPS32R2: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 16 73 ; MIPS32R2-NOT: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 18, 46 74 ; MIPS16-NOT: ins{{[[:space:]].*}} 75 76 77 ; int foo(volatile int x) { 78 ; int y = x; 79 ; y = y & -4; 80 ; x = y | 8; 81 ; return y; 82 ; } 83 84 define i32 @foo(i32 signext %x) { 85 entry: 86 %x.addr = alloca i32, align 4 87 store volatile i32 %x, i32* %x.addr, align 4 88 %x.addr.0.x.addr.0. = load volatile i32, i32* %x.addr, align 4 89 %and = and i32 %x.addr.0.x.addr.0., -4 90 %or = or i32 %and, 8 91 store volatile i32 %or, i32* %x.addr, align 4 92 ret i32 %and 93 } 94 95 ; CHECK-LABEL: foo: 96 ; MIPS64R2: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8 97 ; MIPS64R2-NOT: ins {{[[:space:]].*}} 98 ; MIPS32R2: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8 99 ; MIPS32R2-NOT: ins {{[[:space:]].*}} 100 ; MIPS64R2N32: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8 101 ; MIPS64R2N32-NOT: ins {{[[:space:]].*}} 102
