1 ; RUN: llc -mcpu=mips32r2 -march=mipsel -relocation-model=static -o - %s | FileCheck %s 2 3 define void @isr_sw0() #0 { 4 ; CHECK-LABEL: isr_sw0: 5 ; CHECK: mfc0 $27, $14, 0 6 ; CHECK: sw $27, [[R1:[0-9]+]]($sp) 7 ; CHECK: mfc0 $27, $12, 0 8 ; CHECK: sw $27, [[R2:[0-9]+]]($sp) 9 ; CHECK: ins $27, $zero, 8, 1 10 ; CHECK: ins $27, $zero, 1, 4 11 ; CHECK: ins $27, $zero, 29, 1 12 ; CHECK: mtc0 $27, $12, 0 13 ; Must save all registers 14 ; CHECK: sw $7, {{[0-9]+}}($sp) 15 ; CHECK: sw $6, {{[0-9]+}}($sp) 16 ; CHECK: sw $5, {{[0-9]+}}($sp) 17 ; CHECK: sw $4, {{[0-9]+}}($sp) 18 ; CHECK: sw $3, {{[0-9]+}}($sp) 19 ; CHECK: sw $2, {{[0-9]+}}($sp) 20 ; CHECK: sw $25, {{[0-9]+}}($sp) 21 ; CHECK: sw $24, {{[0-9]+}}($sp) 22 ; CHECK: sw $15, {{[0-9]+}}($sp) 23 ; CHECK: sw $14, {{[0-9]+}}($sp) 24 ; CHECK: sw $13, {{[0-9]+}}($sp) 25 ; CHECK: sw $12, {{[0-9]+}}($sp) 26 ; CHECK: sw $11, {{[0-9]+}}($sp) 27 ; CHECK: sw $10, {{[0-9]+}}($sp) 28 ; CHECK: sw $9, {{[0-9]+}}($sp) 29 ; CHECK: sw $8, {{[0-9]+}}($sp) 30 ; CHECK: sw $ra, [[R5:[0-9]+]]($sp) 31 ; CHECK: sw $gp, {{[0-9]+}}($sp) 32 ; CHECK: sw $1, {{[0-9]+}}($sp) 33 ; CHECK: mflo $26 34 ; CHECK: sw $26, [[R3:[0-9]+]]($sp) 35 ; CHECK: mfhi $26 36 ; CHECK: sw $26, [[R4:[0-9]+]]($sp) 37 call void bitcast (void (...)* @write to void ()*)() 38 ; CHECK: lw $26, [[R4:[0-9]+]]($sp) 39 ; CHECK: mthi $26 40 ; CHECK: lw $26, [[R3:[0-9]+]]($sp) 41 ; CHECK: mtlo $26 42 ; CHECK: lw $1, {{[0-9]+}}($sp) 43 ; CHECK: lw $gp, {{[0-9]+}}($sp) 44 ; CHECK: lw $ra, [[R5:[0-9]+]]($sp) 45 ; CHECK: lw $8, {{[0-9]+}}($sp) 46 ; CHECK: lw $9, {{[0-9]+}}($sp) 47 ; CHECK: lw $10, {{[0-9]+}}($sp) 48 ; CHECK: lw $11, {{[0-9]+}}($sp) 49 ; CHECK: lw $12, {{[0-9]+}}($sp) 50 ; CHECK: lw $13, {{[0-9]+}}($sp) 51 ; CHECK: lw $14, {{[0-9]+}}($sp) 52 ; CHECK: lw $15, {{[0-9]+}}($sp) 53 ; CHECK: lw $24, {{[0-9]+}}($sp) 54 ; CHECK: lw $25, {{[0-9]+}}($sp) 55 ; CHECK: lw $2, {{[0-9]+}}($sp) 56 ; CHECK: lw $3, {{[0-9]+}}($sp) 57 ; CHECK: lw $4, {{[0-9]+}}($sp) 58 ; CHECK: lw $5, {{[0-9]+}}($sp) 59 ; CHECK: lw $6, {{[0-9]+}}($sp) 60 ; CHECK: lw $7, {{[0-9]+}}($sp) 61 ; CHECK: di 62 ; CHECK: ehb 63 ; CHECK: lw $27, [[R2:[0-9]+]]($sp) 64 ; CHECK: mtc0 $27, $14, 0 65 ; CHECK: lw $27, [[R1:[0-9]+]]($sp) 66 ; CHECK: mtc0 $27, $12, 0 67 ; CHECK: eret 68 ret void 69 } 70 71 declare void @write(...) 72 73 define void @isr_sw1() #2 { 74 ; CHECK-LABEL: isr_sw1: 75 ; CHECK: mfc0 $27, $14, 0 76 ; CHECK: sw $27, {{[0-9]+}}($sp) 77 ; CHECK: mfc0 $27, $12, 0 78 ; CHECK: sw $27, {{[0-9]+}}($sp) 79 ; CHECK: ins $27, $zero, 8, 2 80 ; CHECK: ins $27, $zero, 1, 4 81 ; CHECK: ins $27, $zero, 29, 1 82 ; CHECK: mtc0 $27, $12, 0 83 ret void 84 ; CHECK: di 85 ; CHECK: ehb 86 ; CHECK: lw $27, {{[0-9]+}}($sp) 87 ; CHECK: mtc0 $27, $14, 0 88 ; CHECK: lw $27, {{[0-9]+}}($sp) 89 ; CHECK: mtc0 $27, $12, 0 90 ; CHECK: eret 91 } 92 93 define void @isr_hw0() #3 { 94 ; CHECK-LABEL: isr_hw0: 95 ; CHECK: mfc0 $27, $14, 0 96 ; CHECK: sw $27, {{[0-9]+}}($sp) 97 ; CHECK: mfc0 $27, $12, 0 98 ; CHECK: sw $27, {{[0-9]+}}($sp) 99 ; CHECK: ins $27, $zero, 8, 3 100 ; CHECK: ins $27, $zero, 1, 4 101 ; CHECK: ins $27, $zero, 29, 1 102 ; CHECK: mtc0 $27, $12, 0 103 ret void 104 ; CHECK: di 105 ; CHECK: ehb 106 ; CHECK: lw $27, {{[0-9]+}}($sp) 107 ; CHECK: mtc0 $27, $14, 0 108 ; CHECK: lw $27, {{[0-9]+}}($sp) 109 ; CHECK: mtc0 $27, $12, 0 110 ; CHECK: eret 111 } 112 113 define void @isr_hw1() #4 { 114 ; CHECK-LABEL: isr_hw1: 115 ; CHECK: mfc0 $27, $14, 0 116 ; CHECK: sw $27, {{[0-9]+}}($sp) 117 ; CHECK: mfc0 $27, $12, 0 118 ; CHECK: sw $27, {{[0-9]+}}($sp) 119 ; CHECK: ins $27, $zero, 8, 4 120 ; CHECK: ins $27, $zero, 1, 4 121 ; CHECK: ins $27, $zero, 29, 1 122 ; CHECK: mtc0 $27, $12, 0 123 ret void 124 ; CHECK: di 125 ; CHECK: ehb 126 ; CHECK: lw $27, {{[0-9]+}}($sp) 127 ; CHECK: mtc0 $27, $14, 0 128 ; CHECK: lw $27, {{[0-9]+}}($sp) 129 ; CHECK: mtc0 $27, $12, 0 130 ; CHECK: eret 131 } 132 133 134 define void @isr_hw2() #5 { 135 ; CHECK-LABEL: isr_hw2: 136 ; CHECK: mfc0 $27, $14, 0 137 ; CHECK: sw $27, {{[0-9]+}}($sp) 138 ; CHECK: mfc0 $27, $12, 0 139 ; CHECK: sw $27, {{[0-9]+}}($sp) 140 ; CHECK: ins $27, $zero, 8, 5 141 ; CHECK: ins $27, $zero, 1, 4 142 ; CHECK: ins $27, $zero, 29, 1 143 ; CHECK: mtc0 $27, $12, 0 144 ret void 145 ; CHECK: di 146 ; CHECK: ehb 147 ; CHECK: lw $27, {{[0-9]+}}($sp) 148 ; CHECK: mtc0 $27, $14, 0 149 ; CHECK: lw $27, {{[0-9]+}}($sp) 150 ; CHECK: mtc0 $27, $12, 0 151 ; CHECK: eret 152 } 153 154 define void @isr_hw3() #6 { 155 ; CHECK-LABEL: isr_hw3: 156 ; CHECK: mfc0 $27, $14, 0 157 ; CHECK: sw $27, {{[0-9]+}}($sp) 158 ; CHECK: mfc0 $27, $12, 0 159 ; CHECK: sw $27, {{[0-9]+}}($sp) 160 ; CHECK: ins $27, $zero, 8, 6 161 ; CHECK: ins $27, $zero, 1, 4 162 ; CHECK: ins $27, $zero, 29, 1 163 ; CHECK: mtc0 $27, $12, 0 164 ret void 165 ; CHECK: di 166 ; CHECK: ehb 167 ; CHECK: lw $27, {{[0-9]+}}($sp) 168 ; CHECK: mtc0 $27, $14, 0 169 ; CHECK: lw $27, {{[0-9]+}}($sp) 170 ; CHECK: mtc0 $27, $12, 0 171 ; CHECK: eret 172 } 173 174 define void @isr_hw4() #7 { 175 ; CHECK-LABEL: isr_hw4: 176 ; CHECK: mfc0 $27, $14, 0 177 ; CHECK: sw $27, {{[0-9]+}}($sp) 178 ; CHECK: mfc0 $27, $12, 0 179 ; CHECK: sw $27, {{[0-9]+}}($sp) 180 ; CHECK: ins $27, $zero, 8, 7 181 ; CHECK: ins $27, $zero, 1, 4 182 ; CHECK: ins $27, $zero, 29, 1 183 ; CHECK: mtc0 $27, $12, 0 184 ret void 185 ; CHECK: di 186 ; CHECK: ehb 187 ; CHECK: lw $27, {{[0-9]+}}($sp) 188 ; CHECK: mtc0 $27, $14, 0 189 ; CHECK: lw $27, {{[0-9]+}}($sp) 190 ; CHECK: mtc0 $27, $12, 0 191 ; CHECK: eret 192 } 193 194 define void @isr_hw5() #8 { 195 ; CHECK-LABEL: isr_hw5: 196 ; CHECK: mfc0 $27, $14, 0 197 ; CHECK: sw $27, {{[0-9]+}}($sp) 198 ; CHECK: mfc0 $27, $12, 0 199 ; CHECK: sw $27, {{[0-9]+}}($sp) 200 ; CHECK: ins $27, $zero, 8, 8 201 ; CHECK: ins $27, $zero, 1, 4 202 ; CHECK: ins $27, $zero, 29, 1 203 ; CHECK: mtc0 $27, $12, 0 204 ret void 205 ; CHECK: di 206 ; CHECK: ehb 207 ; CHECK: lw $27, {{[0-9]+}}($sp) 208 ; CHECK: mtc0 $27, $14, 0 209 ; CHECK: lw $27, {{[0-9]+}}($sp) 210 ; CHECK: mtc0 $27, $12, 0 211 ; CHECK: eret 212 } 213 214 define void @isr_eic() #9 { 215 ; CHECK-LABEL: isr_eic: 216 ; CHECK: mfc0 $26, $13, 0 217 ; CHECK: ext $26, $26, 10, 6 218 ; CHECK: mfc0 $27, $14, 0 219 ; CHECK: sw $27, {{[0-9]+}}($sp) 220 ; CHECK: mfc0 $27, $12, 0 221 ; CHECK: sw $27, {{[0-9]+}}($sp) 222 ; CHECK: ins $27, $26, 10, 6 223 ; CHECK: ins $27, $zero, 1, 4 224 ; CHECK: ins $27, $zero, 29, 1 225 ; CHECK: mtc0 $27, $12, 0 226 ret void 227 ; CHECK: di 228 ; CHECK: ehb 229 ; CHECK: lw $27, {{[0-9]+}}($sp) 230 ; CHECK: mtc0 $27, $14, 0 231 ; CHECK: lw $27, {{[0-9]+}}($sp) 232 ; CHECK: mtc0 $27, $12, 0 233 ; CHECK: eret 234 } 235 236 attributes #0 = { "interrupt"="sw0" } 237 attributes #2 = { "interrupt"="sw1" } 238 attributes #3 = { "interrupt"="hw0" } 239 attributes #4 = { "interrupt"="hw1" } 240 attributes #5 = { "interrupt"="hw2" } 241 attributes #6 = { "interrupt"="hw3" } 242 attributes #7 = { "interrupt"="hw4" } 243 attributes #8 = { "interrupt"="hw5" } 244 attributes #9 = { "interrupt"="eic" } 245
