1 ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 2 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 3 ; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM 4 ; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 5 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 6 7 define double @add_d(double %a, double %b) { 8 ; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32 9 ; MIPS32FP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64 10 ; MM: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32_MM 11 ; MMFP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM 12 ; MMR6: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM 13 %1 = fadd double %a, %b 14 ret double %1 15 } 16 17 define double @sub_d(double %a, double %b) { 18 ; MIPS32: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32 19 ; MIPS32FP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64 20 ; MM: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32_MM 21 ; MMFP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM 22 ; MMR6: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM 23 %1 = fsub double %a, %b 24 ret double %1 25 } 26 27 define double @mul_d(double %a, double %b) { 28 ; MIPS32: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32 29 ; MIPS32FP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64 30 ; MM: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32_MM 31 ; MMFP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM 32 ; MMR6: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM 33 %1 = fmul double %a, %b 34 ret double %1 35 } 36 37 define double @div_d(double %a, double %b) { 38 ; MIPS32: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32 39 ; MIPS32FP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64 40 ; MM: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32_MM 41 ; MMFP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM 42 ; MMR6: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM 43 %1 = fdiv double %a, %b 44 ret double %1 45 } 46 47 define double @fneg(double %a) { 48 ; MIPS32: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32 49 ; MIPS32FP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64 50 ; MM: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32_MM 51 ; MMFP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM 52 ; MMR6: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM 53 %1 = fsub double -0.000000e+00, %a 54 ret double %1 55 } 56
