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      1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
      2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
      3 ; RUN:    -check-prefix=MIPS
      4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
      5 ; RUN:    -check-prefix=MIPS32
      6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
      7 ; RUN:    -check-prefix=32R2
      8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
      9 ; RUN:    -check-prefix=32R2
     10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
     11 ; RUN:    -check-prefix=32R2
     12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
     13 ; RUN:    -check-prefix=32R6
     14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
     15 ; RUN:    -check-prefix=MIPS3
     16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
     17 ; RUN:    -check-prefix=MIPS64
     18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
     19 ; RUN:    -check-prefix=MIPS64
     20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
     21 ; RUN:    -check-prefix=MIPS64R2
     22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
     23 ; RUN:    -check-prefix=MIPS64R2
     24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
     25 ; RUN:    -check-prefix=MIPS64R2
     26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
     27 ; RUN:    -check-prefix=MIPS64R6
     28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
     29 ; RUN:    -check-prefix=MMR3
     30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
     31 ; RUN:    -check-prefix=MMR6
     32 
     33 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
     34 ; MIPS-LABEL: ashr_i1:
     35 ; MIPS:       # %bb.0: # %entry
     36 ; MIPS-NEXT:    jr $ra
     37 ; MIPS-NEXT:    move $2, $4
     38 ;
     39 ; MIPS32-LABEL: ashr_i1:
     40 ; MIPS32:       # %bb.0: # %entry
     41 ; MIPS32-NEXT:    jr $ra
     42 ; MIPS32-NEXT:    move $2, $4
     43 ;
     44 ; 32R2-LABEL: ashr_i1:
     45 ; 32R2:       # %bb.0: # %entry
     46 ; 32R2-NEXT:    jr $ra
     47 ; 32R2-NEXT:    move $2, $4
     48 ;
     49 ; 32R6-LABEL: ashr_i1:
     50 ; 32R6:       # %bb.0: # %entry
     51 ; 32R6-NEXT:    jr $ra
     52 ; 32R6-NEXT:    move $2, $4
     53 ;
     54 ; MIPS3-LABEL: ashr_i1:
     55 ; MIPS3:       # %bb.0: # %entry
     56 ; MIPS3-NEXT:    jr $ra
     57 ; MIPS3-NEXT:    move $2, $4
     58 ;
     59 ; MIPS64-LABEL: ashr_i1:
     60 ; MIPS64:       # %bb.0: # %entry
     61 ; MIPS64-NEXT:    jr $ra
     62 ; MIPS64-NEXT:    move $2, $4
     63 ;
     64 ; MIPS64R2-LABEL: ashr_i1:
     65 ; MIPS64R2:       # %bb.0: # %entry
     66 ; MIPS64R2-NEXT:    jr $ra
     67 ; MIPS64R2-NEXT:    move $2, $4
     68 ;
     69 ; MIPS64R6-LABEL: ashr_i1:
     70 ; MIPS64R6:       # %bb.0: # %entry
     71 ; MIPS64R6-NEXT:    jr $ra
     72 ; MIPS64R6-NEXT:    move $2, $4
     73 ;
     74 ; MMR3-LABEL: ashr_i1:
     75 ; MMR3:       # %bb.0: # %entry
     76 ; MMR3-NEXT:    move $2, $4
     77 ; MMR3-NEXT:    jrc $ra
     78 ;
     79 ; MMR6-LABEL: ashr_i1:
     80 ; MMR6:       # %bb.0: # %entry
     81 ; MMR6-NEXT:    move $2, $4
     82 ; MMR6-NEXT:    jrc $ra
     83 entry:
     84   %r = ashr i1 %a, %b
     85   ret i1 %r
     86 }
     87 
     88 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
     89 ; MIPS-LABEL: ashr_i8:
     90 ; MIPS:       # %bb.0: # %entry
     91 ; MIPS-NEXT:    andi $1, $5, 255
     92 ; MIPS-NEXT:    jr $ra
     93 ; MIPS-NEXT:    srav $2, $4, $1
     94 ;
     95 ; MIPS32-LABEL: ashr_i8:
     96 ; MIPS32:       # %bb.0: # %entry
     97 ; MIPS32-NEXT:    andi $1, $5, 255
     98 ; MIPS32-NEXT:    jr $ra
     99 ; MIPS32-NEXT:    srav $2, $4, $1
    100 ;
    101 ; 32R2-LABEL: ashr_i8:
    102 ; 32R2:       # %bb.0: # %entry
    103 ; 32R2-NEXT:    andi $1, $5, 255
    104 ; 32R2-NEXT:    jr $ra
    105 ; 32R2-NEXT:    srav $2, $4, $1
    106 ;
    107 ; 32R6-LABEL: ashr_i8:
    108 ; 32R6:       # %bb.0: # %entry
    109 ; 32R6-NEXT:    andi $1, $5, 255
    110 ; 32R6-NEXT:    jr $ra
    111 ; 32R6-NEXT:    srav $2, $4, $1
    112 ;
    113 ; MIPS3-LABEL: ashr_i8:
    114 ; MIPS3:       # %bb.0: # %entry
    115 ; MIPS3-NEXT:    andi $1, $5, 255
    116 ; MIPS3-NEXT:    jr $ra
    117 ; MIPS3-NEXT:    srav $2, $4, $1
    118 ;
    119 ; MIPS64-LABEL: ashr_i8:
    120 ; MIPS64:       # %bb.0: # %entry
    121 ; MIPS64-NEXT:    andi $1, $5, 255
    122 ; MIPS64-NEXT:    jr $ra
    123 ; MIPS64-NEXT:    srav $2, $4, $1
    124 ;
    125 ; MIPS64R2-LABEL: ashr_i8:
    126 ; MIPS64R2:       # %bb.0: # %entry
    127 ; MIPS64R2-NEXT:    andi $1, $5, 255
    128 ; MIPS64R2-NEXT:    jr $ra
    129 ; MIPS64R2-NEXT:    srav $2, $4, $1
    130 ;
    131 ; MIPS64R6-LABEL: ashr_i8:
    132 ; MIPS64R6:       # %bb.0: # %entry
    133 ; MIPS64R6-NEXT:    andi $1, $5, 255
    134 ; MIPS64R6-NEXT:    jr $ra
    135 ; MIPS64R6-NEXT:    srav $2, $4, $1
    136 ;
    137 ; MMR3-LABEL: ashr_i8:
    138 ; MMR3:       # %bb.0: # %entry
    139 ; MMR3-NEXT:    andi16 $2, $5, 255
    140 ; MMR3-NEXT:    jr $ra
    141 ; MMR3-NEXT:    srav $2, $4, $2
    142 ;
    143 ; MMR6-LABEL: ashr_i8:
    144 ; MMR6:       # %bb.0: # %entry
    145 ; MMR6-NEXT:    andi16 $2, $5, 255
    146 ; MMR6-NEXT:    srav $2, $4, $2
    147 ; MMR6-NEXT:    jrc $ra
    148 entry:
    149   ; FIXME: The andi instruction is redundant.
    150   %r = ashr i8 %a, %b
    151   ret i8 %r
    152 }
    153 
    154 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
    155 ; MIPS-LABEL: ashr_i16:
    156 ; MIPS:       # %bb.0: # %entry
    157 ; MIPS-NEXT:    andi $1, $5, 65535
    158 ; MIPS-NEXT:    jr $ra
    159 ; MIPS-NEXT:    srav $2, $4, $1
    160 ;
    161 ; MIPS32-LABEL: ashr_i16:
    162 ; MIPS32:       # %bb.0: # %entry
    163 ; MIPS32-NEXT:    andi $1, $5, 65535
    164 ; MIPS32-NEXT:    jr $ra
    165 ; MIPS32-NEXT:    srav $2, $4, $1
    166 ;
    167 ; 32R2-LABEL: ashr_i16:
    168 ; 32R2:       # %bb.0: # %entry
    169 ; 32R2-NEXT:    andi $1, $5, 65535
    170 ; 32R2-NEXT:    jr $ra
    171 ; 32R2-NEXT:    srav $2, $4, $1
    172 ;
    173 ; 32R6-LABEL: ashr_i16:
    174 ; 32R6:       # %bb.0: # %entry
    175 ; 32R6-NEXT:    andi $1, $5, 65535
    176 ; 32R6-NEXT:    jr $ra
    177 ; 32R6-NEXT:    srav $2, $4, $1
    178 ;
    179 ; MIPS3-LABEL: ashr_i16:
    180 ; MIPS3:       # %bb.0: # %entry
    181 ; MIPS3-NEXT:    andi $1, $5, 65535
    182 ; MIPS3-NEXT:    jr $ra
    183 ; MIPS3-NEXT:    srav $2, $4, $1
    184 ;
    185 ; MIPS64-LABEL: ashr_i16:
    186 ; MIPS64:       # %bb.0: # %entry
    187 ; MIPS64-NEXT:    andi $1, $5, 65535
    188 ; MIPS64-NEXT:    jr $ra
    189 ; MIPS64-NEXT:    srav $2, $4, $1
    190 ;
    191 ; MIPS64R2-LABEL: ashr_i16:
    192 ; MIPS64R2:       # %bb.0: # %entry
    193 ; MIPS64R2-NEXT:    andi $1, $5, 65535
    194 ; MIPS64R2-NEXT:    jr $ra
    195 ; MIPS64R2-NEXT:    srav $2, $4, $1
    196 ;
    197 ; MIPS64R6-LABEL: ashr_i16:
    198 ; MIPS64R6:       # %bb.0: # %entry
    199 ; MIPS64R6-NEXT:    andi $1, $5, 65535
    200 ; MIPS64R6-NEXT:    jr $ra
    201 ; MIPS64R6-NEXT:    srav $2, $4, $1
    202 ;
    203 ; MMR3-LABEL: ashr_i16:
    204 ; MMR3:       # %bb.0: # %entry
    205 ; MMR3-NEXT:    andi16 $2, $5, 65535
    206 ; MMR3-NEXT:    jr $ra
    207 ; MMR3-NEXT:    srav $2, $4, $2
    208 ;
    209 ; MMR6-LABEL: ashr_i16:
    210 ; MMR6:       # %bb.0: # %entry
    211 ; MMR6-NEXT:    andi16 $2, $5, 65535
    212 ; MMR6-NEXT:    srav $2, $4, $2
    213 ; MMR6-NEXT:    jrc $ra
    214 entry:
    215   ; FIXME: The andi instruction is redundant.
    216   %r = ashr i16 %a, %b
    217   ret i16 %r
    218 }
    219 
    220 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
    221 ; MIPS-LABEL: ashr_i32:
    222 ; MIPS:       # %bb.0: # %entry
    223 ; MIPS-NEXT:    jr $ra
    224 ; MIPS-NEXT:    srav $2, $4, $5
    225 ;
    226 ; MIPS32-LABEL: ashr_i32:
    227 ; MIPS32:       # %bb.0: # %entry
    228 ; MIPS32-NEXT:    jr $ra
    229 ; MIPS32-NEXT:    srav $2, $4, $5
    230 ;
    231 ; 32R2-LABEL: ashr_i32:
    232 ; 32R2:       # %bb.0: # %entry
    233 ; 32R2-NEXT:    jr $ra
    234 ; 32R2-NEXT:    srav $2, $4, $5
    235 ;
    236 ; 32R6-LABEL: ashr_i32:
    237 ; 32R6:       # %bb.0: # %entry
    238 ; 32R6-NEXT:    jr $ra
    239 ; 32R6-NEXT:    srav $2, $4, $5
    240 ;
    241 ; MIPS3-LABEL: ashr_i32:
    242 ; MIPS3:       # %bb.0: # %entry
    243 ; MIPS3-NEXT:    jr $ra
    244 ; MIPS3-NEXT:    srav $2, $4, $5
    245 ;
    246 ; MIPS64-LABEL: ashr_i32:
    247 ; MIPS64:       # %bb.0: # %entry
    248 ; MIPS64-NEXT:    jr $ra
    249 ; MIPS64-NEXT:    srav $2, $4, $5
    250 ;
    251 ; MIPS64R2-LABEL: ashr_i32:
    252 ; MIPS64R2:       # %bb.0: # %entry
    253 ; MIPS64R2-NEXT:    jr $ra
    254 ; MIPS64R2-NEXT:    srav $2, $4, $5
    255 ;
    256 ; MIPS64R6-LABEL: ashr_i32:
    257 ; MIPS64R6:       # %bb.0: # %entry
    258 ; MIPS64R6-NEXT:    jr $ra
    259 ; MIPS64R6-NEXT:    srav $2, $4, $5
    260 ;
    261 ; MMR3-LABEL: ashr_i32:
    262 ; MMR3:       # %bb.0: # %entry
    263 ; MMR3-NEXT:    jr $ra
    264 ; MMR3-NEXT:    srav $2, $4, $5
    265 ;
    266 ; MMR6-LABEL: ashr_i32:
    267 ; MMR6:       # %bb.0: # %entry
    268 ; MMR6-NEXT:    srav $2, $4, $5
    269 ; MMR6-NEXT:    jrc $ra
    270 entry:
    271   %r = ashr i32 %a, %b
    272   ret i32 %r
    273 }
    274 
    275 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
    276 ; MIPS-LABEL: ashr_i64:
    277 ; MIPS:       # %bb.0: # %entry
    278 ; MIPS-NEXT:    srav $2, $4, $7
    279 ; MIPS-NEXT:    andi $6, $7, 32
    280 ; MIPS-NEXT:    beqz $6, $BB4_3
    281 ; MIPS-NEXT:    move $3, $2
    282 ; MIPS-NEXT:  # %bb.1: # %entry
    283 ; MIPS-NEXT:    bnez $6, $BB4_4
    284 ; MIPS-NEXT:    nop
    285 ; MIPS-NEXT:  $BB4_2: # %entry
    286 ; MIPS-NEXT:    jr $ra
    287 ; MIPS-NEXT:    nop
    288 ; MIPS-NEXT:  $BB4_3: # %entry
    289 ; MIPS-NEXT:    srlv $1, $5, $7
    290 ; MIPS-NEXT:    not $3, $7
    291 ; MIPS-NEXT:    sll $5, $4, 1
    292 ; MIPS-NEXT:    sllv $3, $5, $3
    293 ; MIPS-NEXT:    beqz $6, $BB4_2
    294 ; MIPS-NEXT:    or $3, $3, $1
    295 ; MIPS-NEXT:  $BB4_4:
    296 ; MIPS-NEXT:    jr $ra
    297 ; MIPS-NEXT:    sra $2, $4, 31
    298 ;
    299 ; MIPS32-LABEL: ashr_i64:
    300 ; MIPS32:       # %bb.0: # %entry
    301 ; MIPS32-NEXT:    srlv $1, $5, $7
    302 ; MIPS32-NEXT:    not $2, $7
    303 ; MIPS32-NEXT:    sll $3, $4, 1
    304 ; MIPS32-NEXT:    sllv $2, $3, $2
    305 ; MIPS32-NEXT:    or $3, $2, $1
    306 ; MIPS32-NEXT:    srav $2, $4, $7
    307 ; MIPS32-NEXT:    andi $1, $7, 32
    308 ; MIPS32-NEXT:    movn $3, $2, $1
    309 ; MIPS32-NEXT:    sra $4, $4, 31
    310 ; MIPS32-NEXT:    jr $ra
    311 ; MIPS32-NEXT:    movn $2, $4, $1
    312 ;
    313 ; 32R2-LABEL: ashr_i64:
    314 ; 32R2:       # %bb.0: # %entry
    315 ; 32R2-NEXT:    srlv $1, $5, $7
    316 ; 32R2-NEXT:    not $2, $7
    317 ; 32R2-NEXT:    sll $3, $4, 1
    318 ; 32R2-NEXT:    sllv $2, $3, $2
    319 ; 32R2-NEXT:    or $3, $2, $1
    320 ; 32R2-NEXT:    srav $2, $4, $7
    321 ; 32R2-NEXT:    andi $1, $7, 32
    322 ; 32R2-NEXT:    movn $3, $2, $1
    323 ; 32R2-NEXT:    sra $4, $4, 31
    324 ; 32R2-NEXT:    jr $ra
    325 ; 32R2-NEXT:    movn $2, $4, $1
    326 ;
    327 ; 32R6-LABEL: ashr_i64:
    328 ; 32R6:       # %bb.0: # %entry
    329 ; 32R6-NEXT:    srav $1, $4, $7
    330 ; 32R6-NEXT:    andi $3, $7, 32
    331 ; 32R6-NEXT:    seleqz $2, $1, $3
    332 ; 32R6-NEXT:    sra $6, $4, 31
    333 ; 32R6-NEXT:    selnez $6, $6, $3
    334 ; 32R6-NEXT:    or $2, $6, $2
    335 ; 32R6-NEXT:    srlv $5, $5, $7
    336 ; 32R6-NEXT:    not $6, $7
    337 ; 32R6-NEXT:    sll $4, $4, 1
    338 ; 32R6-NEXT:    sllv $4, $4, $6
    339 ; 32R6-NEXT:    or $4, $4, $5
    340 ; 32R6-NEXT:    seleqz $4, $4, $3
    341 ; 32R6-NEXT:    selnez $1, $1, $3
    342 ; 32R6-NEXT:    jr $ra
    343 ; 32R6-NEXT:    or $3, $1, $4
    344 ;
    345 ; MIPS3-LABEL: ashr_i64:
    346 ; MIPS3:       # %bb.0: # %entry
    347 ; MIPS3-NEXT:    jr $ra
    348 ; MIPS3-NEXT:    dsrav $2, $4, $5
    349 ;
    350 ; MIPS64-LABEL: ashr_i64:
    351 ; MIPS64:       # %bb.0: # %entry
    352 ; MIPS64-NEXT:    jr $ra
    353 ; MIPS64-NEXT:    dsrav $2, $4, $5
    354 ;
    355 ; MIPS64R2-LABEL: ashr_i64:
    356 ; MIPS64R2:       # %bb.0: # %entry
    357 ; MIPS64R2-NEXT:    jr $ra
    358 ; MIPS64R2-NEXT:    dsrav $2, $4, $5
    359 ;
    360 ; MIPS64R6-LABEL: ashr_i64:
    361 ; MIPS64R6:       # %bb.0: # %entry
    362 ; MIPS64R6-NEXT:    jr $ra
    363 ; MIPS64R6-NEXT:    dsrav $2, $4, $5
    364 ;
    365 ; MMR3-LABEL: ashr_i64:
    366 ; MMR3:       # %bb.0: # %entry
    367 ; MMR3-NEXT:    srlv $2, $5, $7
    368 ; MMR3-NEXT:    not16 $3, $7
    369 ; MMR3-NEXT:    sll16 $5, $4, 1
    370 ; MMR3-NEXT:    sllv $3, $5, $3
    371 ; MMR3-NEXT:    or16 $3, $2
    372 ; MMR3-NEXT:    srav $2, $4, $7
    373 ; MMR3-NEXT:    andi16 $5, $7, 32
    374 ; MMR3-NEXT:    movn $3, $2, $5
    375 ; MMR3-NEXT:    sra $1, $4, 31
    376 ; MMR3-NEXT:    jr $ra
    377 ; MMR3-NEXT:    movn $2, $1, $5
    378 ;
    379 ; MMR6-LABEL: ashr_i64:
    380 ; MMR6:       # %bb.0: # %entry
    381 ; MMR6-NEXT:    srav $1, $4, $7
    382 ; MMR6-NEXT:    andi16 $3, $7, 32
    383 ; MMR6-NEXT:    seleqz $2, $1, $3
    384 ; MMR6-NEXT:    sra $6, $4, 31
    385 ; MMR6-NEXT:    selnez $6, $6, $3
    386 ; MMR6-NEXT:    or $2, $6, $2
    387 ; MMR6-NEXT:    srlv $5, $5, $7
    388 ; MMR6-NEXT:    not16 $6, $7
    389 ; MMR6-NEXT:    sll16 $4, $4, 1
    390 ; MMR6-NEXT:    sllv $4, $4, $6
    391 ; MMR6-NEXT:    or $4, $4, $5
    392 ; MMR6-NEXT:    seleqz $4, $4, $3
    393 ; MMR6-NEXT:    selnez $1, $1, $3
    394 ; MMR6-NEXT:    or $3, $1, $4
    395 ; MMR6-NEXT:    jrc $ra
    396 entry:
    397   %r = ashr i64 %a, %b
    398   ret i64 %r
    399 }
    400 
    401 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
    402 ; MIPS-LABEL: ashr_i128:
    403 ; MIPS:       # %bb.0: # %entry
    404 ; MIPS-NEXT:    addiu $sp, $sp, -8
    405 ; MIPS-NEXT:    .cfi_def_cfa_offset 8
    406 ; MIPS-NEXT:    sw $17, 4($sp) # 4-byte Folded Spill
    407 ; MIPS-NEXT:    sw $16, 0($sp) # 4-byte Folded Spill
    408 ; MIPS-NEXT:    .cfi_offset 17, -4
    409 ; MIPS-NEXT:    .cfi_offset 16, -8
    410 ; MIPS-NEXT:    lw $25, 36($sp)
    411 ; MIPS-NEXT:    addiu $1, $zero, 64
    412 ; MIPS-NEXT:    subu $11, $1, $25
    413 ; MIPS-NEXT:    sllv $9, $5, $11
    414 ; MIPS-NEXT:    andi $13, $11, 32
    415 ; MIPS-NEXT:    addiu $2, $zero, 0
    416 ; MIPS-NEXT:    bnez $13, $BB5_2
    417 ; MIPS-NEXT:    addiu $3, $zero, 0
    418 ; MIPS-NEXT:  # %bb.1: # %entry
    419 ; MIPS-NEXT:    move $3, $9
    420 ; MIPS-NEXT:  $BB5_2: # %entry
    421 ; MIPS-NEXT:    not $gp, $25
    422 ; MIPS-NEXT:    srlv $12, $6, $25
    423 ; MIPS-NEXT:    andi $8, $25, 32
    424 ; MIPS-NEXT:    bnez $8, $BB5_4
    425 ; MIPS-NEXT:    move $15, $12
    426 ; MIPS-NEXT:  # %bb.3: # %entry
    427 ; MIPS-NEXT:    srlv $1, $7, $25
    428 ; MIPS-NEXT:    sll $10, $6, 1
    429 ; MIPS-NEXT:    sllv $10, $10, $gp
    430 ; MIPS-NEXT:    or $15, $10, $1
    431 ; MIPS-NEXT:  $BB5_4: # %entry
    432 ; MIPS-NEXT:    addiu $10, $25, -64
    433 ; MIPS-NEXT:    sll $17, $4, 1
    434 ; MIPS-NEXT:    srav $14, $4, $10
    435 ; MIPS-NEXT:    andi $24, $10, 32
    436 ; MIPS-NEXT:    bnez $24, $BB5_6
    437 ; MIPS-NEXT:    move $16, $14
    438 ; MIPS-NEXT:  # %bb.5: # %entry
    439 ; MIPS-NEXT:    srlv $1, $5, $10
    440 ; MIPS-NEXT:    not $10, $10
    441 ; MIPS-NEXT:    sllv $10, $17, $10
    442 ; MIPS-NEXT:    or $16, $10, $1
    443 ; MIPS-NEXT:  $BB5_6: # %entry
    444 ; MIPS-NEXT:    sltiu $10, $25, 64
    445 ; MIPS-NEXT:    beqz $10, $BB5_8
    446 ; MIPS-NEXT:    nop
    447 ; MIPS-NEXT:  # %bb.7:
    448 ; MIPS-NEXT:    or $16, $15, $3
    449 ; MIPS-NEXT:  $BB5_8: # %entry
    450 ; MIPS-NEXT:    srav $15, $4, $25
    451 ; MIPS-NEXT:    beqz $8, $BB5_20
    452 ; MIPS-NEXT:    move $3, $15
    453 ; MIPS-NEXT:  # %bb.9: # %entry
    454 ; MIPS-NEXT:    sltiu $gp, $25, 1
    455 ; MIPS-NEXT:    beqz $gp, $BB5_21
    456 ; MIPS-NEXT:    nop
    457 ; MIPS-NEXT:  $BB5_10: # %entry
    458 ; MIPS-NEXT:    beqz $10, $BB5_22
    459 ; MIPS-NEXT:    sra $25, $4, 31
    460 ; MIPS-NEXT:  $BB5_11: # %entry
    461 ; MIPS-NEXT:    beqz $13, $BB5_23
    462 ; MIPS-NEXT:    nop
    463 ; MIPS-NEXT:  $BB5_12: # %entry
    464 ; MIPS-NEXT:    beqz $8, $BB5_24
    465 ; MIPS-NEXT:    nop
    466 ; MIPS-NEXT:  $BB5_13: # %entry
    467 ; MIPS-NEXT:    beqz $24, $BB5_25
    468 ; MIPS-NEXT:    move $4, $25
    469 ; MIPS-NEXT:  $BB5_14: # %entry
    470 ; MIPS-NEXT:    bnez $10, $BB5_26
    471 ; MIPS-NEXT:    nop
    472 ; MIPS-NEXT:  $BB5_15: # %entry
    473 ; MIPS-NEXT:    beqz $gp, $BB5_27
    474 ; MIPS-NEXT:    nop
    475 ; MIPS-NEXT:  $BB5_16: # %entry
    476 ; MIPS-NEXT:    beqz $8, $BB5_28
    477 ; MIPS-NEXT:    move $2, $25
    478 ; MIPS-NEXT:  $BB5_17: # %entry
    479 ; MIPS-NEXT:    bnez $10, $BB5_19
    480 ; MIPS-NEXT:    nop
    481 ; MIPS-NEXT:  $BB5_18: # %entry
    482 ; MIPS-NEXT:    move $2, $25
    483 ; MIPS-NEXT:  $BB5_19: # %entry
    484 ; MIPS-NEXT:    move $4, $6
    485 ; MIPS-NEXT:    move $5, $7
    486 ; MIPS-NEXT:    lw $16, 0($sp) # 4-byte Folded Reload
    487 ; MIPS-NEXT:    lw $17, 4($sp) # 4-byte Folded Reload
    488 ; MIPS-NEXT:    jr $ra
    489 ; MIPS-NEXT:    addiu $sp, $sp, 8
    490 ; MIPS-NEXT:  $BB5_20: # %entry
    491 ; MIPS-NEXT:    srlv $1, $5, $25
    492 ; MIPS-NEXT:    sllv $3, $17, $gp
    493 ; MIPS-NEXT:    sltiu $gp, $25, 1
    494 ; MIPS-NEXT:    bnez $gp, $BB5_10
    495 ; MIPS-NEXT:    or $3, $3, $1
    496 ; MIPS-NEXT:  $BB5_21: # %entry
    497 ; MIPS-NEXT:    move $7, $16
    498 ; MIPS-NEXT:    bnez $10, $BB5_11
    499 ; MIPS-NEXT:    sra $25, $4, 31
    500 ; MIPS-NEXT:  $BB5_22: # %entry
    501 ; MIPS-NEXT:    bnez $13, $BB5_12
    502 ; MIPS-NEXT:    move $3, $25
    503 ; MIPS-NEXT:  $BB5_23: # %entry
    504 ; MIPS-NEXT:    not $1, $11
    505 ; MIPS-NEXT:    srl $5, $5, 1
    506 ; MIPS-NEXT:    sllv $4, $4, $11
    507 ; MIPS-NEXT:    srlv $1, $5, $1
    508 ; MIPS-NEXT:    bnez $8, $BB5_13
    509 ; MIPS-NEXT:    or $9, $4, $1
    510 ; MIPS-NEXT:  $BB5_24: # %entry
    511 ; MIPS-NEXT:    move $2, $12
    512 ; MIPS-NEXT:    bnez $24, $BB5_14
    513 ; MIPS-NEXT:    move $4, $25
    514 ; MIPS-NEXT:  $BB5_25: # %entry
    515 ; MIPS-NEXT:    beqz $10, $BB5_15
    516 ; MIPS-NEXT:    move $4, $14
    517 ; MIPS-NEXT:  $BB5_26:
    518 ; MIPS-NEXT:    bnez $gp, $BB5_16
    519 ; MIPS-NEXT:    or $4, $2, $9
    520 ; MIPS-NEXT:  $BB5_27: # %entry
    521 ; MIPS-NEXT:    move $6, $4
    522 ; MIPS-NEXT:    bnez $8, $BB5_17
    523 ; MIPS-NEXT:    move $2, $25
    524 ; MIPS-NEXT:  $BB5_28: # %entry
    525 ; MIPS-NEXT:    bnez $10, $BB5_19
    526 ; MIPS-NEXT:    move $2, $15
    527 ; MIPS-NEXT:  # %bb.29: # %entry
    528 ; MIPS-NEXT:    b $BB5_18
    529 ; MIPS-NEXT:    nop
    530 ;
    531 ; MIPS32-LABEL: ashr_i128:
    532 ; MIPS32:       # %bb.0: # %entry
    533 ; MIPS32-NEXT:    lw $9, 28($sp)
    534 ; MIPS32-NEXT:    srlv $1, $7, $9
    535 ; MIPS32-NEXT:    not $2, $9
    536 ; MIPS32-NEXT:    sll $3, $6, 1
    537 ; MIPS32-NEXT:    sllv $3, $3, $2
    538 ; MIPS32-NEXT:    addiu $8, $zero, 64
    539 ; MIPS32-NEXT:    or $1, $3, $1
    540 ; MIPS32-NEXT:    srlv $10, $6, $9
    541 ; MIPS32-NEXT:    subu $3, $8, $9
    542 ; MIPS32-NEXT:    sllv $11, $5, $3
    543 ; MIPS32-NEXT:    andi $12, $3, 32
    544 ; MIPS32-NEXT:    andi $13, $9, 32
    545 ; MIPS32-NEXT:    move $8, $11
    546 ; MIPS32-NEXT:    movn $8, $zero, $12
    547 ; MIPS32-NEXT:    movn $1, $10, $13
    548 ; MIPS32-NEXT:    addiu $14, $9, -64
    549 ; MIPS32-NEXT:    srlv $15, $5, $14
    550 ; MIPS32-NEXT:    sll $24, $4, 1
    551 ; MIPS32-NEXT:    not $25, $14
    552 ; MIPS32-NEXT:    sllv $25, $24, $25
    553 ; MIPS32-NEXT:    or $gp, $1, $8
    554 ; MIPS32-NEXT:    or $1, $25, $15
    555 ; MIPS32-NEXT:    srav $8, $4, $14
    556 ; MIPS32-NEXT:    andi $14, $14, 32
    557 ; MIPS32-NEXT:    movn $1, $8, $14
    558 ; MIPS32-NEXT:    sllv $15, $4, $3
    559 ; MIPS32-NEXT:    not $3, $3
    560 ; MIPS32-NEXT:    srl $25, $5, 1
    561 ; MIPS32-NEXT:    srlv $3, $25, $3
    562 ; MIPS32-NEXT:    sltiu $25, $9, 64
    563 ; MIPS32-NEXT:    movn $1, $gp, $25
    564 ; MIPS32-NEXT:    or $15, $15, $3
    565 ; MIPS32-NEXT:    srlv $3, $5, $9
    566 ; MIPS32-NEXT:    sllv $2, $24, $2
    567 ; MIPS32-NEXT:    or $5, $2, $3
    568 ; MIPS32-NEXT:    srav $24, $4, $9
    569 ; MIPS32-NEXT:    movn $5, $24, $13
    570 ; MIPS32-NEXT:    sra $2, $4, 31
    571 ; MIPS32-NEXT:    movz $1, $7, $9
    572 ; MIPS32-NEXT:    move $3, $2
    573 ; MIPS32-NEXT:    movn $3, $5, $25
    574 ; MIPS32-NEXT:    movn $15, $11, $12
    575 ; MIPS32-NEXT:    movn $10, $zero, $13
    576 ; MIPS32-NEXT:    or $4, $10, $15
    577 ; MIPS32-NEXT:    movn $8, $2, $14
    578 ; MIPS32-NEXT:    movn $8, $4, $25
    579 ; MIPS32-NEXT:    movz $8, $6, $9
    580 ; MIPS32-NEXT:    movn $24, $2, $13
    581 ; MIPS32-NEXT:    movn $2, $24, $25
    582 ; MIPS32-NEXT:    move $4, $8
    583 ; MIPS32-NEXT:    jr $ra
    584 ; MIPS32-NEXT:    move $5, $1
    585 ;
    586 ; 32R2-LABEL: ashr_i128:
    587 ; 32R2:       # %bb.0: # %entry
    588 ; 32R2-NEXT:    lw $9, 28($sp)
    589 ; 32R2-NEXT:    srlv $1, $7, $9
    590 ; 32R2-NEXT:    not $2, $9
    591 ; 32R2-NEXT:    sll $3, $6, 1
    592 ; 32R2-NEXT:    sllv $3, $3, $2
    593 ; 32R2-NEXT:    addiu $8, $zero, 64
    594 ; 32R2-NEXT:    or $1, $3, $1
    595 ; 32R2-NEXT:    srlv $10, $6, $9
    596 ; 32R2-NEXT:    subu $3, $8, $9
    597 ; 32R2-NEXT:    sllv $11, $5, $3
    598 ; 32R2-NEXT:    andi $12, $3, 32
    599 ; 32R2-NEXT:    andi $13, $9, 32
    600 ; 32R2-NEXT:    move $8, $11
    601 ; 32R2-NEXT:    movn $8, $zero, $12
    602 ; 32R2-NEXT:    movn $1, $10, $13
    603 ; 32R2-NEXT:    addiu $14, $9, -64
    604 ; 32R2-NEXT:    srlv $15, $5, $14
    605 ; 32R2-NEXT:    sll $24, $4, 1
    606 ; 32R2-NEXT:    not $25, $14
    607 ; 32R2-NEXT:    sllv $25, $24, $25
    608 ; 32R2-NEXT:    or $gp, $1, $8
    609 ; 32R2-NEXT:    or $1, $25, $15
    610 ; 32R2-NEXT:    srav $8, $4, $14
    611 ; 32R2-NEXT:    andi $14, $14, 32
    612 ; 32R2-NEXT:    movn $1, $8, $14
    613 ; 32R2-NEXT:    sllv $15, $4, $3
    614 ; 32R2-NEXT:    not $3, $3
    615 ; 32R2-NEXT:    srl $25, $5, 1
    616 ; 32R2-NEXT:    srlv $3, $25, $3
    617 ; 32R2-NEXT:    sltiu $25, $9, 64
    618 ; 32R2-NEXT:    movn $1, $gp, $25
    619 ; 32R2-NEXT:    or $15, $15, $3
    620 ; 32R2-NEXT:    srlv $3, $5, $9
    621 ; 32R2-NEXT:    sllv $2, $24, $2
    622 ; 32R2-NEXT:    or $5, $2, $3
    623 ; 32R2-NEXT:    srav $24, $4, $9
    624 ; 32R2-NEXT:    movn $5, $24, $13
    625 ; 32R2-NEXT:    sra $2, $4, 31
    626 ; 32R2-NEXT:    movz $1, $7, $9
    627 ; 32R2-NEXT:    move $3, $2
    628 ; 32R2-NEXT:    movn $3, $5, $25
    629 ; 32R2-NEXT:    movn $15, $11, $12
    630 ; 32R2-NEXT:    movn $10, $zero, $13
    631 ; 32R2-NEXT:    or $4, $10, $15
    632 ; 32R2-NEXT:    movn $8, $2, $14
    633 ; 32R2-NEXT:    movn $8, $4, $25
    634 ; 32R2-NEXT:    movz $8, $6, $9
    635 ; 32R2-NEXT:    movn $24, $2, $13
    636 ; 32R2-NEXT:    movn $2, $24, $25
    637 ; 32R2-NEXT:    move $4, $8
    638 ; 32R2-NEXT:    jr $ra
    639 ; 32R2-NEXT:    move $5, $1
    640 ;
    641 ; 32R6-LABEL: ashr_i128:
    642 ; 32R6:       # %bb.0: # %entry
    643 ; 32R6-NEXT:    lw $3, 28($sp)
    644 ; 32R6-NEXT:    addiu $1, $zero, 64
    645 ; 32R6-NEXT:    subu $1, $1, $3
    646 ; 32R6-NEXT:    sllv $2, $5, $1
    647 ; 32R6-NEXT:    andi $8, $1, 32
    648 ; 32R6-NEXT:    selnez $9, $2, $8
    649 ; 32R6-NEXT:    sllv $10, $4, $1
    650 ; 32R6-NEXT:    not $1, $1
    651 ; 32R6-NEXT:    srl $11, $5, 1
    652 ; 32R6-NEXT:    srlv $1, $11, $1
    653 ; 32R6-NEXT:    or $1, $10, $1
    654 ; 32R6-NEXT:    seleqz $1, $1, $8
    655 ; 32R6-NEXT:    or $1, $9, $1
    656 ; 32R6-NEXT:    srlv $9, $7, $3
    657 ; 32R6-NEXT:    not $10, $3
    658 ; 32R6-NEXT:    sll $11, $6, 1
    659 ; 32R6-NEXT:    sllv $11, $11, $10
    660 ; 32R6-NEXT:    or $9, $11, $9
    661 ; 32R6-NEXT:    andi $11, $3, 32
    662 ; 32R6-NEXT:    seleqz $9, $9, $11
    663 ; 32R6-NEXT:    srlv $12, $6, $3
    664 ; 32R6-NEXT:    selnez $13, $12, $11
    665 ; 32R6-NEXT:    seleqz $12, $12, $11
    666 ; 32R6-NEXT:    or $1, $12, $1
    667 ; 32R6-NEXT:    seleqz $2, $2, $8
    668 ; 32R6-NEXT:    or $8, $13, $9
    669 ; 32R6-NEXT:    addiu $9, $3, -64
    670 ; 32R6-NEXT:    srlv $12, $5, $9
    671 ; 32R6-NEXT:    sll $13, $4, 1
    672 ; 32R6-NEXT:    not $14, $9
    673 ; 32R6-NEXT:    sllv $14, $13, $14
    674 ; 32R6-NEXT:    sltiu $15, $3, 64
    675 ; 32R6-NEXT:    or $2, $8, $2
    676 ; 32R6-NEXT:    selnez $1, $1, $15
    677 ; 32R6-NEXT:    or $8, $14, $12
    678 ; 32R6-NEXT:    srav $12, $4, $9
    679 ; 32R6-NEXT:    andi $9, $9, 32
    680 ; 32R6-NEXT:    seleqz $14, $12, $9
    681 ; 32R6-NEXT:    sra $24, $4, 31
    682 ; 32R6-NEXT:    selnez $25, $24, $9
    683 ; 32R6-NEXT:    seleqz $8, $8, $9
    684 ; 32R6-NEXT:    or $14, $25, $14
    685 ; 32R6-NEXT:    seleqz $14, $14, $15
    686 ; 32R6-NEXT:    selnez $9, $12, $9
    687 ; 32R6-NEXT:    seleqz $12, $24, $15
    688 ; 32R6-NEXT:    or $1, $1, $14
    689 ; 32R6-NEXT:    selnez $14, $1, $3
    690 ; 32R6-NEXT:    selnez $1, $2, $15
    691 ; 32R6-NEXT:    or $2, $9, $8
    692 ; 32R6-NEXT:    srav $8, $4, $3
    693 ; 32R6-NEXT:    seleqz $4, $8, $11
    694 ; 32R6-NEXT:    selnez $9, $24, $11
    695 ; 32R6-NEXT:    or $4, $9, $4
    696 ; 32R6-NEXT:    selnez $9, $4, $15
    697 ; 32R6-NEXT:    seleqz $2, $2, $15
    698 ; 32R6-NEXT:    seleqz $4, $6, $3
    699 ; 32R6-NEXT:    seleqz $6, $7, $3
    700 ; 32R6-NEXT:    or $1, $1, $2
    701 ; 32R6-NEXT:    selnez $1, $1, $3
    702 ; 32R6-NEXT:    or $1, $6, $1
    703 ; 32R6-NEXT:    or $4, $4, $14
    704 ; 32R6-NEXT:    or $2, $9, $12
    705 ; 32R6-NEXT:    srlv $3, $5, $3
    706 ; 32R6-NEXT:    sllv $5, $13, $10
    707 ; 32R6-NEXT:    or $3, $5, $3
    708 ; 32R6-NEXT:    seleqz $3, $3, $11
    709 ; 32R6-NEXT:    selnez $5, $8, $11
    710 ; 32R6-NEXT:    or $3, $5, $3
    711 ; 32R6-NEXT:    selnez $3, $3, $15
    712 ; 32R6-NEXT:    or $3, $3, $12
    713 ; 32R6-NEXT:    jr $ra
    714 ; 32R6-NEXT:    move $5, $1
    715 ;
    716 ; MIPS3-LABEL: ashr_i128:
    717 ; MIPS3:       # %bb.0: # %entry
    718 ; MIPS3-NEXT:    sll $8, $7, 0
    719 ; MIPS3-NEXT:    dsrav $2, $4, $7
    720 ; MIPS3-NEXT:    andi $6, $8, 64
    721 ; MIPS3-NEXT:    beqz $6, .LBB5_3
    722 ; MIPS3-NEXT:    move $3, $2
    723 ; MIPS3-NEXT:  # %bb.1: # %entry
    724 ; MIPS3-NEXT:    bnez $6, .LBB5_4
    725 ; MIPS3-NEXT:    nop
    726 ; MIPS3-NEXT:  .LBB5_2: # %entry
    727 ; MIPS3-NEXT:    jr $ra
    728 ; MIPS3-NEXT:    nop
    729 ; MIPS3-NEXT:  .LBB5_3: # %entry
    730 ; MIPS3-NEXT:    dsrlv $1, $5, $7
    731 ; MIPS3-NEXT:    dsll $3, $4, 1
    732 ; MIPS3-NEXT:    not $5, $8
    733 ; MIPS3-NEXT:    dsllv $3, $3, $5
    734 ; MIPS3-NEXT:    beqz $6, .LBB5_2
    735 ; MIPS3-NEXT:    or $3, $3, $1
    736 ; MIPS3-NEXT:  .LBB5_4:
    737 ; MIPS3-NEXT:    jr $ra
    738 ; MIPS3-NEXT:    dsra $2, $4, 63
    739 ;
    740 ; MIPS64-LABEL: ashr_i128:
    741 ; MIPS64:       # %bb.0: # %entry
    742 ; MIPS64-NEXT:    dsrlv $1, $5, $7
    743 ; MIPS64-NEXT:    dsll $2, $4, 1
    744 ; MIPS64-NEXT:    sll $5, $7, 0
    745 ; MIPS64-NEXT:    not $3, $5
    746 ; MIPS64-NEXT:    dsllv $2, $2, $3
    747 ; MIPS64-NEXT:    or $3, $2, $1
    748 ; MIPS64-NEXT:    dsrav $2, $4, $7
    749 ; MIPS64-NEXT:    andi $1, $5, 64
    750 ; MIPS64-NEXT:    movn $3, $2, $1
    751 ; MIPS64-NEXT:    dsra $4, $4, 63
    752 ; MIPS64-NEXT:    jr $ra
    753 ; MIPS64-NEXT:    movn $2, $4, $1
    754 ;
    755 ; MIPS64R2-LABEL: ashr_i128:
    756 ; MIPS64R2:       # %bb.0: # %entry
    757 ; MIPS64R2-NEXT:    dsrlv $1, $5, $7
    758 ; MIPS64R2-NEXT:    dsll $2, $4, 1
    759 ; MIPS64R2-NEXT:    sll $5, $7, 0
    760 ; MIPS64R2-NEXT:    not $3, $5
    761 ; MIPS64R2-NEXT:    dsllv $2, $2, $3
    762 ; MIPS64R2-NEXT:    or $3, $2, $1
    763 ; MIPS64R2-NEXT:    dsrav $2, $4, $7
    764 ; MIPS64R2-NEXT:    andi $1, $5, 64
    765 ; MIPS64R2-NEXT:    movn $3, $2, $1
    766 ; MIPS64R2-NEXT:    dsra $4, $4, 63
    767 ; MIPS64R2-NEXT:    jr $ra
    768 ; MIPS64R2-NEXT:    movn $2, $4, $1
    769 ;
    770 ; MIPS64R6-LABEL: ashr_i128:
    771 ; MIPS64R6:       # %bb.0: # %entry
    772 ; MIPS64R6-NEXT:    dsrav $1, $4, $7
    773 ; MIPS64R6-NEXT:    sll $3, $7, 0
    774 ; MIPS64R6-NEXT:    andi $2, $3, 64
    775 ; MIPS64R6-NEXT:    sll $6, $2, 0
    776 ; MIPS64R6-NEXT:    seleqz $2, $1, $6
    777 ; MIPS64R6-NEXT:    dsra $8, $4, 63
    778 ; MIPS64R6-NEXT:    selnez $8, $8, $6
    779 ; MIPS64R6-NEXT:    or $2, $8, $2
    780 ; MIPS64R6-NEXT:    dsrlv $5, $5, $7
    781 ; MIPS64R6-NEXT:    dsll $4, $4, 1
    782 ; MIPS64R6-NEXT:    not $3, $3
    783 ; MIPS64R6-NEXT:    dsllv $3, $4, $3
    784 ; MIPS64R6-NEXT:    or $3, $3, $5
    785 ; MIPS64R6-NEXT:    seleqz $3, $3, $6
    786 ; MIPS64R6-NEXT:    selnez $1, $1, $6
    787 ; MIPS64R6-NEXT:    jr $ra
    788 ; MIPS64R6-NEXT:    or $3, $1, $3
    789 ;
    790 ; MMR3-LABEL: ashr_i128:
    791 ; MMR3:       # %bb.0: # %entry
    792 ; MMR3-NEXT:    addiusp -48
    793 ; MMR3-NEXT:    .cfi_def_cfa_offset 48
    794 ; MMR3-NEXT:    swp $16, 40($sp)
    795 ; MMR3-NEXT:    .cfi_offset 17, -4
    796 ; MMR3-NEXT:    .cfi_offset 16, -8
    797 ; MMR3-NEXT:    move $8, $7
    798 ; MMR3-NEXT:    sw $6, 32($sp) # 4-byte Folded Spill
    799 ; MMR3-NEXT:    sw $5, 36($sp) # 4-byte Folded Spill
    800 ; MMR3-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
    801 ; MMR3-NEXT:    lw $16, 76($sp)
    802 ; MMR3-NEXT:    srlv $4, $7, $16
    803 ; MMR3-NEXT:    not16 $3, $16
    804 ; MMR3-NEXT:    sw $3, 24($sp) # 4-byte Folded Spill
    805 ; MMR3-NEXT:    sll16 $2, $6, 1
    806 ; MMR3-NEXT:    sllv $3, $2, $3
    807 ; MMR3-NEXT:    li16 $2, 64
    808 ; MMR3-NEXT:    or16 $3, $4
    809 ; MMR3-NEXT:    srlv $6, $6, $16
    810 ; MMR3-NEXT:    sw $6, 12($sp) # 4-byte Folded Spill
    811 ; MMR3-NEXT:    subu16 $7, $2, $16
    812 ; MMR3-NEXT:    sllv $9, $5, $7
    813 ; MMR3-NEXT:    andi16 $2, $7, 32
    814 ; MMR3-NEXT:    sw $2, 28($sp) # 4-byte Folded Spill
    815 ; MMR3-NEXT:    andi16 $5, $16, 32
    816 ; MMR3-NEXT:    sw $5, 16($sp) # 4-byte Folded Spill
    817 ; MMR3-NEXT:    move $4, $9
    818 ; MMR3-NEXT:    li16 $17, 0
    819 ; MMR3-NEXT:    movn $4, $17, $2
    820 ; MMR3-NEXT:    movn $3, $6, $5
    821 ; MMR3-NEXT:    addiu $2, $16, -64
    822 ; MMR3-NEXT:    lw $5, 36($sp) # 4-byte Folded Reload
    823 ; MMR3-NEXT:    srlv $5, $5, $2
    824 ; MMR3-NEXT:    sw $5, 20($sp) # 4-byte Folded Spill
    825 ; MMR3-NEXT:    lw $17, 8($sp) # 4-byte Folded Reload
    826 ; MMR3-NEXT:    sll16 $6, $17, 1
    827 ; MMR3-NEXT:    sw $6, 4($sp) # 4-byte Folded Spill
    828 ; MMR3-NEXT:    not16 $5, $2
    829 ; MMR3-NEXT:    sllv $5, $6, $5
    830 ; MMR3-NEXT:    or16 $3, $4
    831 ; MMR3-NEXT:    lw $4, 20($sp) # 4-byte Folded Reload
    832 ; MMR3-NEXT:    or16 $5, $4
    833 ; MMR3-NEXT:    srav $1, $17, $2
    834 ; MMR3-NEXT:    andi16 $2, $2, 32
    835 ; MMR3-NEXT:    sw $2, 20($sp) # 4-byte Folded Spill
    836 ; MMR3-NEXT:    movn $5, $1, $2
    837 ; MMR3-NEXT:    sllv $2, $17, $7
    838 ; MMR3-NEXT:    not16 $4, $7
    839 ; MMR3-NEXT:    lw $7, 36($sp) # 4-byte Folded Reload
    840 ; MMR3-NEXT:    srl16 $6, $7, 1
    841 ; MMR3-NEXT:    srlv $6, $6, $4
    842 ; MMR3-NEXT:    sltiu $10, $16, 64
    843 ; MMR3-NEXT:    movn $5, $3, $10
    844 ; MMR3-NEXT:    or16 $6, $2
    845 ; MMR3-NEXT:    srlv $2, $7, $16
    846 ; MMR3-NEXT:    lw $3, 24($sp) # 4-byte Folded Reload
    847 ; MMR3-NEXT:    lw $4, 4($sp) # 4-byte Folded Reload
    848 ; MMR3-NEXT:    sllv $3, $4, $3
    849 ; MMR3-NEXT:    or16 $3, $2
    850 ; MMR3-NEXT:    srav $11, $17, $16
    851 ; MMR3-NEXT:    lw $4, 16($sp) # 4-byte Folded Reload
    852 ; MMR3-NEXT:    movn $3, $11, $4
    853 ; MMR3-NEXT:    sra $2, $17, 31
    854 ; MMR3-NEXT:    movz $5, $8, $16
    855 ; MMR3-NEXT:    move $8, $2
    856 ; MMR3-NEXT:    movn $8, $3, $10
    857 ; MMR3-NEXT:    lw $3, 28($sp) # 4-byte Folded Reload
    858 ; MMR3-NEXT:    movn $6, $9, $3
    859 ; MMR3-NEXT:    li16 $3, 0
    860 ; MMR3-NEXT:    lw $7, 12($sp) # 4-byte Folded Reload
    861 ; MMR3-NEXT:    movn $7, $3, $4
    862 ; MMR3-NEXT:    or16 $7, $6
    863 ; MMR3-NEXT:    lw $3, 20($sp) # 4-byte Folded Reload
    864 ; MMR3-NEXT:    movn $1, $2, $3
    865 ; MMR3-NEXT:    movn $1, $7, $10
    866 ; MMR3-NEXT:    lw $3, 32($sp) # 4-byte Folded Reload
    867 ; MMR3-NEXT:    movz $1, $3, $16
    868 ; MMR3-NEXT:    movn $11, $2, $4
    869 ; MMR3-NEXT:    movn $2, $11, $10
    870 ; MMR3-NEXT:    move $3, $8
    871 ; MMR3-NEXT:    move $4, $1
    872 ; MMR3-NEXT:    lwp $16, 40($sp)
    873 ; MMR3-NEXT:    addiusp 48
    874 ; MMR3-NEXT:    jrc $ra
    875 ;
    876 ; MMR6-LABEL: ashr_i128:
    877 ; MMR6:       # %bb.0: # %entry
    878 ; MMR6-NEXT:    addiu $sp, $sp, -16
    879 ; MMR6-NEXT:    .cfi_def_cfa_offset 16
    880 ; MMR6-NEXT:    sw $17, 12($sp) # 4-byte Folded Spill
    881 ; MMR6-NEXT:    sw $16, 8($sp) # 4-byte Folded Spill
    882 ; MMR6-NEXT:    .cfi_offset 17, -4
    883 ; MMR6-NEXT:    .cfi_offset 16, -8
    884 ; MMR6-NEXT:    move $1, $7
    885 ; MMR6-NEXT:    lw $3, 44($sp)
    886 ; MMR6-NEXT:    li16 $2, 64
    887 ; MMR6-NEXT:    subu16 $7, $2, $3
    888 ; MMR6-NEXT:    sllv $8, $5, $7
    889 ; MMR6-NEXT:    andi16 $2, $7, 32
    890 ; MMR6-NEXT:    selnez $9, $8, $2
    891 ; MMR6-NEXT:    sllv $10, $4, $7
    892 ; MMR6-NEXT:    not16 $7, $7
    893 ; MMR6-NEXT:    srl16 $16, $5, 1
    894 ; MMR6-NEXT:    srlv $7, $16, $7
    895 ; MMR6-NEXT:    or $7, $10, $7
    896 ; MMR6-NEXT:    seleqz $7, $7, $2
    897 ; MMR6-NEXT:    or $7, $9, $7
    898 ; MMR6-NEXT:    srlv $9, $1, $3
    899 ; MMR6-NEXT:    not16 $16, $3
    900 ; MMR6-NEXT:    sw $16, 4($sp) # 4-byte Folded Spill
    901 ; MMR6-NEXT:    sll16 $17, $6, 1
    902 ; MMR6-NEXT:    sllv $10, $17, $16
    903 ; MMR6-NEXT:    or $9, $10, $9
    904 ; MMR6-NEXT:    andi16 $17, $3, 32
    905 ; MMR6-NEXT:    seleqz $9, $9, $17
    906 ; MMR6-NEXT:    srlv $10, $6, $3
    907 ; MMR6-NEXT:    selnez $11, $10, $17
    908 ; MMR6-NEXT:    seleqz $10, $10, $17
    909 ; MMR6-NEXT:    or $10, $10, $7
    910 ; MMR6-NEXT:    seleqz $12, $8, $2
    911 ; MMR6-NEXT:    or $8, $11, $9
    912 ; MMR6-NEXT:    addiu $2, $3, -64
    913 ; MMR6-NEXT:    srlv $9, $5, $2
    914 ; MMR6-NEXT:    sll16 $7, $4, 1
    915 ; MMR6-NEXT:    not16 $16, $2
    916 ; MMR6-NEXT:    sllv $11, $7, $16
    917 ; MMR6-NEXT:    sltiu $13, $3, 64
    918 ; MMR6-NEXT:    or $8, $8, $12
    919 ; MMR6-NEXT:    selnez $10, $10, $13
    920 ; MMR6-NEXT:    or $9, $11, $9
    921 ; MMR6-NEXT:    srav $11, $4, $2
    922 ; MMR6-NEXT:    andi16 $2, $2, 32
    923 ; MMR6-NEXT:    seleqz $12, $11, $2
    924 ; MMR6-NEXT:    sra $14, $4, 31
    925 ; MMR6-NEXT:    selnez $15, $14, $2
    926 ; MMR6-NEXT:    seleqz $9, $9, $2
    927 ; MMR6-NEXT:    or $12, $15, $12
    928 ; MMR6-NEXT:    seleqz $12, $12, $13
    929 ; MMR6-NEXT:    selnez $2, $11, $2
    930 ; MMR6-NEXT:    seleqz $11, $14, $13
    931 ; MMR6-NEXT:    or $10, $10, $12
    932 ; MMR6-NEXT:    selnez $10, $10, $3
    933 ; MMR6-NEXT:    selnez $8, $8, $13
    934 ; MMR6-NEXT:    or $2, $2, $9
    935 ; MMR6-NEXT:    srav $9, $4, $3
    936 ; MMR6-NEXT:    seleqz $4, $9, $17
    937 ; MMR6-NEXT:    selnez $12, $14, $17
    938 ; MMR6-NEXT:    or $4, $12, $4
    939 ; MMR6-NEXT:    selnez $12, $4, $13
    940 ; MMR6-NEXT:    seleqz $2, $2, $13
    941 ; MMR6-NEXT:    seleqz $4, $6, $3
    942 ; MMR6-NEXT:    seleqz $1, $1, $3
    943 ; MMR6-NEXT:    or $2, $8, $2
    944 ; MMR6-NEXT:    selnez $2, $2, $3
    945 ; MMR6-NEXT:    or $1, $1, $2
    946 ; MMR6-NEXT:    or $4, $4, $10
    947 ; MMR6-NEXT:    or $2, $12, $11
    948 ; MMR6-NEXT:    srlv $3, $5, $3
    949 ; MMR6-NEXT:    lw $5, 4($sp) # 4-byte Folded Reload
    950 ; MMR6-NEXT:    sllv $5, $7, $5
    951 ; MMR6-NEXT:    or $3, $5, $3
    952 ; MMR6-NEXT:    seleqz $3, $3, $17
    953 ; MMR6-NEXT:    selnez $5, $9, $17
    954 ; MMR6-NEXT:    or $3, $5, $3
    955 ; MMR6-NEXT:    selnez $3, $3, $13
    956 ; MMR6-NEXT:    or $3, $3, $11
    957 ; MMR6-NEXT:    move $5, $1
    958 ; MMR6-NEXT:    lw $16, 8($sp) # 4-byte Folded Reload
    959 ; MMR6-NEXT:    lw $17, 12($sp) # 4-byte Folded Reload
    960 ; MMR6-NEXT:    addiu $sp, $sp, 16
    961 ; MMR6-NEXT:    jrc $ra
    962 entry:
    963 ; o32 shouldn't use TImode helpers.
    964 ; GP32-NOT:       lw        $25, %call16(__ashrti3)($gp)
    965 ; MM-NOT:         lw        $25, %call16(__ashrti3)($2)
    966 
    967   %r = ashr i128 %a, %b
    968   ret i128 %r
    969 }
    970