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      1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
      2 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
      3 ; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
      4 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
      5 ; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
      6 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS3
      7 ; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64
      8 ; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
      9 
     10 ; Test subword and word loads.
     11 
     12 @a = common global i8 0, align 4
     13 @b = common global i16 0, align 4
     14 @c = common global i32 0, align 4
     15 @d = common global i64 0, align 8
     16 
     17 define i8 @f1() {
     18 ; MIPS32-LABEL: f1:
     19 ; MIPS32:       # %bb.0: # %entry
     20 ; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
     21 ; MIPS32-NEXT:    # <MCOperand Reg:1>
     22 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
     23 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
     24 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
     25 ; MIPS32-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
     26 ; MIPS32-NEXT:    # <MCOperand Reg:321>
     27 ; MIPS32-NEXT:    # <MCOperand Reg:1>
     28 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
     29 ;
     30 ; MMR3-LABEL: f1:
     31 ; MMR3:       # %bb.0: # %entry
     32 ; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
     33 ; MMR3-NEXT:    # <MCOperand Reg:1>
     34 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
     35 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
     36 ; MMR3-NEXT:    # <MCOperand Reg:19>>
     37 ; MMR3-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
     38 ; MMR3-NEXT:    # <MCOperand Reg:321>
     39 ; MMR3-NEXT:    # <MCOperand Reg:1>
     40 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
     41 ;
     42 ; MIPS32R6-LABEL: f1:
     43 ; MIPS32R6:       # %bb.0: # %entry
     44 ; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
     45 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
     46 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
     47 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
     48 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
     49 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
     50 ; MIPS32R6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
     51 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
     52 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
     53 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
     54 ;
     55 ; MMR6-LABEL: f1:
     56 ; MMR6:       # %bb.0: # %entry
     57 ; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
     58 ; MMR6-NEXT:    # <MCOperand Reg:1>
     59 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
     60 ; MMR6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
     61 ; MMR6-NEXT:    # <MCOperand Reg:321>
     62 ; MMR6-NEXT:    # <MCOperand Reg:1>
     63 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
     64 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
     65 ; MMR6-NEXT:    # <MCOperand Reg:19>>
     66 ;
     67 ; MIPS3-LABEL: f1:
     68 ; MIPS3:       # %bb.0: # %entry
     69 ; MIPS3-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
     70 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     71 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(a))>>
     72 ; MIPS3-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
     73 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     74 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     75 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(a))>>
     76 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
     77 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     78 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     79 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
     80 ; MIPS3-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
     81 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     82 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     83 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(a))>>
     84 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
     85 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     86 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     87 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
     88 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
     89 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
     90 ; MIPS3-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
     91 ; MIPS3-NEXT:    # <MCOperand Reg:321>
     92 ; MIPS3-NEXT:    # <MCOperand Reg:30>
     93 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(a))>>
     94 ;
     95 ; MIPS64-LABEL: f1:
     96 ; MIPS64:       # %bb.0: # %entry
     97 ; MIPS64-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
     98 ; MIPS64-NEXT:    # <MCOperand Reg:30>
     99 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(a))>>
    100 ; MIPS64-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
    101 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    102 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    103 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(a))>>
    104 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    105 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    106 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    107 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    108 ; MIPS64-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
    109 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    110 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    111 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(a))>>
    112 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    113 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    114 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    115 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    116 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    117 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    118 ; MIPS64-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
    119 ; MIPS64-NEXT:    # <MCOperand Reg:321>
    120 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    121 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(a))>>
    122 ;
    123 ; MIPS64R6-LABEL: f1:
    124 ; MIPS64R6:       # %bb.0: # %entry
    125 ; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
    126 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    127 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
    128 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
    129 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    130 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    131 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
    132 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    133 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    134 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    135 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    136 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
    137 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    138 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    139 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
    140 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    141 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    142 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    143 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    144 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
    145 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
    146 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
    147 ; MIPS64R6-NEXT:    lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
    148 ; MIPS64R6-NEXT:    # <MCOperand Reg:321>
    149 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    150 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
    151 entry:
    152   %0 = load i8, i8 * @a
    153   ret i8 %0
    154 }
    155 
    156 define i32 @f2() {
    157 ; MIPS32-LABEL: f2:
    158 ; MIPS32:       # %bb.0: # %entry
    159 ; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
    160 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    161 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
    162 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    163 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
    164 ; MIPS32-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
    165 ; MIPS32-NEXT:    # <MCOperand Reg:321>
    166 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    167 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
    168 ;
    169 ; MMR3-LABEL: f2:
    170 ; MMR3:       # %bb.0: # %entry
    171 ; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
    172 ; MMR3-NEXT:    # <MCOperand Reg:1>
    173 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
    174 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
    175 ; MMR3-NEXT:    # <MCOperand Reg:19>>
    176 ; MMR3-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
    177 ; MMR3-NEXT:    # <MCOperand Reg:321>
    178 ; MMR3-NEXT:    # <MCOperand Reg:1>
    179 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
    180 ;
    181 ; MIPS32R6-LABEL: f2:
    182 ; MIPS32R6:       # %bb.0: # %entry
    183 ; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
    184 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    185 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
    186 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
    187 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    188 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
    189 ; MIPS32R6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
    190 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
    191 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    192 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
    193 ;
    194 ; MMR6-LABEL: f2:
    195 ; MMR6:       # %bb.0: # %entry
    196 ; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
    197 ; MMR6-NEXT:    # <MCOperand Reg:1>
    198 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
    199 ; MMR6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
    200 ; MMR6-NEXT:    # <MCOperand Reg:321>
    201 ; MMR6-NEXT:    # <MCOperand Reg:1>
    202 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
    203 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
    204 ; MMR6-NEXT:    # <MCOperand Reg:19>>
    205 ;
    206 ; MIPS3-LABEL: f2:
    207 ; MIPS3:       # %bb.0: # %entry
    208 ; MIPS3-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
    209 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    210 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(a))>>
    211 ; MIPS3-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
    212 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    213 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    214 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(a))>>
    215 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    216 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    217 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    218 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    219 ; MIPS3-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
    220 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    221 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    222 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(a))>>
    223 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    224 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    225 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    226 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    227 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    228 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
    229 ; MIPS3-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
    230 ; MIPS3-NEXT:    # <MCOperand Reg:321>
    231 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    232 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(a))>>
    233 ;
    234 ; MIPS64-LABEL: f2:
    235 ; MIPS64:       # %bb.0: # %entry
    236 ; MIPS64-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
    237 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    238 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(a))>>
    239 ; MIPS64-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
    240 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    241 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    242 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(a))>>
    243 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    244 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    245 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    246 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    247 ; MIPS64-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
    248 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    249 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    250 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(a))>>
    251 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    252 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    253 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    254 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    255 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    256 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    257 ; MIPS64-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
    258 ; MIPS64-NEXT:    # <MCOperand Reg:321>
    259 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    260 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(a))>>
    261 ;
    262 ; MIPS64R6-LABEL: f2:
    263 ; MIPS64R6:       # %bb.0: # %entry
    264 ; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
    265 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    266 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
    267 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
    268 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    269 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    270 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
    271 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    272 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    273 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    274 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    275 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
    276 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    277 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    278 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
    279 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    280 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    281 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    282 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    283 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
    284 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
    285 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
    286 ; MIPS64R6-NEXT:    lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
    287 ; MIPS64R6-NEXT:    # <MCOperand Reg:321>
    288 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    289 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
    290 entry:
    291   %0 = load i8, i8 * @a
    292   %1 = sext i8 %0 to i32
    293   ret i32 %1
    294 }
    295 
    296 define i16 @f3() {
    297 ; MIPS32-LABEL: f3:
    298 ; MIPS32:       # %bb.0: # %entry
    299 ; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    300 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    301 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
    302 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    303 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
    304 ; MIPS32-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
    305 ; MIPS32-NEXT:    # <MCOperand Reg:321>
    306 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    307 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
    308 ;
    309 ; MMR3-LABEL: f3:
    310 ; MMR3:       # %bb.0: # %entry
    311 ; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    312 ; MMR3-NEXT:    # <MCOperand Reg:1>
    313 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
    314 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
    315 ; MMR3-NEXT:    # <MCOperand Reg:19>>
    316 ; MMR3-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
    317 ; MMR3-NEXT:    # <MCOperand Reg:321>
    318 ; MMR3-NEXT:    # <MCOperand Reg:1>
    319 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
    320 ;
    321 ; MIPS32R6-LABEL: f3:
    322 ; MIPS32R6:       # %bb.0: # %entry
    323 ; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    324 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    325 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
    326 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
    327 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    328 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
    329 ; MIPS32R6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
    330 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
    331 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    332 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
    333 ;
    334 ; MMR6-LABEL: f3:
    335 ; MMR6:       # %bb.0: # %entry
    336 ; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    337 ; MMR6-NEXT:    # <MCOperand Reg:1>
    338 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
    339 ; MMR6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
    340 ; MMR6-NEXT:    # <MCOperand Reg:321>
    341 ; MMR6-NEXT:    # <MCOperand Reg:1>
    342 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
    343 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
    344 ; MMR6-NEXT:    # <MCOperand Reg:19>>
    345 ;
    346 ; MIPS3-LABEL: f3:
    347 ; MIPS3:       # %bb.0: # %entry
    348 ; MIPS3-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
    349 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    350 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(b))>>
    351 ; MIPS3-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
    352 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    353 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    354 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(b))>>
    355 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    356 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    357 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    358 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    359 ; MIPS3-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
    360 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    361 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    362 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(b))>>
    363 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    364 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    365 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    366 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    367 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    368 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
    369 ; MIPS3-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
    370 ; MIPS3-NEXT:    # <MCOperand Reg:321>
    371 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    372 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(b))>>
    373 ;
    374 ; MIPS64-LABEL: f3:
    375 ; MIPS64:       # %bb.0: # %entry
    376 ; MIPS64-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
    377 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    378 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(b))>>
    379 ; MIPS64-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
    380 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    381 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    382 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(b))>>
    383 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    384 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    385 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    386 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    387 ; MIPS64-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
    388 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    389 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    390 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(b))>>
    391 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    392 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    393 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    394 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    395 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    396 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    397 ; MIPS64-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
    398 ; MIPS64-NEXT:    # <MCOperand Reg:321>
    399 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    400 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(b))>>
    401 ;
    402 ; MIPS64R6-LABEL: f3:
    403 ; MIPS64R6:       # %bb.0: # %entry
    404 ; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
    405 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    406 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
    407 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
    408 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    409 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    410 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
    411 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    412 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    413 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    414 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    415 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
    416 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    417 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    418 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
    419 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    420 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    421 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    422 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    423 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
    424 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
    425 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
    426 ; MIPS64R6-NEXT:    lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
    427 ; MIPS64R6-NEXT:    # <MCOperand Reg:321>
    428 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    429 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
    430 entry:
    431   %0 = load i16, i16 * @b
    432   ret i16 %0
    433 }
    434 
    435 define i32 @f4() {
    436 ; MIPS32-LABEL: f4:
    437 ; MIPS32:       # %bb.0: # %entry
    438 ; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    439 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    440 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
    441 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    442 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
    443 ; MIPS32-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
    444 ; MIPS32-NEXT:    # <MCOperand Reg:321>
    445 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    446 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
    447 ;
    448 ; MMR3-LABEL: f4:
    449 ; MMR3:       # %bb.0: # %entry
    450 ; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    451 ; MMR3-NEXT:    # <MCOperand Reg:1>
    452 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
    453 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
    454 ; MMR3-NEXT:    # <MCOperand Reg:19>>
    455 ; MMR3-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
    456 ; MMR3-NEXT:    # <MCOperand Reg:321>
    457 ; MMR3-NEXT:    # <MCOperand Reg:1>
    458 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
    459 ;
    460 ; MIPS32R6-LABEL: f4:
    461 ; MIPS32R6:       # %bb.0: # %entry
    462 ; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    463 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    464 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
    465 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
    466 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    467 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
    468 ; MIPS32R6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
    469 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
    470 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    471 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
    472 ;
    473 ; MMR6-LABEL: f4:
    474 ; MMR6:       # %bb.0: # %entry
    475 ; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
    476 ; MMR6-NEXT:    # <MCOperand Reg:1>
    477 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
    478 ; MMR6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
    479 ; MMR6-NEXT:    # <MCOperand Reg:321>
    480 ; MMR6-NEXT:    # <MCOperand Reg:1>
    481 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
    482 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
    483 ; MMR6-NEXT:    # <MCOperand Reg:19>>
    484 ;
    485 ; MIPS3-LABEL: f4:
    486 ; MIPS3:       # %bb.0: # %entry
    487 ; MIPS3-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
    488 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    489 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(b))>>
    490 ; MIPS3-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
    491 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    492 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    493 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(b))>>
    494 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    495 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    496 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    497 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    498 ; MIPS3-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
    499 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    500 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    501 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(b))>>
    502 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    503 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    504 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    505 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    506 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    507 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
    508 ; MIPS3-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
    509 ; MIPS3-NEXT:    # <MCOperand Reg:321>
    510 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    511 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(b))>>
    512 ;
    513 ; MIPS64-LABEL: f4:
    514 ; MIPS64:       # %bb.0: # %entry
    515 ; MIPS64-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
    516 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    517 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(b))>>
    518 ; MIPS64-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
    519 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    520 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    521 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(b))>>
    522 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    523 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    524 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    525 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    526 ; MIPS64-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
    527 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    528 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    529 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(b))>>
    530 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    531 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    532 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    533 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    534 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    535 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    536 ; MIPS64-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
    537 ; MIPS64-NEXT:    # <MCOperand Reg:321>
    538 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    539 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(b))>>
    540 ;
    541 ; MIPS64R6-LABEL: f4:
    542 ; MIPS64R6:       # %bb.0: # %entry
    543 ; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
    544 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    545 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
    546 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
    547 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    548 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    549 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
    550 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    551 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    552 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    553 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    554 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
    555 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    556 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    557 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
    558 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    559 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    560 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    561 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    562 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
    563 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
    564 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
    565 ; MIPS64R6-NEXT:    lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
    566 ; MIPS64R6-NEXT:    # <MCOperand Reg:321>
    567 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    568 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
    569 entry:
    570   %0 = load i16, i16 * @b
    571   %1 = sext i16 %0 to i32
    572   ret i32 %1
    573 }
    574 
    575 define i32 @f5() {
    576 ; MIPS32-LABEL: f5:
    577 ; MIPS32:       # %bb.0: # %entry
    578 ; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    579 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    580 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
    581 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    582 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
    583 ; MIPS32-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    584 ; MIPS32-NEXT:    # <MCOperand Reg:321>
    585 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    586 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
    587 ;
    588 ; MMR3-LABEL: f5:
    589 ; MMR3:       # %bb.0: # %entry
    590 ; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    591 ; MMR3-NEXT:    # <MCOperand Reg:1>
    592 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
    593 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
    594 ; MMR3-NEXT:    # <MCOperand Reg:19>>
    595 ; MMR3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
    596 ; MMR3-NEXT:    # <MCOperand Reg:321>
    597 ; MMR3-NEXT:    # <MCOperand Reg:1>
    598 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
    599 ;
    600 ; MIPS32R6-LABEL: f5:
    601 ; MIPS32R6:       # %bb.0: # %entry
    602 ; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    603 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    604 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    605 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
    606 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    607 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
    608 ; MIPS32R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    609 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
    610 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    611 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    612 ;
    613 ; MMR6-LABEL: f5:
    614 ; MMR6:       # %bb.0: # %entry
    615 ; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    616 ; MMR6-NEXT:    # <MCOperand Reg:1>
    617 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    618 ; MMR6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
    619 ; MMR6-NEXT:    # <MCOperand Reg:321>
    620 ; MMR6-NEXT:    # <MCOperand Reg:1>
    621 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    622 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
    623 ; MMR6-NEXT:    # <MCOperand Reg:19>>
    624 ;
    625 ; MIPS3-LABEL: f5:
    626 ; MIPS3:       # %bb.0: # %entry
    627 ; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    628 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    629 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
    630 ; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    631 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    632 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    633 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
    634 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    635 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    636 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    637 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    638 ; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    639 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    640 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    641 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
    642 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    643 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    644 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    645 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    646 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    647 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
    648 ; MIPS3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    649 ; MIPS3-NEXT:    # <MCOperand Reg:321>
    650 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    651 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
    652 ;
    653 ; MIPS64-LABEL: f5:
    654 ; MIPS64:       # %bb.0: # %entry
    655 ; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    656 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    657 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
    658 ; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    659 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    660 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    661 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
    662 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    663 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    664 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    665 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    666 ; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    667 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    668 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    669 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
    670 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    671 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    672 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    673 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    674 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    675 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    676 ; MIPS64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    677 ; MIPS64-NEXT:    # <MCOperand Reg:321>
    678 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    679 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
    680 ;
    681 ; MIPS64R6-LABEL: f5:
    682 ; MIPS64R6:       # %bb.0: # %entry
    683 ; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    684 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    685 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
    686 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    687 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    688 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    689 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
    690 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    691 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    692 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    693 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    694 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    695 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    696 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    697 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    698 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    699 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    700 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    701 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    702 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
    703 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
    704 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
    705 ; MIPS64R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    706 ; MIPS64R6-NEXT:    # <MCOperand Reg:321>
    707 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    708 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    709 entry:
    710   %0 = load i32, i32 * @c
    711   ret i32 %0
    712 }
    713 
    714 define i64 @f6() {
    715 ; MIPS32-LABEL: f6:
    716 ; MIPS32:       # %bb.0: # %entry
    717 ; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    718 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    719 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
    720 ; MIPS32-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    721 ; MIPS32-NEXT:    # <MCOperand Reg:322>
    722 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    723 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
    724 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    725 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
    726 ; MIPS32-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
    727 ; MIPS32-NEXT:    # <MCOperand Reg:321>
    728 ; MIPS32-NEXT:    # <MCOperand Reg:21>
    729 ; MIPS32-NEXT:    # <MCOperand Imm:0>>
    730 ;
    731 ; MMR3-LABEL: f6:
    732 ; MMR3:       # %bb.0: # %entry
    733 ; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    734 ; MMR3-NEXT:    # <MCOperand Reg:1>
    735 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
    736 ; MMR3-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
    737 ; MMR3-NEXT:    # <MCOperand Reg:321>
    738 ; MMR3-NEXT:    # <MCOperand Imm:0>>
    739 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
    740 ; MMR3-NEXT:    # <MCOperand Reg:19>>
    741 ; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
    742 ; MMR3-NEXT:    # <MCOperand Reg:322>
    743 ; MMR3-NEXT:    # <MCOperand Reg:1>
    744 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
    745 ;
    746 ; MIPS32R6-LABEL: f6:
    747 ; MIPS32R6:       # %bb.0: # %entry
    748 ; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    749 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    750 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    751 ; MIPS32R6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    752 ; MIPS32R6-NEXT:    # <MCOperand Reg:322>
    753 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    754 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    755 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
    756 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    757 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
    758 ; MIPS32R6-NEXT:    addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
    759 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
    760 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    761 ; MIPS32R6-NEXT:    # <MCOperand Imm:0>>
    762 ;
    763 ; MMR6-LABEL: f6:
    764 ; MMR6:       # %bb.0: # %entry
    765 ; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    766 ; MMR6-NEXT:    # <MCOperand Reg:1>
    767 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    768 ; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
    769 ; MMR6-NEXT:    # <MCOperand Reg:322>
    770 ; MMR6-NEXT:    # <MCOperand Reg:1>
    771 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    772 ; MMR6-NEXT:    li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
    773 ; MMR6-NEXT:    # <MCOperand Reg:321>
    774 ; MMR6-NEXT:    # <MCOperand Imm:0>>
    775 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
    776 ; MMR6-NEXT:    # <MCOperand Reg:19>>
    777 ;
    778 ; MIPS3-LABEL: f6:
    779 ; MIPS3:       # %bb.0: # %entry
    780 ; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    781 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    782 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
    783 ; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    784 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    785 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    786 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
    787 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    788 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    789 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    790 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    791 ; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    792 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    793 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    794 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
    795 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    796 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    797 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    798 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    799 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    800 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
    801 ; MIPS3-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
    802 ; MIPS3-NEXT:    # <MCOperand Reg:416>
    803 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    804 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
    805 ;
    806 ; MIPS64-LABEL: f6:
    807 ; MIPS64:       # %bb.0: # %entry
    808 ; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    809 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    810 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
    811 ; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    812 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    813 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    814 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
    815 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    816 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    817 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    818 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    819 ; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    820 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    821 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    822 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
    823 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    824 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    825 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    826 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    827 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    828 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    829 ; MIPS64-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
    830 ; MIPS64-NEXT:    # <MCOperand Reg:416>
    831 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    832 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
    833 ;
    834 ; MIPS64R6-LABEL: f6:
    835 ; MIPS64R6:       # %bb.0: # %entry
    836 ; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    837 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    838 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
    839 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    840 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    841 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    842 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
    843 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    844 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    845 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    846 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    847 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    848 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    849 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    850 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    851 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    852 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    853 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    854 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
    855 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
    856 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
    857 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
    858 ; MIPS64R6-NEXT:    lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
    859 ; MIPS64R6-NEXT:    # <MCOperand Reg:416>
    860 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    861 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    862 entry:
    863   %0 = load i32, i32 * @c
    864   %1 = zext i32 %0 to i64
    865   ret i64 %1
    866 }
    867 
    868 define i64 @f7() {
    869 ; MIPS32-LABEL: f7:
    870 ; MIPS32:       # %bb.0: # %entry
    871 ; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    872 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    873 ; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
    874 ; MIPS32-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    875 ; MIPS32-NEXT:    # <MCOperand Reg:322>
    876 ; MIPS32-NEXT:    # <MCOperand Reg:1>
    877 ; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
    878 ; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    879 ; MIPS32-NEXT:    # <MCOperand Reg:19>>
    880 ; MIPS32-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
    881 ; MIPS32-NEXT:    # <MCOperand Reg:321>
    882 ; MIPS32-NEXT:    # <MCOperand Reg:322>
    883 ; MIPS32-NEXT:    # <MCOperand Imm:31>>
    884 ;
    885 ; MMR3-LABEL: f7:
    886 ; MMR3:       # %bb.0: # %entry
    887 ; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    888 ; MMR3-NEXT:    # <MCOperand Reg:1>
    889 ; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
    890 ; MMR3-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
    891 ; MMR3-NEXT:    # <MCOperand Reg:322>
    892 ; MMR3-NEXT:    # <MCOperand Reg:1>
    893 ; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
    894 ; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
    895 ; MMR3-NEXT:    # <MCOperand Reg:19>>
    896 ; MMR3-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
    897 ; MMR3-NEXT:    # <MCOperand Reg:321>
    898 ; MMR3-NEXT:    # <MCOperand Reg:322>
    899 ; MMR3-NEXT:    # <MCOperand Imm:31>>
    900 ;
    901 ; MIPS32R6-LABEL: f7:
    902 ; MIPS32R6:       # %bb.0: # %entry
    903 ; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    904 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    905 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    906 ; MIPS32R6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
    907 ; MIPS32R6-NEXT:    # <MCOperand Reg:322>
    908 ; MIPS32R6-NEXT:    # <MCOperand Reg:1>
    909 ; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    910 ; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
    911 ; MIPS32R6-NEXT:    # <MCOperand Reg:21>
    912 ; MIPS32R6-NEXT:    # <MCOperand Reg:19>>
    913 ; MIPS32R6-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
    914 ; MIPS32R6-NEXT:    # <MCOperand Reg:321>
    915 ; MIPS32R6-NEXT:    # <MCOperand Reg:322>
    916 ; MIPS32R6-NEXT:    # <MCOperand Imm:31>>
    917 ;
    918 ; MMR6-LABEL: f7:
    919 ; MMR6:       # %bb.0: # %entry
    920 ; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
    921 ; MMR6-NEXT:    # <MCOperand Reg:1>
    922 ; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
    923 ; MMR6-NEXT:    lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
    924 ; MMR6-NEXT:    # <MCOperand Reg:322>
    925 ; MMR6-NEXT:    # <MCOperand Reg:1>
    926 ; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
    927 ; MMR6-NEXT:    sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
    928 ; MMR6-NEXT:    # <MCOperand Reg:321>
    929 ; MMR6-NEXT:    # <MCOperand Reg:322>
    930 ; MMR6-NEXT:    # <MCOperand Imm:31>>
    931 ; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
    932 ; MMR6-NEXT:    # <MCOperand Reg:19>>
    933 ;
    934 ; MIPS3-LABEL: f7:
    935 ; MIPS3:       # %bb.0: # %entry
    936 ; MIPS3-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    937 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    938 ; MIPS3-NEXT:    # <MCOperand Expr:(%highest(c))>>
    939 ; MIPS3-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    940 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    941 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    942 ; MIPS3-NEXT:    # <MCOperand Expr:(%higher(c))>>
    943 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    944 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    945 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    946 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    947 ; MIPS3-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    948 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    949 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    950 ; MIPS3-NEXT:    # <MCOperand Expr:(%hi(c))>>
    951 ; MIPS3-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    952 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    953 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    954 ; MIPS3-NEXT:    # <MCOperand Imm:16>>
    955 ; MIPS3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    956 ; MIPS3-NEXT:    # <MCOperand Reg:301>>
    957 ; MIPS3-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
    958 ; MIPS3-NEXT:    # <MCOperand Reg:416>
    959 ; MIPS3-NEXT:    # <MCOperand Reg:30>
    960 ; MIPS3-NEXT:    # <MCOperand Expr:(%lo(c))>>
    961 ;
    962 ; MIPS64-LABEL: f7:
    963 ; MIPS64:       # %bb.0: # %entry
    964 ; MIPS64-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    965 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    966 ; MIPS64-NEXT:    # <MCOperand Expr:(%highest(c))>>
    967 ; MIPS64-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    968 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    969 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    970 ; MIPS64-NEXT:    # <MCOperand Expr:(%higher(c))>>
    971 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    972 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    973 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    974 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    975 ; MIPS64-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
    976 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    977 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    978 ; MIPS64-NEXT:    # <MCOperand Expr:(%hi(c))>>
    979 ; MIPS64-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
    980 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    981 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    982 ; MIPS64-NEXT:    # <MCOperand Imm:16>>
    983 ; MIPS64-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
    984 ; MIPS64-NEXT:    # <MCOperand Reg:301>>
    985 ; MIPS64-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
    986 ; MIPS64-NEXT:    # <MCOperand Reg:416>
    987 ; MIPS64-NEXT:    # <MCOperand Reg:30>
    988 ; MIPS64-NEXT:    # <MCOperand Expr:(%lo(c))>>
    989 ;
    990 ; MIPS64R6-LABEL: f7:
    991 ; MIPS64R6:       # %bb.0: # %entry
    992 ; MIPS64R6-NEXT:    lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
    993 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    994 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
    995 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
    996 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    997 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
    998 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
    999 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
   1000 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1001 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1002 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
   1003 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
   1004 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1005 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1006 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
   1007 ; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
   1008 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1009 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1010 ; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
   1011 ; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
   1012 ; MIPS64R6-NEXT:    # <MCOperand Reg:355>
   1013 ; MIPS64R6-NEXT:    # <MCOperand Reg:301>>
   1014 ; MIPS64R6-NEXT:    lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
   1015 ; MIPS64R6-NEXT:    # <MCOperand Reg:416>
   1016 ; MIPS64R6-NEXT:    # <MCOperand Reg:30>
   1017 ; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
   1018 entry:
   1019   %0 = load i32, i32 * @c
   1020   %1 = sext i32 %0 to i64
   1021   ret i64 %1
   1022 }
   1023