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      1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
      2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
      3 ; RUN:    -check-prefix=MIPS2
      4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
      5 ; RUN:    -check-prefix=MIPS32
      6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
      7 ; RUN:    -check-prefix=MIPS32R2
      8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
      9 ; RUN:    -check-prefix=MIPS32R2
     10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
     11 ; RUN:    -check-prefix=MIPS32R2
     12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
     13 ; RUN:    -check-prefix=MIPS32R6
     14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
     15 ; RUN:    -check-prefix=MIPS3
     16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
     17 ; RUN:    -check-prefix=MIPS4
     18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
     19 ; RUN:    -check-prefix=MIPS64
     20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
     21 ; RUN:    -check-prefix=MIPS64R2
     22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
     23 ; RUN:    -check-prefix=MIPS64R2
     24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
     25 ; RUN:    -check-prefix=MIPS64R2
     26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
     27 ; RUN:    -check-prefix=MIPS64R6
     28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
     29 ; RUN:    -check-prefix=MMR3
     30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
     31 ; RUN:    -check-prefix=MMR6
     32 
     33 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
     34 ; MIPS2-LABEL: lshr_i1:
     35 ; MIPS2:       # %bb.0: # %entry
     36 ; MIPS2-NEXT:    jr $ra
     37 ; MIPS2-NEXT:    move $2, $4
     38 ;
     39 ; MIPS32-LABEL: lshr_i1:
     40 ; MIPS32:       # %bb.0: # %entry
     41 ; MIPS32-NEXT:    jr $ra
     42 ; MIPS32-NEXT:    move $2, $4
     43 ;
     44 ; MIPS32R2-LABEL: lshr_i1:
     45 ; MIPS32R2:       # %bb.0: # %entry
     46 ; MIPS32R2-NEXT:    jr $ra
     47 ; MIPS32R2-NEXT:    move $2, $4
     48 ;
     49 ; MIPS32R6-LABEL: lshr_i1:
     50 ; MIPS32R6:       # %bb.0: # %entry
     51 ; MIPS32R6-NEXT:    jr $ra
     52 ; MIPS32R6-NEXT:    move $2, $4
     53 ;
     54 ; MIPS3-LABEL: lshr_i1:
     55 ; MIPS3:       # %bb.0: # %entry
     56 ; MIPS3-NEXT:    jr $ra
     57 ; MIPS3-NEXT:    move $2, $4
     58 ;
     59 ; MIPS4-LABEL: lshr_i1:
     60 ; MIPS4:       # %bb.0: # %entry
     61 ; MIPS4-NEXT:    jr $ra
     62 ; MIPS4-NEXT:    move $2, $4
     63 ;
     64 ; MIPS64-LABEL: lshr_i1:
     65 ; MIPS64:       # %bb.0: # %entry
     66 ; MIPS64-NEXT:    jr $ra
     67 ; MIPS64-NEXT:    move $2, $4
     68 ;
     69 ; MIPS64R2-LABEL: lshr_i1:
     70 ; MIPS64R2:       # %bb.0: # %entry
     71 ; MIPS64R2-NEXT:    jr $ra
     72 ; MIPS64R2-NEXT:    move $2, $4
     73 ;
     74 ; MIPS64R6-LABEL: lshr_i1:
     75 ; MIPS64R6:       # %bb.0: # %entry
     76 ; MIPS64R6-NEXT:    jr $ra
     77 ; MIPS64R6-NEXT:    move $2, $4
     78 ;
     79 ; MMR3-LABEL: lshr_i1:
     80 ; MMR3:       # %bb.0: # %entry
     81 ; MMR3-NEXT:    move $2, $4
     82 ; MMR3-NEXT:    jrc $ra
     83 ;
     84 ; MMR6-LABEL: lshr_i1:
     85 ; MMR6:       # %bb.0: # %entry
     86 ; MMR6-NEXT:    move $2, $4
     87 ; MMR6-NEXT:    jrc $ra
     88 entry:
     89 
     90   %r = lshr i1 %a, %b
     91   ret i1 %r
     92 }
     93 
     94 define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
     95 ; MIPS2-LABEL: lshr_i8:
     96 ; MIPS2:       # %bb.0: # %entry
     97 ; MIPS2-NEXT:    srlv $1, $4, $5
     98 ; MIPS2-NEXT:    jr $ra
     99 ; MIPS2-NEXT:    andi $2, $1, 255
    100 ;
    101 ; MIPS32-LABEL: lshr_i8:
    102 ; MIPS32:       # %bb.0: # %entry
    103 ; MIPS32-NEXT:    srlv $1, $4, $5
    104 ; MIPS32-NEXT:    jr $ra
    105 ; MIPS32-NEXT:    andi $2, $1, 255
    106 ;
    107 ; MIPS32R2-LABEL: lshr_i8:
    108 ; MIPS32R2:       # %bb.0: # %entry
    109 ; MIPS32R2-NEXT:    srlv $1, $4, $5
    110 ; MIPS32R2-NEXT:    jr $ra
    111 ; MIPS32R2-NEXT:    andi $2, $1, 255
    112 ;
    113 ; MIPS32R6-LABEL: lshr_i8:
    114 ; MIPS32R6:       # %bb.0: # %entry
    115 ; MIPS32R6-NEXT:    srlv $1, $4, $5
    116 ; MIPS32R6-NEXT:    jr $ra
    117 ; MIPS32R6-NEXT:    andi $2, $1, 255
    118 ;
    119 ; MIPS3-LABEL: lshr_i8:
    120 ; MIPS3:       # %bb.0: # %entry
    121 ; MIPS3-NEXT:    srlv $1, $4, $5
    122 ; MIPS3-NEXT:    jr $ra
    123 ; MIPS3-NEXT:    andi $2, $1, 255
    124 ;
    125 ; MIPS4-LABEL: lshr_i8:
    126 ; MIPS4:       # %bb.0: # %entry
    127 ; MIPS4-NEXT:    srlv $1, $4, $5
    128 ; MIPS4-NEXT:    jr $ra
    129 ; MIPS4-NEXT:    andi $2, $1, 255
    130 ;
    131 ; MIPS64-LABEL: lshr_i8:
    132 ; MIPS64:       # %bb.0: # %entry
    133 ; MIPS64-NEXT:    srlv $1, $4, $5
    134 ; MIPS64-NEXT:    jr $ra
    135 ; MIPS64-NEXT:    andi $2, $1, 255
    136 ;
    137 ; MIPS64R2-LABEL: lshr_i8:
    138 ; MIPS64R2:       # %bb.0: # %entry
    139 ; MIPS64R2-NEXT:    srlv $1, $4, $5
    140 ; MIPS64R2-NEXT:    jr $ra
    141 ; MIPS64R2-NEXT:    andi $2, $1, 255
    142 ;
    143 ; MIPS64R6-LABEL: lshr_i8:
    144 ; MIPS64R6:       # %bb.0: # %entry
    145 ; MIPS64R6-NEXT:    srlv $1, $4, $5
    146 ; MIPS64R6-NEXT:    jr $ra
    147 ; MIPS64R6-NEXT:    andi $2, $1, 255
    148 ;
    149 ; MMR3-LABEL: lshr_i8:
    150 ; MMR3:       # %bb.0: # %entry
    151 ; MMR3-NEXT:    srlv $2, $4, $5
    152 ; MMR3-NEXT:    andi16 $2, $2, 255
    153 ; MMR3-NEXT:    jrc $ra
    154 ;
    155 ; MMR6-LABEL: lshr_i8:
    156 ; MMR6:       # %bb.0: # %entry
    157 ; MMR6-NEXT:    srlv $2, $4, $5
    158 ; MMR6-NEXT:    andi16 $2, $2, 255
    159 ; MMR6-NEXT:    jrc $ra
    160 entry:
    161 
    162   %r = lshr i8 %a, %b
    163   ret i8 %r
    164 }
    165 
    166 define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
    167 ; MIPS2-LABEL: lshr_i16:
    168 ; MIPS2:       # %bb.0: # %entry
    169 ; MIPS2-NEXT:    srlv $1, $4, $5
    170 ; MIPS2-NEXT:    jr $ra
    171 ; MIPS2-NEXT:    andi $2, $1, 65535
    172 ;
    173 ; MIPS32-LABEL: lshr_i16:
    174 ; MIPS32:       # %bb.0: # %entry
    175 ; MIPS32-NEXT:    srlv $1, $4, $5
    176 ; MIPS32-NEXT:    jr $ra
    177 ; MIPS32-NEXT:    andi $2, $1, 65535
    178 ;
    179 ; MIPS32R2-LABEL: lshr_i16:
    180 ; MIPS32R2:       # %bb.0: # %entry
    181 ; MIPS32R2-NEXT:    srlv $1, $4, $5
    182 ; MIPS32R2-NEXT:    jr $ra
    183 ; MIPS32R2-NEXT:    andi $2, $1, 65535
    184 ;
    185 ; MIPS32R6-LABEL: lshr_i16:
    186 ; MIPS32R6:       # %bb.0: # %entry
    187 ; MIPS32R6-NEXT:    srlv $1, $4, $5
    188 ; MIPS32R6-NEXT:    jr $ra
    189 ; MIPS32R6-NEXT:    andi $2, $1, 65535
    190 ;
    191 ; MIPS3-LABEL: lshr_i16:
    192 ; MIPS3:       # %bb.0: # %entry
    193 ; MIPS3-NEXT:    srlv $1, $4, $5
    194 ; MIPS3-NEXT:    jr $ra
    195 ; MIPS3-NEXT:    andi $2, $1, 65535
    196 ;
    197 ; MIPS4-LABEL: lshr_i16:
    198 ; MIPS4:       # %bb.0: # %entry
    199 ; MIPS4-NEXT:    srlv $1, $4, $5
    200 ; MIPS4-NEXT:    jr $ra
    201 ; MIPS4-NEXT:    andi $2, $1, 65535
    202 ;
    203 ; MIPS64-LABEL: lshr_i16:
    204 ; MIPS64:       # %bb.0: # %entry
    205 ; MIPS64-NEXT:    srlv $1, $4, $5
    206 ; MIPS64-NEXT:    jr $ra
    207 ; MIPS64-NEXT:    andi $2, $1, 65535
    208 ;
    209 ; MIPS64R2-LABEL: lshr_i16:
    210 ; MIPS64R2:       # %bb.0: # %entry
    211 ; MIPS64R2-NEXT:    srlv $1, $4, $5
    212 ; MIPS64R2-NEXT:    jr $ra
    213 ; MIPS64R2-NEXT:    andi $2, $1, 65535
    214 ;
    215 ; MIPS64R6-LABEL: lshr_i16:
    216 ; MIPS64R6:       # %bb.0: # %entry
    217 ; MIPS64R6-NEXT:    srlv $1, $4, $5
    218 ; MIPS64R6-NEXT:    jr $ra
    219 ; MIPS64R6-NEXT:    andi $2, $1, 65535
    220 ;
    221 ; MMR3-LABEL: lshr_i16:
    222 ; MMR3:       # %bb.0: # %entry
    223 ; MMR3-NEXT:    srlv $2, $4, $5
    224 ; MMR3-NEXT:    andi16 $2, $2, 65535
    225 ; MMR3-NEXT:    jrc $ra
    226 ;
    227 ; MMR6-LABEL: lshr_i16:
    228 ; MMR6:       # %bb.0: # %entry
    229 ; MMR6-NEXT:    srlv $2, $4, $5
    230 ; MMR6-NEXT:    andi16 $2, $2, 65535
    231 ; MMR6-NEXT:    jrc $ra
    232 entry:
    233 
    234   %r = lshr i16 %a, %b
    235   ret i16 %r
    236 }
    237 
    238 define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
    239 ; MIPS2-LABEL: lshr_i32:
    240 ; MIPS2:       # %bb.0: # %entry
    241 ; MIPS2-NEXT:    jr $ra
    242 ; MIPS2-NEXT:    srlv $2, $4, $5
    243 ;
    244 ; MIPS32-LABEL: lshr_i32:
    245 ; MIPS32:       # %bb.0: # %entry
    246 ; MIPS32-NEXT:    jr $ra
    247 ; MIPS32-NEXT:    srlv $2, $4, $5
    248 ;
    249 ; MIPS32R2-LABEL: lshr_i32:
    250 ; MIPS32R2:       # %bb.0: # %entry
    251 ; MIPS32R2-NEXT:    jr $ra
    252 ; MIPS32R2-NEXT:    srlv $2, $4, $5
    253 ;
    254 ; MIPS32R6-LABEL: lshr_i32:
    255 ; MIPS32R6:       # %bb.0: # %entry
    256 ; MIPS32R6-NEXT:    jr $ra
    257 ; MIPS32R6-NEXT:    srlv $2, $4, $5
    258 ;
    259 ; MIPS3-LABEL: lshr_i32:
    260 ; MIPS3:       # %bb.0: # %entry
    261 ; MIPS3-NEXT:    jr $ra
    262 ; MIPS3-NEXT:    srlv $2, $4, $5
    263 ;
    264 ; MIPS4-LABEL: lshr_i32:
    265 ; MIPS4:       # %bb.0: # %entry
    266 ; MIPS4-NEXT:    jr $ra
    267 ; MIPS4-NEXT:    srlv $2, $4, $5
    268 ;
    269 ; MIPS64-LABEL: lshr_i32:
    270 ; MIPS64:       # %bb.0: # %entry
    271 ; MIPS64-NEXT:    jr $ra
    272 ; MIPS64-NEXT:    srlv $2, $4, $5
    273 ;
    274 ; MIPS64R2-LABEL: lshr_i32:
    275 ; MIPS64R2:       # %bb.0: # %entry
    276 ; MIPS64R2-NEXT:    jr $ra
    277 ; MIPS64R2-NEXT:    srlv $2, $4, $5
    278 ;
    279 ; MIPS64R6-LABEL: lshr_i32:
    280 ; MIPS64R6:       # %bb.0: # %entry
    281 ; MIPS64R6-NEXT:    jr $ra
    282 ; MIPS64R6-NEXT:    srlv $2, $4, $5
    283 ;
    284 ; MMR3-LABEL: lshr_i32:
    285 ; MMR3:       # %bb.0: # %entry
    286 ; MMR3-NEXT:    jr $ra
    287 ; MMR3-NEXT:    srlv $2, $4, $5
    288 ;
    289 ; MMR6-LABEL: lshr_i32:
    290 ; MMR6:       # %bb.0: # %entry
    291 ; MMR6-NEXT:    srlv $2, $4, $5
    292 ; MMR6-NEXT:    jrc $ra
    293 entry:
    294 
    295   %r = lshr i32 %a, %b
    296   ret i32 %r
    297 }
    298 
    299 define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
    300 ; MIPS2-LABEL: lshr_i64:
    301 ; MIPS2:       # %bb.0: # %entry
    302 ; MIPS2-NEXT:    srlv $6, $4, $7
    303 ; MIPS2-NEXT:    andi $8, $7, 32
    304 ; MIPS2-NEXT:    beqz $8, $BB4_3
    305 ; MIPS2-NEXT:    move $3, $6
    306 ; MIPS2-NEXT:  # %bb.1: # %entry
    307 ; MIPS2-NEXT:    beqz $8, $BB4_4
    308 ; MIPS2-NEXT:    addiu $2, $zero, 0
    309 ; MIPS2-NEXT:  $BB4_2: # %entry
    310 ; MIPS2-NEXT:    jr $ra
    311 ; MIPS2-NEXT:    nop
    312 ; MIPS2-NEXT:  $BB4_3: # %entry
    313 ; MIPS2-NEXT:    srlv $1, $5, $7
    314 ; MIPS2-NEXT:    not $2, $7
    315 ; MIPS2-NEXT:    sll $3, $4, 1
    316 ; MIPS2-NEXT:    sllv $2, $3, $2
    317 ; MIPS2-NEXT:    or $3, $2, $1
    318 ; MIPS2-NEXT:    bnez $8, $BB4_2
    319 ; MIPS2-NEXT:    addiu $2, $zero, 0
    320 ; MIPS2-NEXT:  $BB4_4: # %entry
    321 ; MIPS2-NEXT:    jr $ra
    322 ; MIPS2-NEXT:    move $2, $6
    323 ;
    324 ; MIPS32-LABEL: lshr_i64:
    325 ; MIPS32:       # %bb.0: # %entry
    326 ; MIPS32-NEXT:    srlv $1, $5, $7
    327 ; MIPS32-NEXT:    not $2, $7
    328 ; MIPS32-NEXT:    sll $3, $4, 1
    329 ; MIPS32-NEXT:    sllv $2, $3, $2
    330 ; MIPS32-NEXT:    or $3, $2, $1
    331 ; MIPS32-NEXT:    srlv $2, $4, $7
    332 ; MIPS32-NEXT:    andi $1, $7, 32
    333 ; MIPS32-NEXT:    movn $3, $2, $1
    334 ; MIPS32-NEXT:    jr $ra
    335 ; MIPS32-NEXT:    movn $2, $zero, $1
    336 ;
    337 ; MIPS32R2-LABEL: lshr_i64:
    338 ; MIPS32R2:       # %bb.0: # %entry
    339 ; MIPS32R2-NEXT:    srlv $1, $5, $7
    340 ; MIPS32R2-NEXT:    not $2, $7
    341 ; MIPS32R2-NEXT:    sll $3, $4, 1
    342 ; MIPS32R2-NEXT:    sllv $2, $3, $2
    343 ; MIPS32R2-NEXT:    or $3, $2, $1
    344 ; MIPS32R2-NEXT:    srlv $2, $4, $7
    345 ; MIPS32R2-NEXT:    andi $1, $7, 32
    346 ; MIPS32R2-NEXT:    movn $3, $2, $1
    347 ; MIPS32R2-NEXT:    jr $ra
    348 ; MIPS32R2-NEXT:    movn $2, $zero, $1
    349 ;
    350 ; MIPS32R6-LABEL: lshr_i64:
    351 ; MIPS32R6:       # %bb.0: # %entry
    352 ; MIPS32R6-NEXT:    srlv $1, $5, $7
    353 ; MIPS32R6-NEXT:    not $2, $7
    354 ; MIPS32R6-NEXT:    sll $3, $4, 1
    355 ; MIPS32R6-NEXT:    sllv $2, $3, $2
    356 ; MIPS32R6-NEXT:    or $1, $2, $1
    357 ; MIPS32R6-NEXT:    andi $2, $7, 32
    358 ; MIPS32R6-NEXT:    seleqz $1, $1, $2
    359 ; MIPS32R6-NEXT:    srlv $4, $4, $7
    360 ; MIPS32R6-NEXT:    selnez $3, $4, $2
    361 ; MIPS32R6-NEXT:    or $3, $3, $1
    362 ; MIPS32R6-NEXT:    jr $ra
    363 ; MIPS32R6-NEXT:    seleqz $2, $4, $2
    364 ;
    365 ; MIPS3-LABEL: lshr_i64:
    366 ; MIPS3:       # %bb.0: # %entry
    367 ; MIPS3-NEXT:    jr $ra
    368 ; MIPS3-NEXT:    dsrlv $2, $4, $5
    369 ;
    370 ; MIPS4-LABEL: lshr_i64:
    371 ; MIPS4:       # %bb.0: # %entry
    372 ; MIPS4-NEXT:    jr $ra
    373 ; MIPS4-NEXT:    dsrlv $2, $4, $5
    374 ;
    375 ; MIPS64-LABEL: lshr_i64:
    376 ; MIPS64:       # %bb.0: # %entry
    377 ; MIPS64-NEXT:    jr $ra
    378 ; MIPS64-NEXT:    dsrlv $2, $4, $5
    379 ;
    380 ; MIPS64R2-LABEL: lshr_i64:
    381 ; MIPS64R2:       # %bb.0: # %entry
    382 ; MIPS64R2-NEXT:    jr $ra
    383 ; MIPS64R2-NEXT:    dsrlv $2, $4, $5
    384 ;
    385 ; MIPS64R6-LABEL: lshr_i64:
    386 ; MIPS64R6:       # %bb.0: # %entry
    387 ; MIPS64R6-NEXT:    jr $ra
    388 ; MIPS64R6-NEXT:    dsrlv $2, $4, $5
    389 ;
    390 ; MMR3-LABEL: lshr_i64:
    391 ; MMR3:       # %bb.0: # %entry
    392 ; MMR3-NEXT:    srlv $2, $5, $7
    393 ; MMR3-NEXT:    not16 $3, $7
    394 ; MMR3-NEXT:    sll16 $5, $4, 1
    395 ; MMR3-NEXT:    sllv $3, $5, $3
    396 ; MMR3-NEXT:    or16 $3, $2
    397 ; MMR3-NEXT:    srlv $2, $4, $7
    398 ; MMR3-NEXT:    andi16 $4, $7, 32
    399 ; MMR3-NEXT:    movn $3, $2, $4
    400 ; MMR3-NEXT:    li16 $5, 0
    401 ; MMR3-NEXT:    jr $ra
    402 ; MMR3-NEXT:    movn $2, $5, $4
    403 ;
    404 ; MMR6-LABEL: lshr_i64:
    405 ; MMR6:       # %bb.0: # %entry
    406 ; MMR6-NEXT:    srlv $1, $5, $7
    407 ; MMR6-NEXT:    not16 $2, $7
    408 ; MMR6-NEXT:    sll16 $3, $4, 1
    409 ; MMR6-NEXT:    sllv $2, $3, $2
    410 ; MMR6-NEXT:    or $1, $2, $1
    411 ; MMR6-NEXT:    andi16 $2, $7, 32
    412 ; MMR6-NEXT:    seleqz $1, $1, $2
    413 ; MMR6-NEXT:    srlv $4, $4, $7
    414 ; MMR6-NEXT:    selnez $3, $4, $2
    415 ; MMR6-NEXT:    or $3, $3, $1
    416 ; MMR6-NEXT:    seleqz $2, $4, $2
    417 ; MMR6-NEXT:    jrc $ra
    418 entry:
    419 
    420   %r = lshr i64 %a, %b
    421   ret i64 %r
    422 }
    423 
    424 define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
    425 ; MIPS2-LABEL: lshr_i128:
    426 ; MIPS2:       # %bb.0: # %entry
    427 ; MIPS2-NEXT:    addiu $sp, $sp, -8
    428 ; MIPS2-NEXT:    .cfi_def_cfa_offset 8
    429 ; MIPS2-NEXT:    sw $17, 4($sp) # 4-byte Folded Spill
    430 ; MIPS2-NEXT:    sw $16, 0($sp) # 4-byte Folded Spill
    431 ; MIPS2-NEXT:    .cfi_offset 17, -4
    432 ; MIPS2-NEXT:    .cfi_offset 16, -8
    433 ; MIPS2-NEXT:    lw $2, 36($sp)
    434 ; MIPS2-NEXT:    addiu $1, $zero, 64
    435 ; MIPS2-NEXT:    subu $10, $1, $2
    436 ; MIPS2-NEXT:    sllv $9, $5, $10
    437 ; MIPS2-NEXT:    andi $13, $10, 32
    438 ; MIPS2-NEXT:    addiu $8, $zero, 0
    439 ; MIPS2-NEXT:    bnez $13, $BB5_2
    440 ; MIPS2-NEXT:    addiu $25, $zero, 0
    441 ; MIPS2-NEXT:  # %bb.1: # %entry
    442 ; MIPS2-NEXT:    move $25, $9
    443 ; MIPS2-NEXT:  $BB5_2: # %entry
    444 ; MIPS2-NEXT:    not $3, $2
    445 ; MIPS2-NEXT:    srlv $11, $6, $2
    446 ; MIPS2-NEXT:    andi $12, $2, 32
    447 ; MIPS2-NEXT:    bnez $12, $BB5_4
    448 ; MIPS2-NEXT:    move $16, $11
    449 ; MIPS2-NEXT:  # %bb.3: # %entry
    450 ; MIPS2-NEXT:    srlv $1, $7, $2
    451 ; MIPS2-NEXT:    sll $14, $6, 1
    452 ; MIPS2-NEXT:    sllv $14, $14, $3
    453 ; MIPS2-NEXT:    or $16, $14, $1
    454 ; MIPS2-NEXT:  $BB5_4: # %entry
    455 ; MIPS2-NEXT:    addiu $24, $2, -64
    456 ; MIPS2-NEXT:    sll $17, $4, 1
    457 ; MIPS2-NEXT:    srlv $14, $4, $24
    458 ; MIPS2-NEXT:    andi $15, $24, 32
    459 ; MIPS2-NEXT:    bnez $15, $BB5_6
    460 ; MIPS2-NEXT:    move $gp, $14
    461 ; MIPS2-NEXT:  # %bb.5: # %entry
    462 ; MIPS2-NEXT:    srlv $1, $5, $24
    463 ; MIPS2-NEXT:    not $24, $24
    464 ; MIPS2-NEXT:    sllv $24, $17, $24
    465 ; MIPS2-NEXT:    or $gp, $24, $1
    466 ; MIPS2-NEXT:  $BB5_6: # %entry
    467 ; MIPS2-NEXT:    sltiu $24, $2, 64
    468 ; MIPS2-NEXT:    beqz $24, $BB5_8
    469 ; MIPS2-NEXT:    nop
    470 ; MIPS2-NEXT:  # %bb.7:
    471 ; MIPS2-NEXT:    or $gp, $16, $25
    472 ; MIPS2-NEXT:  $BB5_8: # %entry
    473 ; MIPS2-NEXT:    srlv $25, $4, $2
    474 ; MIPS2-NEXT:    bnez $12, $BB5_10
    475 ; MIPS2-NEXT:    move $16, $25
    476 ; MIPS2-NEXT:  # %bb.9: # %entry
    477 ; MIPS2-NEXT:    srlv $1, $5, $2
    478 ; MIPS2-NEXT:    sllv $3, $17, $3
    479 ; MIPS2-NEXT:    or $16, $3, $1
    480 ; MIPS2-NEXT:  $BB5_10: # %entry
    481 ; MIPS2-NEXT:    bnez $12, $BB5_12
    482 ; MIPS2-NEXT:    addiu $3, $zero, 0
    483 ; MIPS2-NEXT:  # %bb.11: # %entry
    484 ; MIPS2-NEXT:    move $3, $25
    485 ; MIPS2-NEXT:  $BB5_12: # %entry
    486 ; MIPS2-NEXT:    addiu $1, $zero, 63
    487 ; MIPS2-NEXT:    sltiu $25, $2, 1
    488 ; MIPS2-NEXT:    beqz $25, $BB5_22
    489 ; MIPS2-NEXT:    sltu $17, $1, $2
    490 ; MIPS2-NEXT:  # %bb.13: # %entry
    491 ; MIPS2-NEXT:    beqz $17, $BB5_23
    492 ; MIPS2-NEXT:    addiu $2, $zero, 0
    493 ; MIPS2-NEXT:  $BB5_14: # %entry
    494 ; MIPS2-NEXT:    beqz $17, $BB5_24
    495 ; MIPS2-NEXT:    addiu $3, $zero, 0
    496 ; MIPS2-NEXT:  $BB5_15: # %entry
    497 ; MIPS2-NEXT:    beqz $13, $BB5_25
    498 ; MIPS2-NEXT:    nop
    499 ; MIPS2-NEXT:  $BB5_16: # %entry
    500 ; MIPS2-NEXT:    beqz $12, $BB5_26
    501 ; MIPS2-NEXT:    addiu $4, $zero, 0
    502 ; MIPS2-NEXT:  $BB5_17: # %entry
    503 ; MIPS2-NEXT:    beqz $15, $BB5_27
    504 ; MIPS2-NEXT:    nop
    505 ; MIPS2-NEXT:  $BB5_18: # %entry
    506 ; MIPS2-NEXT:    bnez $24, $BB5_28
    507 ; MIPS2-NEXT:    nop
    508 ; MIPS2-NEXT:  $BB5_19: # %entry
    509 ; MIPS2-NEXT:    bnez $25, $BB5_21
    510 ; MIPS2-NEXT:    nop
    511 ; MIPS2-NEXT:  $BB5_20: # %entry
    512 ; MIPS2-NEXT:    move $6, $8
    513 ; MIPS2-NEXT:  $BB5_21: # %entry
    514 ; MIPS2-NEXT:    move $4, $6
    515 ; MIPS2-NEXT:    move $5, $7
    516 ; MIPS2-NEXT:    lw $16, 0($sp) # 4-byte Folded Reload
    517 ; MIPS2-NEXT:    lw $17, 4($sp) # 4-byte Folded Reload
    518 ; MIPS2-NEXT:    jr $ra
    519 ; MIPS2-NEXT:    addiu $sp, $sp, 8
    520 ; MIPS2-NEXT:  $BB5_22: # %entry
    521 ; MIPS2-NEXT:    move $7, $gp
    522 ; MIPS2-NEXT:    bnez $17, $BB5_14
    523 ; MIPS2-NEXT:    addiu $2, $zero, 0
    524 ; MIPS2-NEXT:  $BB5_23: # %entry
    525 ; MIPS2-NEXT:    move $2, $3
    526 ; MIPS2-NEXT:    bnez $17, $BB5_15
    527 ; MIPS2-NEXT:    addiu $3, $zero, 0
    528 ; MIPS2-NEXT:  $BB5_24: # %entry
    529 ; MIPS2-NEXT:    bnez $13, $BB5_16
    530 ; MIPS2-NEXT:    move $3, $16
    531 ; MIPS2-NEXT:  $BB5_25: # %entry
    532 ; MIPS2-NEXT:    not $1, $10
    533 ; MIPS2-NEXT:    srl $5, $5, 1
    534 ; MIPS2-NEXT:    sllv $4, $4, $10
    535 ; MIPS2-NEXT:    srlv $1, $5, $1
    536 ; MIPS2-NEXT:    or $9, $4, $1
    537 ; MIPS2-NEXT:    bnez $12, $BB5_17
    538 ; MIPS2-NEXT:    addiu $4, $zero, 0
    539 ; MIPS2-NEXT:  $BB5_26: # %entry
    540 ; MIPS2-NEXT:    bnez $15, $BB5_18
    541 ; MIPS2-NEXT:    move $4, $11
    542 ; MIPS2-NEXT:  $BB5_27: # %entry
    543 ; MIPS2-NEXT:    beqz $24, $BB5_19
    544 ; MIPS2-NEXT:    move $8, $14
    545 ; MIPS2-NEXT:  $BB5_28:
    546 ; MIPS2-NEXT:    bnez $25, $BB5_21
    547 ; MIPS2-NEXT:    or $8, $4, $9
    548 ; MIPS2-NEXT:  # %bb.29:
    549 ; MIPS2-NEXT:    b $BB5_20
    550 ; MIPS2-NEXT:    nop
    551 ;
    552 ; MIPS32-LABEL: lshr_i128:
    553 ; MIPS32:       # %bb.0: # %entry
    554 ; MIPS32-NEXT:    lw $9, 28($sp)
    555 ; MIPS32-NEXT:    addiu $1, $zero, 64
    556 ; MIPS32-NEXT:    subu $2, $1, $9
    557 ; MIPS32-NEXT:    sllv $10, $5, $2
    558 ; MIPS32-NEXT:    andi $11, $2, 32
    559 ; MIPS32-NEXT:    move $1, $10
    560 ; MIPS32-NEXT:    movn $1, $zero, $11
    561 ; MIPS32-NEXT:    srlv $3, $7, $9
    562 ; MIPS32-NEXT:    not $12, $9
    563 ; MIPS32-NEXT:    sll $8, $6, 1
    564 ; MIPS32-NEXT:    sllv $8, $8, $12
    565 ; MIPS32-NEXT:    or $3, $8, $3
    566 ; MIPS32-NEXT:    srlv $13, $6, $9
    567 ; MIPS32-NEXT:    andi $14, $9, 32
    568 ; MIPS32-NEXT:    movn $3, $13, $14
    569 ; MIPS32-NEXT:    addiu $15, $9, -64
    570 ; MIPS32-NEXT:    or $3, $3, $1
    571 ; MIPS32-NEXT:    srlv $1, $5, $15
    572 ; MIPS32-NEXT:    sll $24, $4, 1
    573 ; MIPS32-NEXT:    not $8, $15
    574 ; MIPS32-NEXT:    sllv $8, $24, $8
    575 ; MIPS32-NEXT:    or $1, $8, $1
    576 ; MIPS32-NEXT:    srlv $8, $4, $15
    577 ; MIPS32-NEXT:    andi $15, $15, 32
    578 ; MIPS32-NEXT:    movn $1, $8, $15
    579 ; MIPS32-NEXT:    sltiu $25, $9, 64
    580 ; MIPS32-NEXT:    movn $1, $3, $25
    581 ; MIPS32-NEXT:    sllv $3, $4, $2
    582 ; MIPS32-NEXT:    not $2, $2
    583 ; MIPS32-NEXT:    srl $gp, $5, 1
    584 ; MIPS32-NEXT:    srlv $2, $gp, $2
    585 ; MIPS32-NEXT:    or $gp, $3, $2
    586 ; MIPS32-NEXT:    srlv $2, $5, $9
    587 ; MIPS32-NEXT:    sllv $3, $24, $12
    588 ; MIPS32-NEXT:    or $3, $3, $2
    589 ; MIPS32-NEXT:    srlv $2, $4, $9
    590 ; MIPS32-NEXT:    movn $3, $2, $14
    591 ; MIPS32-NEXT:    movz $1, $7, $9
    592 ; MIPS32-NEXT:    movz $3, $zero, $25
    593 ; MIPS32-NEXT:    movn $gp, $10, $11
    594 ; MIPS32-NEXT:    movn $13, $zero, $14
    595 ; MIPS32-NEXT:    or $4, $13, $gp
    596 ; MIPS32-NEXT:    movn $8, $zero, $15
    597 ; MIPS32-NEXT:    movn $8, $4, $25
    598 ; MIPS32-NEXT:    movz $8, $6, $9
    599 ; MIPS32-NEXT:    movn $2, $zero, $14
    600 ; MIPS32-NEXT:    movz $2, $zero, $25
    601 ; MIPS32-NEXT:    move $4, $8
    602 ; MIPS32-NEXT:    jr $ra
    603 ; MIPS32-NEXT:    move $5, $1
    604 ;
    605 ; MIPS32R2-LABEL: lshr_i128:
    606 ; MIPS32R2:       # %bb.0: # %entry
    607 ; MIPS32R2-NEXT:    lw $9, 28($sp)
    608 ; MIPS32R2-NEXT:    addiu $1, $zero, 64
    609 ; MIPS32R2-NEXT:    subu $2, $1, $9
    610 ; MIPS32R2-NEXT:    sllv $10, $5, $2
    611 ; MIPS32R2-NEXT:    andi $11, $2, 32
    612 ; MIPS32R2-NEXT:    move $1, $10
    613 ; MIPS32R2-NEXT:    movn $1, $zero, $11
    614 ; MIPS32R2-NEXT:    srlv $3, $7, $9
    615 ; MIPS32R2-NEXT:    not $12, $9
    616 ; MIPS32R2-NEXT:    sll $8, $6, 1
    617 ; MIPS32R2-NEXT:    sllv $8, $8, $12
    618 ; MIPS32R2-NEXT:    or $3, $8, $3
    619 ; MIPS32R2-NEXT:    srlv $13, $6, $9
    620 ; MIPS32R2-NEXT:    andi $14, $9, 32
    621 ; MIPS32R2-NEXT:    movn $3, $13, $14
    622 ; MIPS32R2-NEXT:    addiu $15, $9, -64
    623 ; MIPS32R2-NEXT:    or $3, $3, $1
    624 ; MIPS32R2-NEXT:    srlv $1, $5, $15
    625 ; MIPS32R2-NEXT:    sll $24, $4, 1
    626 ; MIPS32R2-NEXT:    not $8, $15
    627 ; MIPS32R2-NEXT:    sllv $8, $24, $8
    628 ; MIPS32R2-NEXT:    or $1, $8, $1
    629 ; MIPS32R2-NEXT:    srlv $8, $4, $15
    630 ; MIPS32R2-NEXT:    andi $15, $15, 32
    631 ; MIPS32R2-NEXT:    movn $1, $8, $15
    632 ; MIPS32R2-NEXT:    sltiu $25, $9, 64
    633 ; MIPS32R2-NEXT:    movn $1, $3, $25
    634 ; MIPS32R2-NEXT:    sllv $3, $4, $2
    635 ; MIPS32R2-NEXT:    not $2, $2
    636 ; MIPS32R2-NEXT:    srl $gp, $5, 1
    637 ; MIPS32R2-NEXT:    srlv $2, $gp, $2
    638 ; MIPS32R2-NEXT:    or $gp, $3, $2
    639 ; MIPS32R2-NEXT:    srlv $2, $5, $9
    640 ; MIPS32R2-NEXT:    sllv $3, $24, $12
    641 ; MIPS32R2-NEXT:    or $3, $3, $2
    642 ; MIPS32R2-NEXT:    srlv $2, $4, $9
    643 ; MIPS32R2-NEXT:    movn $3, $2, $14
    644 ; MIPS32R2-NEXT:    movz $1, $7, $9
    645 ; MIPS32R2-NEXT:    movz $3, $zero, $25
    646 ; MIPS32R2-NEXT:    movn $gp, $10, $11
    647 ; MIPS32R2-NEXT:    movn $13, $zero, $14
    648 ; MIPS32R2-NEXT:    or $4, $13, $gp
    649 ; MIPS32R2-NEXT:    movn $8, $zero, $15
    650 ; MIPS32R2-NEXT:    movn $8, $4, $25
    651 ; MIPS32R2-NEXT:    movz $8, $6, $9
    652 ; MIPS32R2-NEXT:    movn $2, $zero, $14
    653 ; MIPS32R2-NEXT:    movz $2, $zero, $25
    654 ; MIPS32R2-NEXT:    move $4, $8
    655 ; MIPS32R2-NEXT:    jr $ra
    656 ; MIPS32R2-NEXT:    move $5, $1
    657 ;
    658 ; MIPS32R6-LABEL: lshr_i128:
    659 ; MIPS32R6:       # %bb.0: # %entry
    660 ; MIPS32R6-NEXT:    addiu $sp, $sp, -8
    661 ; MIPS32R6-NEXT:    .cfi_def_cfa_offset 8
    662 ; MIPS32R6-NEXT:    sw $16, 4($sp) # 4-byte Folded Spill
    663 ; MIPS32R6-NEXT:    .cfi_offset 16, -4
    664 ; MIPS32R6-NEXT:    lw $1, 36($sp)
    665 ; MIPS32R6-NEXT:    srlv $2, $7, $1
    666 ; MIPS32R6-NEXT:    not $3, $1
    667 ; MIPS32R6-NEXT:    sll $8, $6, 1
    668 ; MIPS32R6-NEXT:    sllv $8, $8, $3
    669 ; MIPS32R6-NEXT:    or $2, $8, $2
    670 ; MIPS32R6-NEXT:    addiu $8, $1, -64
    671 ; MIPS32R6-NEXT:    srlv $9, $5, $8
    672 ; MIPS32R6-NEXT:    sll $10, $4, 1
    673 ; MIPS32R6-NEXT:    not $11, $8
    674 ; MIPS32R6-NEXT:    sllv $11, $10, $11
    675 ; MIPS32R6-NEXT:    andi $12, $1, 32
    676 ; MIPS32R6-NEXT:    seleqz $2, $2, $12
    677 ; MIPS32R6-NEXT:    or $9, $11, $9
    678 ; MIPS32R6-NEXT:    srlv $11, $6, $1
    679 ; MIPS32R6-NEXT:    selnez $13, $11, $12
    680 ; MIPS32R6-NEXT:    addiu $14, $zero, 64
    681 ; MIPS32R6-NEXT:    subu $14, $14, $1
    682 ; MIPS32R6-NEXT:    sllv $15, $5, $14
    683 ; MIPS32R6-NEXT:    andi $24, $14, 32
    684 ; MIPS32R6-NEXT:    andi $25, $8, 32
    685 ; MIPS32R6-NEXT:    seleqz $9, $9, $25
    686 ; MIPS32R6-NEXT:    seleqz $gp, $15, $24
    687 ; MIPS32R6-NEXT:    or $2, $13, $2
    688 ; MIPS32R6-NEXT:    selnez $13, $15, $24
    689 ; MIPS32R6-NEXT:    sllv $15, $4, $14
    690 ; MIPS32R6-NEXT:    not $14, $14
    691 ; MIPS32R6-NEXT:    srl $16, $5, 1
    692 ; MIPS32R6-NEXT:    srlv $14, $16, $14
    693 ; MIPS32R6-NEXT:    or $14, $15, $14
    694 ; MIPS32R6-NEXT:    seleqz $14, $14, $24
    695 ; MIPS32R6-NEXT:    srlv $8, $4, $8
    696 ; MIPS32R6-NEXT:    or $13, $13, $14
    697 ; MIPS32R6-NEXT:    or $2, $2, $gp
    698 ; MIPS32R6-NEXT:    srlv $5, $5, $1
    699 ; MIPS32R6-NEXT:    selnez $14, $8, $25
    700 ; MIPS32R6-NEXT:    sltiu $15, $1, 64
    701 ; MIPS32R6-NEXT:    selnez $2, $2, $15
    702 ; MIPS32R6-NEXT:    or $9, $14, $9
    703 ; MIPS32R6-NEXT:    sllv $3, $10, $3
    704 ; MIPS32R6-NEXT:    seleqz $10, $11, $12
    705 ; MIPS32R6-NEXT:    or $10, $10, $13
    706 ; MIPS32R6-NEXT:    or $3, $3, $5
    707 ; MIPS32R6-NEXT:    seleqz $5, $9, $15
    708 ; MIPS32R6-NEXT:    seleqz $9, $zero, $15
    709 ; MIPS32R6-NEXT:    srlv $4, $4, $1
    710 ; MIPS32R6-NEXT:    seleqz $11, $4, $12
    711 ; MIPS32R6-NEXT:    selnez $11, $11, $15
    712 ; MIPS32R6-NEXT:    seleqz $7, $7, $1
    713 ; MIPS32R6-NEXT:    or $2, $2, $5
    714 ; MIPS32R6-NEXT:    selnez $2, $2, $1
    715 ; MIPS32R6-NEXT:    or $5, $7, $2
    716 ; MIPS32R6-NEXT:    or $2, $9, $11
    717 ; MIPS32R6-NEXT:    seleqz $3, $3, $12
    718 ; MIPS32R6-NEXT:    selnez $7, $4, $12
    719 ; MIPS32R6-NEXT:    seleqz $4, $6, $1
    720 ; MIPS32R6-NEXT:    selnez $6, $10, $15
    721 ; MIPS32R6-NEXT:    seleqz $8, $8, $25
    722 ; MIPS32R6-NEXT:    seleqz $8, $8, $15
    723 ; MIPS32R6-NEXT:    or $6, $6, $8
    724 ; MIPS32R6-NEXT:    selnez $1, $6, $1
    725 ; MIPS32R6-NEXT:    or $4, $4, $1
    726 ; MIPS32R6-NEXT:    or $1, $7, $3
    727 ; MIPS32R6-NEXT:    selnez $1, $1, $15
    728 ; MIPS32R6-NEXT:    or $3, $9, $1
    729 ; MIPS32R6-NEXT:    lw $16, 4($sp) # 4-byte Folded Reload
    730 ; MIPS32R6-NEXT:    jr $ra
    731 ; MIPS32R6-NEXT:    addiu $sp, $sp, 8
    732 ;
    733 ; MIPS3-LABEL: lshr_i128:
    734 ; MIPS3:       # %bb.0: # %entry
    735 ; MIPS3-NEXT:    sll $2, $7, 0
    736 ; MIPS3-NEXT:    dsrlv $6, $4, $7
    737 ; MIPS3-NEXT:    andi $8, $2, 64
    738 ; MIPS3-NEXT:    beqz $8, .LBB5_3
    739 ; MIPS3-NEXT:    move $3, $6
    740 ; MIPS3-NEXT:  # %bb.1: # %entry
    741 ; MIPS3-NEXT:    beqz $8, .LBB5_4
    742 ; MIPS3-NEXT:    daddiu $2, $zero, 0
    743 ; MIPS3-NEXT:  .LBB5_2: # %entry
    744 ; MIPS3-NEXT:    jr $ra
    745 ; MIPS3-NEXT:    nop
    746 ; MIPS3-NEXT:  .LBB5_3: # %entry
    747 ; MIPS3-NEXT:    dsrlv $1, $5, $7
    748 ; MIPS3-NEXT:    dsll $3, $4, 1
    749 ; MIPS3-NEXT:    not $2, $2
    750 ; MIPS3-NEXT:    dsllv $2, $3, $2
    751 ; MIPS3-NEXT:    or $3, $2, $1
    752 ; MIPS3-NEXT:    bnez $8, .LBB5_2
    753 ; MIPS3-NEXT:    daddiu $2, $zero, 0
    754 ; MIPS3-NEXT:  .LBB5_4: # %entry
    755 ; MIPS3-NEXT:    jr $ra
    756 ; MIPS3-NEXT:    move $2, $6
    757 ;
    758 ; MIPS4-LABEL: lshr_i128:
    759 ; MIPS4:       # %bb.0: # %entry
    760 ; MIPS4-NEXT:    dsrlv $1, $5, $7
    761 ; MIPS4-NEXT:    dsll $2, $4, 1
    762 ; MIPS4-NEXT:    sll $5, $7, 0
    763 ; MIPS4-NEXT:    not $3, $5
    764 ; MIPS4-NEXT:    dsllv $2, $2, $3
    765 ; MIPS4-NEXT:    or $3, $2, $1
    766 ; MIPS4-NEXT:    dsrlv $2, $4, $7
    767 ; MIPS4-NEXT:    andi $1, $5, 64
    768 ; MIPS4-NEXT:    movn $3, $2, $1
    769 ; MIPS4-NEXT:    jr $ra
    770 ; MIPS4-NEXT:    movn $2, $zero, $1
    771 ;
    772 ; MIPS64-LABEL: lshr_i128:
    773 ; MIPS64:       # %bb.0: # %entry
    774 ; MIPS64-NEXT:    dsrlv $1, $5, $7
    775 ; MIPS64-NEXT:    dsll $2, $4, 1
    776 ; MIPS64-NEXT:    sll $5, $7, 0
    777 ; MIPS64-NEXT:    not $3, $5
    778 ; MIPS64-NEXT:    dsllv $2, $2, $3
    779 ; MIPS64-NEXT:    or $3, $2, $1
    780 ; MIPS64-NEXT:    dsrlv $2, $4, $7
    781 ; MIPS64-NEXT:    andi $1, $5, 64
    782 ; MIPS64-NEXT:    movn $3, $2, $1
    783 ; MIPS64-NEXT:    jr $ra
    784 ; MIPS64-NEXT:    movn $2, $zero, $1
    785 ;
    786 ; MIPS64R2-LABEL: lshr_i128:
    787 ; MIPS64R2:       # %bb.0: # %entry
    788 ; MIPS64R2-NEXT:    dsrlv $1, $5, $7
    789 ; MIPS64R2-NEXT:    dsll $2, $4, 1
    790 ; MIPS64R2-NEXT:    sll $5, $7, 0
    791 ; MIPS64R2-NEXT:    not $3, $5
    792 ; MIPS64R2-NEXT:    dsllv $2, $2, $3
    793 ; MIPS64R2-NEXT:    or $3, $2, $1
    794 ; MIPS64R2-NEXT:    dsrlv $2, $4, $7
    795 ; MIPS64R2-NEXT:    andi $1, $5, 64
    796 ; MIPS64R2-NEXT:    movn $3, $2, $1
    797 ; MIPS64R2-NEXT:    jr $ra
    798 ; MIPS64R2-NEXT:    movn $2, $zero, $1
    799 ;
    800 ; MIPS64R6-LABEL: lshr_i128:
    801 ; MIPS64R6:       # %bb.0: # %entry
    802 ; MIPS64R6-NEXT:    dsrlv $1, $5, $7
    803 ; MIPS64R6-NEXT:    dsll $2, $4, 1
    804 ; MIPS64R6-NEXT:    sll $3, $7, 0
    805 ; MIPS64R6-NEXT:    not $5, $3
    806 ; MIPS64R6-NEXT:    dsllv $2, $2, $5
    807 ; MIPS64R6-NEXT:    or $1, $2, $1
    808 ; MIPS64R6-NEXT:    andi $2, $3, 64
    809 ; MIPS64R6-NEXT:    sll $2, $2, 0
    810 ; MIPS64R6-NEXT:    seleqz $1, $1, $2
    811 ; MIPS64R6-NEXT:    dsrlv $4, $4, $7
    812 ; MIPS64R6-NEXT:    selnez $3, $4, $2
    813 ; MIPS64R6-NEXT:    or $3, $3, $1
    814 ; MIPS64R6-NEXT:    jr $ra
    815 ; MIPS64R6-NEXT:    seleqz $2, $4, $2
    816 ;
    817 ; MMR3-LABEL: lshr_i128:
    818 ; MMR3:       # %bb.0: # %entry
    819 ; MMR3-NEXT:    addiusp -40
    820 ; MMR3-NEXT:    .cfi_def_cfa_offset 40
    821 ; MMR3-NEXT:    swp $16, 32($sp)
    822 ; MMR3-NEXT:    .cfi_offset 17, -4
    823 ; MMR3-NEXT:    .cfi_offset 16, -8
    824 ; MMR3-NEXT:    move $8, $7
    825 ; MMR3-NEXT:    sw $6, 24($sp) # 4-byte Folded Spill
    826 ; MMR3-NEXT:    sw $4, 28($sp) # 4-byte Folded Spill
    827 ; MMR3-NEXT:    lw $16, 68($sp)
    828 ; MMR3-NEXT:    li16 $2, 64
    829 ; MMR3-NEXT:    subu16 $7, $2, $16
    830 ; MMR3-NEXT:    sllv $9, $5, $7
    831 ; MMR3-NEXT:    move $17, $5
    832 ; MMR3-NEXT:    sw $5, 0($sp) # 4-byte Folded Spill
    833 ; MMR3-NEXT:    andi16 $3, $7, 32
    834 ; MMR3-NEXT:    sw $3, 20($sp) # 4-byte Folded Spill
    835 ; MMR3-NEXT:    li16 $2, 0
    836 ; MMR3-NEXT:    move $4, $9
    837 ; MMR3-NEXT:    movn $4, $2, $3
    838 ; MMR3-NEXT:    srlv $5, $8, $16
    839 ; MMR3-NEXT:    not16 $3, $16
    840 ; MMR3-NEXT:    sw $3, 16($sp) # 4-byte Folded Spill
    841 ; MMR3-NEXT:    sll16 $2, $6, 1
    842 ; MMR3-NEXT:    sllv $2, $2, $3
    843 ; MMR3-NEXT:    or16 $2, $5
    844 ; MMR3-NEXT:    srlv $5, $6, $16
    845 ; MMR3-NEXT:    sw $5, 4($sp) # 4-byte Folded Spill
    846 ; MMR3-NEXT:    andi16 $3, $16, 32
    847 ; MMR3-NEXT:    sw $3, 12($sp) # 4-byte Folded Spill
    848 ; MMR3-NEXT:    movn $2, $5, $3
    849 ; MMR3-NEXT:    addiu $3, $16, -64
    850 ; MMR3-NEXT:    or16 $2, $4
    851 ; MMR3-NEXT:    srlv $4, $17, $3
    852 ; MMR3-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
    853 ; MMR3-NEXT:    lw $4, 28($sp) # 4-byte Folded Reload
    854 ; MMR3-NEXT:    sll16 $6, $4, 1
    855 ; MMR3-NEXT:    not16 $5, $3
    856 ; MMR3-NEXT:    sllv $5, $6, $5
    857 ; MMR3-NEXT:    lw $17, 8($sp) # 4-byte Folded Reload
    858 ; MMR3-NEXT:    or16 $5, $17
    859 ; MMR3-NEXT:    srlv $1, $4, $3
    860 ; MMR3-NEXT:    andi16 $3, $3, 32
    861 ; MMR3-NEXT:    sw $3, 8($sp) # 4-byte Folded Spill
    862 ; MMR3-NEXT:    movn $5, $1, $3
    863 ; MMR3-NEXT:    sltiu $10, $16, 64
    864 ; MMR3-NEXT:    movn $5, $2, $10
    865 ; MMR3-NEXT:    sllv $2, $4, $7
    866 ; MMR3-NEXT:    not16 $3, $7
    867 ; MMR3-NEXT:    lw $7, 0($sp) # 4-byte Folded Reload
    868 ; MMR3-NEXT:    srl16 $4, $7, 1
    869 ; MMR3-NEXT:    srlv $4, $4, $3
    870 ; MMR3-NEXT:    or16 $4, $2
    871 ; MMR3-NEXT:    srlv $2, $7, $16
    872 ; MMR3-NEXT:    lw $3, 16($sp) # 4-byte Folded Reload
    873 ; MMR3-NEXT:    sllv $3, $6, $3
    874 ; MMR3-NEXT:    or16 $3, $2
    875 ; MMR3-NEXT:    lw $2, 28($sp) # 4-byte Folded Reload
    876 ; MMR3-NEXT:    srlv $2, $2, $16
    877 ; MMR3-NEXT:    lw $17, 12($sp) # 4-byte Folded Reload
    878 ; MMR3-NEXT:    movn $3, $2, $17
    879 ; MMR3-NEXT:    movz $5, $8, $16
    880 ; MMR3-NEXT:    li16 $6, 0
    881 ; MMR3-NEXT:    movz $3, $6, $10
    882 ; MMR3-NEXT:    lw $7, 20($sp) # 4-byte Folded Reload
    883 ; MMR3-NEXT:    movn $4, $9, $7
    884 ; MMR3-NEXT:    lw $6, 4($sp) # 4-byte Folded Reload
    885 ; MMR3-NEXT:    li16 $7, 0
    886 ; MMR3-NEXT:    movn $6, $7, $17
    887 ; MMR3-NEXT:    or16 $6, $4
    888 ; MMR3-NEXT:    lw $4, 8($sp) # 4-byte Folded Reload
    889 ; MMR3-NEXT:    movn $1, $7, $4
    890 ; MMR3-NEXT:    li16 $7, 0
    891 ; MMR3-NEXT:    movn $1, $6, $10
    892 ; MMR3-NEXT:    lw $4, 24($sp) # 4-byte Folded Reload
    893 ; MMR3-NEXT:    movz $1, $4, $16
    894 ; MMR3-NEXT:    movn $2, $7, $17
    895 ; MMR3-NEXT:    li16 $4, 0
    896 ; MMR3-NEXT:    movz $2, $4, $10
    897 ; MMR3-NEXT:    move $4, $1
    898 ; MMR3-NEXT:    lwp $16, 32($sp)
    899 ; MMR3-NEXT:    addiusp 40
    900 ; MMR3-NEXT:    jrc $ra
    901 ;
    902 ; MMR6-LABEL: lshr_i128:
    903 ; MMR6:       # %bb.0: # %entry
    904 ; MMR6-NEXT:    addiu $sp, $sp, -32
    905 ; MMR6-NEXT:    .cfi_def_cfa_offset 32
    906 ; MMR6-NEXT:    sw $17, 28($sp) # 4-byte Folded Spill
    907 ; MMR6-NEXT:    sw $16, 24($sp) # 4-byte Folded Spill
    908 ; MMR6-NEXT:    .cfi_offset 17, -4
    909 ; MMR6-NEXT:    .cfi_offset 16, -8
    910 ; MMR6-NEXT:    move $1, $7
    911 ; MMR6-NEXT:    move $7, $5
    912 ; MMR6-NEXT:    lw $3, 60($sp)
    913 ; MMR6-NEXT:    srlv $2, $1, $3
    914 ; MMR6-NEXT:    not16 $5, $3
    915 ; MMR6-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
    916 ; MMR6-NEXT:    move $17, $6
    917 ; MMR6-NEXT:    sw $6, 16($sp) # 4-byte Folded Spill
    918 ; MMR6-NEXT:    sll16 $6, $6, 1
    919 ; MMR6-NEXT:    sllv $6, $6, $5
    920 ; MMR6-NEXT:    or $8, $6, $2
    921 ; MMR6-NEXT:    addiu $5, $3, -64
    922 ; MMR6-NEXT:    srlv $9, $7, $5
    923 ; MMR6-NEXT:    move $6, $4
    924 ; MMR6-NEXT:    sll16 $2, $4, 1
    925 ; MMR6-NEXT:    sw $2, 8($sp) # 4-byte Folded Spill
    926 ; MMR6-NEXT:    not16 $16, $5
    927 ; MMR6-NEXT:    sllv $10, $2, $16
    928 ; MMR6-NEXT:    andi16 $16, $3, 32
    929 ; MMR6-NEXT:    seleqz $8, $8, $16
    930 ; MMR6-NEXT:    or $9, $10, $9
    931 ; MMR6-NEXT:    srlv $10, $17, $3
    932 ; MMR6-NEXT:    selnez $11, $10, $16
    933 ; MMR6-NEXT:    li16 $17, 64
    934 ; MMR6-NEXT:    subu16 $2, $17, $3
    935 ; MMR6-NEXT:    sllv $12, $7, $2
    936 ; MMR6-NEXT:    move $17, $7
    937 ; MMR6-NEXT:    andi16 $4, $2, 32
    938 ; MMR6-NEXT:    andi16 $7, $5, 32
    939 ; MMR6-NEXT:    sw $7, 20($sp) # 4-byte Folded Spill
    940 ; MMR6-NEXT:    seleqz $9, $9, $7
    941 ; MMR6-NEXT:    seleqz $13, $12, $4
    942 ; MMR6-NEXT:    or $8, $11, $8
    943 ; MMR6-NEXT:    selnez $11, $12, $4
    944 ; MMR6-NEXT:    sllv $12, $6, $2
    945 ; MMR6-NEXT:    move $7, $6
    946 ; MMR6-NEXT:    sw $6, 4($sp) # 4-byte Folded Spill
    947 ; MMR6-NEXT:    not16 $2, $2
    948 ; MMR6-NEXT:    srl16 $6, $17, 1
    949 ; MMR6-NEXT:    srlv $2, $6, $2
    950 ; MMR6-NEXT:    or $2, $12, $2
    951 ; MMR6-NEXT:    seleqz $2, $2, $4
    952 ; MMR6-NEXT:    srlv $4, $7, $5
    953 ; MMR6-NEXT:    or $11, $11, $2
    954 ; MMR6-NEXT:    or $5, $8, $13
    955 ; MMR6-NEXT:    srlv $6, $17, $3
    956 ; MMR6-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
    957 ; MMR6-NEXT:    selnez $7, $4, $2
    958 ; MMR6-NEXT:    sltiu $8, $3, 64
    959 ; MMR6-NEXT:    selnez $12, $5, $8
    960 ; MMR6-NEXT:    or $7, $7, $9
    961 ; MMR6-NEXT:    lw $5, 12($sp) # 4-byte Folded Reload
    962 ; MMR6-NEXT:    lw $2, 8($sp) # 4-byte Folded Reload
    963 ; MMR6-NEXT:    sllv $9, $2, $5
    964 ; MMR6-NEXT:    seleqz $10, $10, $16
    965 ; MMR6-NEXT:    li16 $5, 0
    966 ; MMR6-NEXT:    or $10, $10, $11
    967 ; MMR6-NEXT:    or $6, $9, $6
    968 ; MMR6-NEXT:    seleqz $2, $7, $8
    969 ; MMR6-NEXT:    seleqz $7, $5, $8
    970 ; MMR6-NEXT:    lw $5, 4($sp) # 4-byte Folded Reload
    971 ; MMR6-NEXT:    srlv $9, $5, $3
    972 ; MMR6-NEXT:    seleqz $11, $9, $16
    973 ; MMR6-NEXT:    selnez $11, $11, $8
    974 ; MMR6-NEXT:    seleqz $1, $1, $3
    975 ; MMR6-NEXT:    or $2, $12, $2
    976 ; MMR6-NEXT:    selnez $2, $2, $3
    977 ; MMR6-NEXT:    or $5, $1, $2
    978 ; MMR6-NEXT:    or $2, $7, $11
    979 ; MMR6-NEXT:    seleqz $1, $6, $16
    980 ; MMR6-NEXT:    selnez $6, $9, $16
    981 ; MMR6-NEXT:    lw $16, 16($sp) # 4-byte Folded Reload
    982 ; MMR6-NEXT:    seleqz $9, $16, $3
    983 ; MMR6-NEXT:    selnez $10, $10, $8
    984 ; MMR6-NEXT:    lw $16, 20($sp) # 4-byte Folded Reload
    985 ; MMR6-NEXT:    seleqz $4, $4, $16
    986 ; MMR6-NEXT:    seleqz $4, $4, $8
    987 ; MMR6-NEXT:    or $4, $10, $4
    988 ; MMR6-NEXT:    selnez $3, $4, $3
    989 ; MMR6-NEXT:    or $4, $9, $3
    990 ; MMR6-NEXT:    or $1, $6, $1
    991 ; MMR6-NEXT:    selnez $1, $1, $8
    992 ; MMR6-NEXT:    or $3, $7, $1
    993 ; MMR6-NEXT:    lw $16, 24($sp) # 4-byte Folded Reload
    994 ; MMR6-NEXT:    lw $17, 28($sp) # 4-byte Folded Reload
    995 ; MMR6-NEXT:    addiu $sp, $sp, 32
    996 ; MMR6-NEXT:    jrc $ra
    997 entry:
    998 
    999 ; o32 shouldn't use TImode helpers.
   1000 ; GP32-NOT:       lw        $25, %call16(__lshrti3)($gp)
   1001 ; MM-NOT:         lw        $25, %call16(__lshrti3)($2)
   1002 
   1003   %r = lshr i128 %a, %b
   1004   ret i128 %r
   1005 }
   1006