1 ; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \ 2 ; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32 3 ; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \ 4 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \ 6 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \ 8 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \ 10 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \ 12 ; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32 13 ; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \ 14 ; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6 15 ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \ 16 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 17 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \ 18 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 19 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \ 20 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 21 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \ 22 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 23 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \ 24 ; RUN: FileCheck %s -check-prefixes=ALL,64R6 25 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ 26 ; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 27 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ 28 ; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 29 30 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { 31 entry: 32 ; ALL-LABEL: mul_i1: 33 34 ; M2: mult $4, $5 35 ; M2: mflo $[[T0:[0-9]+]] 36 ; M2: andi $[[T0]], $[[T0]], 1 37 ; M2: negu $2, $[[T0]] 38 39 ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5 40 ; 32R1-R5: andi $[[T0]], $[[T0]], 1 41 ; 32R1-R5: negu $2, $[[T0]] 42 43 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 44 ; 32R6: andi $[[T0]], $[[T0]], 1 45 ; 32R6: negu $2, $[[T0]] 46 47 ; M4: mult $4, $5 48 ; M4: mflo $[[T0:[0-9]+]] 49 ; M4: andi $[[T0]], $[[T0]], 1 50 ; M4: negu $2, $[[T0]] 51 52 ; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5 53 ; 64R1-R5: andi $[[T0]], $[[T0]], 1 54 ; 64R1-R5: negu $2, $[[T0]] 55 56 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 57 ; 64R6: andi $[[T0]], $[[T0]], 1 58 ; 64R6: negu $2, $[[T0]] 59 60 ; MM32: mul $[[T0:[0-9]+]], $4, $5 61 ; MM32: andi16 $[[T0]], $[[T0]], 1 62 ; MM32: li16 $[[T1:[0-9]+]], 0 63 ; MM32: subu16 $2, $[[T1]], $[[T0]] 64 65 %r = mul i1 %a, %b 66 ret i1 %r 67 } 68 69 define signext i8 @mul_i8(i8 signext %a, i8 signext %b) { 70 entry: 71 ; ALL-LABEL: mul_i8: 72 73 ; M2: mult $4, $5 74 ; M2: mflo $[[T0:[0-9]+]] 75 ; M2: sll $[[T0]], $[[T0]], 24 76 ; M2: sra $2, $[[T0]], 24 77 78 ; 32R1: mul $[[T0:[0-9]+]], $4, $5 79 ; 32R1: sll $[[T0]], $[[T0]], 24 80 ; 32R1: sra $2, $[[T0]], 24 81 82 ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5 83 ; 32R2-R5: seb $2, $[[T0]] 84 85 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 86 ; 32R6: seb $2, $[[T0]] 87 88 ; M4: mult $4, $5 89 ; M4: mflo $[[T0:[0-9]+]] 90 ; M4: sll $[[T0]], $[[T0]], 24 91 ; M4: sra $2, $[[T0]], 24 92 93 ; 64R1: mul $[[T0:[0-9]+]], $4, $5 94 ; 64R1: sll $[[T0]], $[[T0]], 24 95 ; 64R1: sra $2, $[[T0]], 24 96 97 ; 64R2: mul $[[T0:[0-9]+]], $4, $5 98 ; 64R2: seb $2, $[[T0]] 99 100 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 101 ; 64R6: seb $2, $[[T0]] 102 103 ; MM32: mul $[[T0:[0-9]+]], $4, $5 104 ; MM32: seb $2, $[[T0]] 105 106 %r = mul i8 %a, %b 107 ret i8 %r 108 } 109 110 define signext i16 @mul_i16(i16 signext %a, i16 signext %b) { 111 entry: 112 ; ALL-LABEL: mul_i16: 113 114 ; M2: mult $4, $5 115 ; M2: mflo $[[T0:[0-9]+]] 116 ; M2: sll $[[T0]], $[[T0]], 16 117 ; M2: sra $2, $[[T0]], 16 118 119 ; 32R1: mul $[[T0:[0-9]+]], $4, $5 120 ; 32R1: sll $[[T0]], $[[T0]], 16 121 ; 32R1: sra $2, $[[T0]], 16 122 123 ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5 124 ; 32R2-R5: seh $2, $[[T0]] 125 126 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 127 ; 32R6: seh $2, $[[T0]] 128 129 ; M4: mult $4, $5 130 ; M4: mflo $[[T0:[0-9]+]] 131 ; M4: sll $[[T0]], $[[T0]], 16 132 ; M4: sra $2, $[[T0]], 16 133 134 ; 64R1: mul $[[T0:[0-9]+]], $4, $5 135 ; 64R1: sll $[[T0]], $[[T0]], 16 136 ; 64R1: sra $2, $[[T0]], 16 137 138 ; 64R2: mul $[[T0:[0-9]+]], $4, $5 139 ; 64R2: seh $2, $[[T0]] 140 141 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 142 ; 64R6: seh $2, $[[T0]] 143 144 ; MM32: mul $[[T0:[0-9]+]], $4, $5 145 ; MM32: seh $2, $[[T0]] 146 147 %r = mul i16 %a, %b 148 ret i16 %r 149 } 150 151 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) { 152 entry: 153 ; ALL-LABEL: mul_i32: 154 155 ; M2: mult $4, $5 156 ; M2: mflo $2 157 158 ; 32R1-R5: mul $2, $4, $5 159 ; 32R6: mul $2, $4, $5 160 161 ; 64R1-R5: mul $2, $4, $5 162 ; 64R6: mul $2, $4, $5 163 164 ; MM32: mul $2, $4, $5 165 166 %r = mul i32 %a, %b 167 ret i32 %r 168 } 169 170 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) { 171 entry: 172 ; ALL-LABEL: mul_i64: 173 174 ; M2: mult $4, $7 175 ; M2: mflo $[[T0:[0-9]+]] 176 ; M2: mult $5, $6 177 ; M2: mflo $[[T1:[0-9]+]] 178 ; M2: multu $5, $7 179 ; M2: mflo $3 180 ; M2: mfhi $4 181 ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]] 182 ; M2: addu $2, $[[T2]], $[[T0]] 183 184 ; 32R1-R5: multu $5, $7 185 ; 32R1-R5: mflo $3 186 ; 32R1-R5: mfhi $[[T0:[0-9]+]] 187 ; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6 188 ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]] 189 ; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7 190 ; 32R1-R5: addu $2, $[[T0]], $[[T2]] 191 192 ; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6 193 ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 194 ; 32R6: addu $[[T0]], $[[T1]], $[[T0]] 195 ; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7 196 ; 32R6: addu $2, $[[T0]], $[[T2]] 197 ; 32R6-DAG: mul $3, $5, $7 198 199 ; M4: dmult $4, $5 200 ; M4: mflo $2 201 202 ; 64R1-R5: dmult $4, $5 203 ; 64R1-R5: mflo $2 204 205 ; 64R6: dmul $2, $4, $5 206 207 ; MM32R3: multu $[[T0:[0-9]+]], $7 208 ; MM32R3: mflo16 $[[T1:[0-9]+]] 209 ; MM32R3: mfhi16 $[[T2:[0-9]+]] 210 ; MM32R3: mul $[[T0]], $[[T0]], $6 211 ; MM32R3: addu16 $2, $[[T2]], $[[T0]] 212 ; MM32R3: mul $[[T3:[0-9]+]], $4, $7 213 ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]] 214 215 ; MM32R6: mul $[[T0:[0-9]+]], $5, $6 216 ; MM32R6: muhu $[[T1:[0-9]+]], $5, $7 217 ; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]] 218 ; MM32R6: mul $[[T3:[0-9]+]], $4, $7 219 ; MM32R6: addu16 $2, $[[T2]], $[[T3]] 220 ; MM32R6: mul $[[T1]], $5, $7 221 222 %r = mul i64 %a, %b 223 ret i64 %r 224 } 225 226 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { 227 entry: 228 ; ALL-LABEL: mul_i128: 229 230 ; GP32: lw $25, %call16(__multi3)($gp) 231 232 ; GP64-NOT-R6: dmult $4, $7 233 ; GP64-NOT-R6: mflo $[[T0:[0-9]+]] 234 ; GP64-NOT-R6: dmult $5, $6 235 ; GP64-NOT-R6: mflo $[[T1:[0-9]+]] 236 ; GP64-NOT-R6: dmultu $5, $7 237 ; GP64-NOT-R6: mflo $3 238 ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]] 239 ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] 240 ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] 241 242 ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 243 ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7 244 ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] 245 ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 246 ; 64R6: daddu $2, $[[T1]], $[[T0]] 247 ; 64R6-DAG: dmul $3, $5, $7 248 249 ; MM32: lw $25, %call16(__multi3)($16) 250 251 %r = mul i128 %a, %b 252 ret i128 %r 253 } 254
