1 ; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2 ; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 3 ; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4 ; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12 ; RUN: -check-prefixes=ALL,R6,GP32 13 14 ; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15 ; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 16 ; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17 ; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 18 ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19 ; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 20 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 22 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 24 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 26 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27 ; RUN: -check-prefixes=ALL,R6,64R6 28 29 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30 ; RUN: -check-prefixes=ALL,MMR3,MM32 31 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32 ; RUN: -check-prefixes=ALL,MMR6,MM32 33 34 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { 35 entry: 36 ; ALL-LABEL: sdiv_i1: 37 38 ; NOT-R6: div $zero, $4, $5 39 ; NOT-R6: teq $5, $zero, 7 40 ; NOT-R6: mflo $[[T0:[0-9]+]] 41 ; FIXME: The andi/negu instructions are redundant since div is signed. 42 ; NOT-R6: andi $[[T0]], $[[T0]], 1 43 ; NOT-R6: negu $2, $[[T0]] 44 45 ; R6: div $[[T0:[0-9]+]], $4, $5 46 ; R6: teq $5, $zero, 7 47 ; FIXME: The andi/negu instructions are redundant since div is signed. 48 ; R6: andi $[[T0]], $[[T0]], 1 49 ; R6: negu $2, $[[T0]] 50 51 ; MMR3: div $zero, $4, $5 52 ; MMR3: teq $5, $zero, 7 53 ; MMR3: mflo16 $[[T0:[0-9]+]] 54 ; MMR3: andi16 $[[T0]], $[[T0]], 1 55 ; MMR3: li16 $[[T1:[0-9]+]], 0 56 ; MMR3: subu16 $2, $[[T1]], $[[T0]] 57 58 ; MMR6: div $[[T0:[0-9]+]], $4, $5 59 ; MMR6: teq $5, $zero, 7 60 ; MMR6: andi16 $[[T0]], $[[T0]], 1 61 ; MMR6: li16 $[[T1:[0-9]+]], 0 62 ; MMR6: subu16 $2, $[[T1]], $[[T0]] 63 64 %r = sdiv i1 %a, %b 65 ret i1 %r 66 } 67 68 define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) { 69 entry: 70 ; ALL-LABEL: sdiv_i8: 71 72 ; NOT-R2-R6: div $zero, $4, $5 73 ; NOT-R2-R6: teq $5, $zero, 7 74 ; NOT-R2-R6: mflo $[[T0:[0-9]+]] 75 ; FIXME: The sll/sra instructions are redundant since div is signed. 76 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 77 ; NOT-R2-R6: sra $2, $[[T1]], 24 78 79 ; R2-R5: div $zero, $4, $5 80 ; R2-R5: teq $5, $zero, 7 81 ; R2-R5: mflo $[[T0:[0-9]+]] 82 ; FIXME: This instruction is redundant. 83 ; R2-R5: seb $2, $[[T0]] 84 85 ; R6: div $[[T0:[0-9]+]], $4, $5 86 ; R6: teq $5, $zero, 7 87 ; FIXME: This instruction is redundant. 88 ; R6: seb $2, $[[T0]] 89 90 ; MMR3: div $zero, $4, $5 91 ; MMR3: teq $5, $zero, 7 92 ; MMR3: mflo16 $[[T0:[0-9]+]] 93 ; MMR3: seb $2, $[[T0]] 94 95 ; MMR6: div $[[T0:[0-9]+]], $4, $5 96 ; MMR6: teq $5, $zero, 7 97 ; MMR6: seb $2, $[[T0]] 98 99 %r = sdiv i8 %a, %b 100 ret i8 %r 101 } 102 103 define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) { 104 entry: 105 ; ALL-LABEL: sdiv_i16: 106 107 ; NOT-R2-R6: div $zero, $4, $5 108 ; NOT-R2-R6: teq $5, $zero, 7 109 ; NOT-R2-R6: mflo $[[T0:[0-9]+]] 110 ; FIXME: The sll/sra instructions are redundant since div is signed. 111 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 112 ; NOT-R2-R6: sra $2, $[[T1]], 16 113 114 ; R2-R5: div $zero, $4, $5 115 ; R2-R5: teq $5, $zero, 7 116 ; R2-R5: mflo $[[T0:[0-9]+]] 117 ; FIXME: This is instruction is redundant since div is signed. 118 ; R2-R5: seh $2, $[[T0]] 119 120 ; R6: div $[[T0:[0-9]+]], $4, $5 121 ; R6: teq $5, $zero, 7 122 ; FIXME: This is instruction is redundant since div is signed. 123 ; R6: seh $2, $[[T0]] 124 125 ; MMR3: div $zero, $4, $5 126 ; MMR3: teq $5, $zero, 7 127 ; MMR3: mflo16 $[[T0:[0-9]+]] 128 ; MMR3: seh $2, $[[T0]] 129 130 ; MMR6: div $[[T0:[0-9]+]], $4, $5 131 ; MMR6: teq $5, $zero, 7 132 ; MMR6: seh $2, $[[T0]] 133 134 %r = sdiv i16 %a, %b 135 ret i16 %r 136 } 137 138 define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) { 139 entry: 140 ; ALL-LABEL: sdiv_i32: 141 142 ; NOT-R6: div $zero, $4, $5 143 ; NOT-R6: teq $5, $zero, 7 144 ; NOT-R6: mflo $2 145 146 ; R6: div $2, $4, $5 147 ; R6: teq $5, $zero, 7 148 149 ; MMR3: div $zero, $4, $5 150 ; MMR3: teq $5, $zero, 7 151 ; MMR3: mflo16 $2 152 153 ; MMR6: div $2, $4, $5 154 ; MMR6: teq $5, $zero, 7 155 156 %r = sdiv i32 %a, %b 157 ret i32 %r 158 } 159 160 define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) { 161 entry: 162 ; ALL-LABEL: sdiv_i64: 163 164 ; GP32: lw $25, %call16(__divdi3)($gp) 165 166 ; GP64-NOT-R6: ddiv $zero, $4, $5 167 ; GP64-NOT-R6: teq $5, $zero, 7 168 ; GP64-NOT-R6: mflo $2 169 170 ; 64R6: ddiv $2, $4, $5 171 ; 64R6: teq $5, $zero, 7 172 173 ; MM32: lw $25, %call16(__divdi3)($2) 174 175 %r = sdiv i64 %a, %b 176 ret i64 %r 177 } 178 179 define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { 180 entry: 181 ; ALL-LABEL: sdiv_i128: 182 183 ; GP32: lw $25, %call16(__divti3)($gp) 184 185 ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) 186 ; 64R6: ld $25, %call16(__divti3)($gp) 187 188 ; MM32: lw $25, %call16(__divti3)($16) 189 190 %r = sdiv i128 %a, %b 191 ret i128 %r 192 } 193
