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      1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
      2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
      3 ; RUN:    -check-prefix=M2
      4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
      5 ; RUN:    -check-prefix=CMOV32R1
      6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
      7 ; RUN:    -check-prefix=CMOV32R2
      8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
      9 ; RUN:    -check-prefix=CMOV32R2
     10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
     11 ; RUN:    -check-prefix=CMOV32R2
     12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
     13 ; RUN:    -check-prefix=32R6
     14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
     15 ; RUN:    -check-prefix=M3
     16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
     17 ; RUN:    -check-prefix=CMOV64
     18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
     19 ; RUN:    -check-prefix=CMOV64
     20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
     21 ; RUN:    -check-prefix=CMOV64
     22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
     23 ; RUN:    -check-prefix=CMOV64
     24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
     25 ; RUN:    -check-prefix=CMOV64
     26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
     27 ; RUN:    -check-prefix=64R6
     28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 \
     29 ; RUN:   -asm-show-inst -mattr=+micromips -verify-machineinstrs | FileCheck %s \
     30 ; RUN:    -check-prefix=MM32R3
     31 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
     32 ; RUN:    -check-prefix=MM32R6
     33 
     34 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
     35 ; M2-LABEL: tst_select_i1_double:
     36 ; M2:       # %bb.0: # %entry
     37 ; M2-NEXT:    andi $1, $4, 1
     38 ; M2-NEXT:    bnez $1, $BB0_2
     39 ; M2-NEXT:    nop
     40 ; M2-NEXT:  # %bb.1: # %entry
     41 ; M2-NEXT:    ldc1 $f0, 16($sp)
     42 ; M2-NEXT:    jr $ra
     43 ; M2-NEXT:    nop
     44 ; M2-NEXT:  $BB0_2:
     45 ; M2-NEXT:    mtc1 $7, $f0
     46 ; M2-NEXT:    jr $ra
     47 ; M2-NEXT:    mtc1 $6, $f1
     48 ;
     49 ; CMOV32R1-LABEL: tst_select_i1_double:
     50 ; CMOV32R1:       # %bb.0: # %entry
     51 ; CMOV32R1-NEXT:    mtc1 $7, $f2
     52 ; CMOV32R1-NEXT:    mtc1 $6, $f3
     53 ; CMOV32R1-NEXT:    andi $1, $4, 1
     54 ; CMOV32R1-NEXT:    ldc1 $f0, 16($sp)
     55 ; CMOV32R1-NEXT:    jr $ra
     56 ; CMOV32R1-NEXT:    movn.d $f0, $f2, $1
     57 ;
     58 ; CMOV32R2-LABEL: tst_select_i1_double:
     59 ; CMOV32R2:       # %bb.0: # %entry
     60 ; CMOV32R2-NEXT:    mtc1 $7, $f2
     61 ; CMOV32R2-NEXT:    mthc1 $6, $f2
     62 ; CMOV32R2-NEXT:    andi $1, $4, 1
     63 ; CMOV32R2-NEXT:    ldc1 $f0, 16($sp)
     64 ; CMOV32R2-NEXT:    jr $ra
     65 ; CMOV32R2-NEXT:    movn.d $f0, $f2, $1
     66 ;
     67 ; 32R6-LABEL: tst_select_i1_double:
     68 ; 32R6:       # %bb.0: # %entry
     69 ; 32R6-NEXT:    mtc1 $7, $f1
     70 ; 32R6-NEXT:    mthc1 $6, $f1
     71 ; 32R6-NEXT:    mtc1 $4, $f0
     72 ; 32R6-NEXT:    ldc1 $f2, 16($sp)
     73 ; 32R6-NEXT:    jr $ra
     74 ; 32R6-NEXT:    sel.d $f0, $f2, $f1
     75 ;
     76 ; M3-LABEL: tst_select_i1_double:
     77 ; M3:       # %bb.0: # %entry
     78 ; M3-NEXT:    andi $1, $4, 1
     79 ; M3-NEXT:    bnez $1, .LBB0_2
     80 ; M3-NEXT:    mov.d $f0, $f13
     81 ; M3-NEXT:  # %bb.1: # %entry
     82 ; M3-NEXT:    mov.d $f0, $f14
     83 ; M3-NEXT:  .LBB0_2: # %entry
     84 ; M3-NEXT:    jr $ra
     85 ; M3-NEXT:    nop
     86 ;
     87 ; CMOV64-LABEL: tst_select_i1_double:
     88 ; CMOV64:       # %bb.0: # %entry
     89 ; CMOV64-NEXT:    mov.d $f0, $f14
     90 ; CMOV64-NEXT:    andi $1, $4, 1
     91 ; CMOV64-NEXT:    jr $ra
     92 ; CMOV64-NEXT:    movn.d $f0, $f13, $1
     93 ;
     94 ; 64R6-LABEL: tst_select_i1_double:
     95 ; 64R6:       # %bb.0: # %entry
     96 ; 64R6-NEXT:    mtc1 $4, $f0
     97 ; 64R6-NEXT:    jr $ra
     98 ; 64R6-NEXT:    sel.d $f0, $f14, $f13
     99 ;
    100 ; MM32R3-LABEL: tst_select_i1_double:
    101 ; MM32R3:       # %bb.0: # %entry
    102 ; MM32R3:       mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
    103 ; MM32R3:       mthc1 $6, $f2 # <MCInst #{{.*}} MTHC1_D32_MM
    104 ; MM32R3:       andi16 $2, $4, 1 # <MCInst #{{.*}} ANDI16_MM
    105 ; MM32R3:       ldc1 $f0, 16($sp) # <MCInst #{{.*}} LDC1_MM
    106 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    107 ; MM32R3:       movn.d $f0, $f2, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
    108 ;
    109 ; MM32R6-LABEL: tst_select_i1_double:
    110 ; MM32R6:       # %bb.0: # %entry
    111 ; MM32R6-NEXT:    mtc1 $7, $f1
    112 ; MM32R6-NEXT:    mthc1 $6, $f1
    113 ; MM32R6-NEXT:    mtc1 $4, $f0
    114 ; MM32R6-NEXT:    ldc1 $f2, 16($sp)
    115 ; MM32R6-NEXT:    sel.d $f0, $f2, $f1
    116 ; MM32R6-NEXT:    jrc $ra
    117 entry:
    118   %r = select i1 %s, double %x, double %y
    119   ret double %r
    120 }
    121 
    122 define double @tst_select_i1_double_reordered(double %x, double %y,
    123 ; M2-LABEL: tst_select_i1_double_reordered:
    124 ; M2:       # %bb.0: # %entry
    125 ; M2-NEXT:    lw $1, 16($sp)
    126 ; M2-NEXT:    andi $1, $1, 1
    127 ; M2-NEXT:    bnez $1, $BB1_2
    128 ; M2-NEXT:    mov.d $f0, $f12
    129 ; M2-NEXT:  # %bb.1: # %entry
    130 ; M2-NEXT:    mov.d $f0, $f14
    131 ; M2-NEXT:  $BB1_2: # %entry
    132 ; M2-NEXT:    jr $ra
    133 ; M2-NEXT:    nop
    134 ;
    135 ; CMOV32R1-LABEL: tst_select_i1_double_reordered:
    136 ; CMOV32R1:       # %bb.0: # %entry
    137 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    138 ; CMOV32R1-NEXT:    lw $1, 16($sp)
    139 ; CMOV32R1-NEXT:    andi $1, $1, 1
    140 ; CMOV32R1-NEXT:    jr $ra
    141 ; CMOV32R1-NEXT:    movn.d $f0, $f12, $1
    142 ;
    143 ; CMOV32R2-LABEL: tst_select_i1_double_reordered:
    144 ; CMOV32R2:       # %bb.0: # %entry
    145 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    146 ; CMOV32R2-NEXT:    lw $1, 16($sp)
    147 ; CMOV32R2-NEXT:    andi $1, $1, 1
    148 ; CMOV32R2-NEXT:    jr $ra
    149 ; CMOV32R2-NEXT:    movn.d $f0, $f12, $1
    150 ;
    151 ; 32R6-LABEL: tst_select_i1_double_reordered:
    152 ; 32R6:       # %bb.0: # %entry
    153 ; 32R6-NEXT:    lw $1, 16($sp)
    154 ; 32R6-NEXT:    mtc1 $1, $f0
    155 ; 32R6-NEXT:    jr $ra
    156 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    157 ;
    158 ; M3-LABEL: tst_select_i1_double_reordered:
    159 ; M3:       # %bb.0: # %entry
    160 ; M3-NEXT:    andi $1, $6, 1
    161 ; M3-NEXT:    bnez $1, .LBB1_2
    162 ; M3-NEXT:    mov.d $f0, $f12
    163 ; M3-NEXT:  # %bb.1: # %entry
    164 ; M3-NEXT:    mov.d $f0, $f13
    165 ; M3-NEXT:  .LBB1_2: # %entry
    166 ; M3-NEXT:    jr $ra
    167 ; M3-NEXT:    nop
    168 ;
    169 ; CMOV64-LABEL: tst_select_i1_double_reordered:
    170 ; CMOV64:       # %bb.0: # %entry
    171 ; CMOV64-NEXT:    mov.d $f0, $f13
    172 ; CMOV64-NEXT:    andi $1, $6, 1
    173 ; CMOV64-NEXT:    jr $ra
    174 ; CMOV64-NEXT:    movn.d $f0, $f12, $1
    175 ;
    176 ; 64R6-LABEL: tst_select_i1_double_reordered:
    177 ; 64R6:       # %bb.0: # %entry
    178 ; 64R6-NEXT:    mtc1 $6, $f0
    179 ; 64R6-NEXT:    jr $ra
    180 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    181 ;
    182 ; MM32R3-LABEL: tst_select_i1_double_reordered:
    183 ; MM32R3:       # %bb.0: # %entry
    184 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    185 ; MM32R3:       lw $2, 16($sp) # <MCInst #{{.*}} LWSP_MM
    186 ; MM32R3:       andi16 $2, $2, 1 # <MCInst #{{.*}} ANDI16_MM
    187 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    188 ; MM32R3:       movn.d $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
    189 ;
    190 ; MM32R6-LABEL: tst_select_i1_double_reordered:
    191 ; MM32R6:       # %bb.0: # %entry
    192 ; MM32R6-NEXT:    lw $1, 16($sp)
    193 ; MM32R6-NEXT:    mtc1 $1, $f0
    194 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    195 ; MM32R6-NEXT:    jrc $ra
    196                                               i1 signext %s) {
    197 entry:
    198   %r = select i1 %s, double %x, double %y
    199   ret double %r
    200 }
    201 
    202 define double @tst_select_fcmp_olt_double(double %x, double %y) {
    203 ; M2-LABEL: tst_select_fcmp_olt_double:
    204 ; M2:       # %bb.0: # %entry
    205 ; M2-NEXT:    c.olt.d $f12, $f14
    206 ; M2-NEXT:    bc1t $BB2_2
    207 ; M2-NEXT:    mov.d $f0, $f12
    208 ; M2-NEXT:  # %bb.1: # %entry
    209 ; M2-NEXT:    mov.d $f0, $f14
    210 ; M2-NEXT:  $BB2_2: # %entry
    211 ; M2-NEXT:    jr $ra
    212 ; M2-NEXT:    nop
    213 ;
    214 ; CMOV32R1-LABEL: tst_select_fcmp_olt_double:
    215 ; CMOV32R1:       # %bb.0: # %entry
    216 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    217 ; CMOV32R1-NEXT:    c.olt.d $f12, $f14
    218 ; CMOV32R1-NEXT:    jr $ra
    219 ; CMOV32R1-NEXT:    movt.d $f0, $f12, $fcc0
    220 ;
    221 ; CMOV32R2-LABEL: tst_select_fcmp_olt_double:
    222 ; CMOV32R2:       # %bb.0: # %entry
    223 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    224 ; CMOV32R2-NEXT:    c.olt.d $f12, $f14
    225 ; CMOV32R2-NEXT:    jr $ra
    226 ; CMOV32R2-NEXT:    movt.d $f0, $f12, $fcc0
    227 ;
    228 ; 32R6-LABEL: tst_select_fcmp_olt_double:
    229 ; 32R6:       # %bb.0: # %entry
    230 ; 32R6-NEXT:    cmp.lt.d $f0, $f12, $f14
    231 ; 32R6-NEXT:    mfc1 $1, $f0
    232 ; 32R6-NEXT:    mtc1 $1, $f0
    233 ; 32R6-NEXT:    jr $ra
    234 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    235 ;
    236 ; M3-LABEL: tst_select_fcmp_olt_double:
    237 ; M3:       # %bb.0: # %entry
    238 ; M3-NEXT:    c.olt.d $f12, $f13
    239 ; M3-NEXT:    bc1t .LBB2_2
    240 ; M3-NEXT:    mov.d $f0, $f12
    241 ; M3-NEXT:  # %bb.1: # %entry
    242 ; M3-NEXT:    mov.d $f0, $f13
    243 ; M3-NEXT:  .LBB2_2: # %entry
    244 ; M3-NEXT:    jr $ra
    245 ; M3-NEXT:    nop
    246 ;
    247 ; CMOV64-LABEL: tst_select_fcmp_olt_double:
    248 ; CMOV64:       # %bb.0: # %entry
    249 ; CMOV64-NEXT:    mov.d $f0, $f13
    250 ; CMOV64-NEXT:    c.olt.d $f12, $f13
    251 ; CMOV64-NEXT:    jr $ra
    252 ; CMOV64-NEXT:    movt.d $f0, $f12, $fcc0
    253 ;
    254 ; 64R6-LABEL: tst_select_fcmp_olt_double:
    255 ; 64R6:       # %bb.0: # %entry
    256 ; 64R6-NEXT:    cmp.lt.d $f0, $f12, $f13
    257 ; 64R6-NEXT:    mfc1 $1, $f0
    258 ; 64R6-NEXT:    mtc1 $1, $f0
    259 ; 64R6-NEXT:    jr $ra
    260 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    261 ;
    262 ; MM32R3-LABEL: tst_select_fcmp_olt_double:
    263 ; MM32R3:       # %bb.0: # %entry
    264 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    265 ; MM32R3:       c.olt.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
    266 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    267 ; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
    268 ;
    269 ; MM32R6-LABEL: tst_select_fcmp_olt_double:
    270 ; MM32R6:       # %bb.0: # %entry
    271 ; MM32R6-NEXT:    cmp.lt.d $f0, $f12, $f14
    272 ; MM32R6-NEXT:    mfc1 $1, $f0
    273 ; MM32R6-NEXT:    mtc1 $1, $f0
    274 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    275 ; MM32R6-NEXT:    jrc $ra
    276 entry:
    277   %s = fcmp olt double %x, %y
    278   %r = select i1 %s, double %x, double %y
    279   ret double %r
    280 }
    281 
    282 define double @tst_select_fcmp_ole_double(double %x, double %y) {
    283 ; M2-LABEL: tst_select_fcmp_ole_double:
    284 ; M2:       # %bb.0: # %entry
    285 ; M2-NEXT:    c.ole.d $f12, $f14
    286 ; M2-NEXT:    bc1t $BB3_2
    287 ; M2-NEXT:    mov.d $f0, $f12
    288 ; M2-NEXT:  # %bb.1: # %entry
    289 ; M2-NEXT:    mov.d $f0, $f14
    290 ; M2-NEXT:  $BB3_2: # %entry
    291 ; M2-NEXT:    jr $ra
    292 ; M2-NEXT:    nop
    293 ;
    294 ; CMOV32R1-LABEL: tst_select_fcmp_ole_double:
    295 ; CMOV32R1:       # %bb.0: # %entry
    296 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    297 ; CMOV32R1-NEXT:    c.ole.d $f12, $f14
    298 ; CMOV32R1-NEXT:    jr $ra
    299 ; CMOV32R1-NEXT:    movt.d $f0, $f12, $fcc0
    300 ;
    301 ; CMOV32R2-LABEL: tst_select_fcmp_ole_double:
    302 ; CMOV32R2:       # %bb.0: # %entry
    303 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    304 ; CMOV32R2-NEXT:    c.ole.d $f12, $f14
    305 ; CMOV32R2-NEXT:    jr $ra
    306 ; CMOV32R2-NEXT:    movt.d $f0, $f12, $fcc0
    307 ;
    308 ; 32R6-LABEL: tst_select_fcmp_ole_double:
    309 ; 32R6:       # %bb.0: # %entry
    310 ; 32R6-NEXT:    cmp.le.d $f0, $f12, $f14
    311 ; 32R6-NEXT:    mfc1 $1, $f0
    312 ; 32R6-NEXT:    mtc1 $1, $f0
    313 ; 32R6-NEXT:    jr $ra
    314 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    315 ;
    316 ; M3-LABEL: tst_select_fcmp_ole_double:
    317 ; M3:       # %bb.0: # %entry
    318 ; M3-NEXT:    c.ole.d $f12, $f13
    319 ; M3-NEXT:    bc1t .LBB3_2
    320 ; M3-NEXT:    mov.d $f0, $f12
    321 ; M3-NEXT:  # %bb.1: # %entry
    322 ; M3-NEXT:    mov.d $f0, $f13
    323 ; M3-NEXT:  .LBB3_2: # %entry
    324 ; M3-NEXT:    jr $ra
    325 ; M3-NEXT:    nop
    326 ;
    327 ; CMOV64-LABEL: tst_select_fcmp_ole_double:
    328 ; CMOV64:       # %bb.0: # %entry
    329 ; CMOV64-NEXT:    mov.d $f0, $f13
    330 ; CMOV64-NEXT:    c.ole.d $f12, $f13
    331 ; CMOV64-NEXT:    jr $ra
    332 ; CMOV64-NEXT:    movt.d $f0, $f12, $fcc0
    333 ;
    334 ; 64R6-LABEL: tst_select_fcmp_ole_double:
    335 ; 64R6:       # %bb.0: # %entry
    336 ; 64R6-NEXT:    cmp.le.d $f0, $f12, $f13
    337 ; 64R6-NEXT:    mfc1 $1, $f0
    338 ; 64R6-NEXT:    mtc1 $1, $f0
    339 ; 64R6-NEXT:    jr $ra
    340 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    341 ;
    342 ; MM32R3-LABEL: tst_select_fcmp_ole_double:
    343 ; MM32R3:       # %bb.0: # %entry
    344 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    345 ; MM32R3:       c.ole.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
    346 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    347 ; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
    348 ;
    349 ; MM32R6-LABEL: tst_select_fcmp_ole_double:
    350 ; MM32R6:       # %bb.0: # %entry
    351 ; MM32R6-NEXT:    cmp.le.d $f0, $f12, $f14
    352 ; MM32R6-NEXT:    mfc1 $1, $f0
    353 ; MM32R6-NEXT:    mtc1 $1, $f0
    354 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    355 ; MM32R6-NEXT:    jrc $ra
    356 entry:
    357   %s = fcmp ole double %x, %y
    358   %r = select i1 %s, double %x, double %y
    359   ret double %r
    360 }
    361 
    362 define double @tst_select_fcmp_ogt_double(double %x, double %y) {
    363 ; M2-LABEL: tst_select_fcmp_ogt_double:
    364 ; M2:       # %bb.0: # %entry
    365 ; M2-NEXT:    c.ule.d $f12, $f14
    366 ; M2-NEXT:    bc1f $BB4_2
    367 ; M2-NEXT:    mov.d $f0, $f12
    368 ; M2-NEXT:  # %bb.1: # %entry
    369 ; M2-NEXT:    mov.d $f0, $f14
    370 ; M2-NEXT:  $BB4_2: # %entry
    371 ; M2-NEXT:    jr $ra
    372 ; M2-NEXT:    nop
    373 ;
    374 ; CMOV32R1-LABEL: tst_select_fcmp_ogt_double:
    375 ; CMOV32R1:       # %bb.0: # %entry
    376 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    377 ; CMOV32R1-NEXT:    c.ule.d $f12, $f14
    378 ; CMOV32R1-NEXT:    jr $ra
    379 ; CMOV32R1-NEXT:    movf.d $f0, $f12, $fcc0
    380 ;
    381 ; CMOV32R2-LABEL: tst_select_fcmp_ogt_double:
    382 ; CMOV32R2:       # %bb.0: # %entry
    383 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    384 ; CMOV32R2-NEXT:    c.ule.d $f12, $f14
    385 ; CMOV32R2-NEXT:    jr $ra
    386 ; CMOV32R2-NEXT:    movf.d $f0, $f12, $fcc0
    387 ;
    388 ; 32R6-LABEL: tst_select_fcmp_ogt_double:
    389 ; 32R6:       # %bb.0: # %entry
    390 ; 32R6-NEXT:    cmp.lt.d $f0, $f14, $f12
    391 ; 32R6-NEXT:    mfc1 $1, $f0
    392 ; 32R6-NEXT:    mtc1 $1, $f0
    393 ; 32R6-NEXT:    jr $ra
    394 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    395 ;
    396 ; M3-LABEL: tst_select_fcmp_ogt_double:
    397 ; M3:       # %bb.0: # %entry
    398 ; M3-NEXT:    c.ule.d $f12, $f13
    399 ; M3-NEXT:    bc1f .LBB4_2
    400 ; M3-NEXT:    mov.d $f0, $f12
    401 ; M3-NEXT:  # %bb.1: # %entry
    402 ; M3-NEXT:    mov.d $f0, $f13
    403 ; M3-NEXT:  .LBB4_2: # %entry
    404 ; M3-NEXT:    jr $ra
    405 ; M3-NEXT:    nop
    406 ;
    407 ; CMOV64-LABEL: tst_select_fcmp_ogt_double:
    408 ; CMOV64:       # %bb.0: # %entry
    409 ; CMOV64-NEXT:    mov.d $f0, $f13
    410 ; CMOV64-NEXT:    c.ule.d $f12, $f13
    411 ; CMOV64-NEXT:    jr $ra
    412 ; CMOV64-NEXT:    movf.d $f0, $f12, $fcc0
    413 ;
    414 ; 64R6-LABEL: tst_select_fcmp_ogt_double:
    415 ; 64R6:       # %bb.0: # %entry
    416 ; 64R6-NEXT:    cmp.lt.d $f0, $f13, $f12
    417 ; 64R6-NEXT:    mfc1 $1, $f0
    418 ; 64R6-NEXT:    mtc1 $1, $f0
    419 ; 64R6-NEXT:    jr $ra
    420 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    421 ;
    422 ; MM32R3-LABEL: tst_select_fcmp_ogt_double:
    423 ; MM32R3:       # %bb.0: # %entry
    424 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    425 ; MM32R3:       c.ule.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
    426 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    427 ; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
    428 ;
    429 ; MM32R6-LABEL: tst_select_fcmp_ogt_double:
    430 ; MM32R6:       # %bb.0: # %entry
    431 ; MM32R6-NEXT:    cmp.lt.d $f0, $f14, $f12
    432 ; MM32R6-NEXT:    mfc1 $1, $f0
    433 ; MM32R6-NEXT:    mtc1 $1, $f0
    434 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    435 ; MM32R6-NEXT:    jrc $ra
    436 entry:
    437   %s = fcmp ogt double %x, %y
    438   %r = select i1 %s, double %x, double %y
    439   ret double %r
    440 }
    441 
    442 define double @tst_select_fcmp_oge_double(double %x, double %y) {
    443 ; M2-LABEL: tst_select_fcmp_oge_double:
    444 ; M2:       # %bb.0: # %entry
    445 ; M2-NEXT:    c.ult.d $f12, $f14
    446 ; M2-NEXT:    bc1f $BB5_2
    447 ; M2-NEXT:    mov.d $f0, $f12
    448 ; M2-NEXT:  # %bb.1: # %entry
    449 ; M2-NEXT:    mov.d $f0, $f14
    450 ; M2-NEXT:  $BB5_2: # %entry
    451 ; M2-NEXT:    jr $ra
    452 ; M2-NEXT:    nop
    453 ;
    454 ; CMOV32R1-LABEL: tst_select_fcmp_oge_double:
    455 ; CMOV32R1:       # %bb.0: # %entry
    456 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    457 ; CMOV32R1-NEXT:    c.ult.d $f12, $f14
    458 ; CMOV32R1-NEXT:    jr $ra
    459 ; CMOV32R1-NEXT:    movf.d $f0, $f12, $fcc0
    460 ;
    461 ; CMOV32R2-LABEL: tst_select_fcmp_oge_double:
    462 ; CMOV32R2:       # %bb.0: # %entry
    463 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    464 ; CMOV32R2-NEXT:    c.ult.d $f12, $f14
    465 ; CMOV32R2-NEXT:    jr $ra
    466 ; CMOV32R2-NEXT:    movf.d $f0, $f12, $fcc0
    467 ;
    468 ; 32R6-LABEL: tst_select_fcmp_oge_double:
    469 ; 32R6:       # %bb.0: # %entry
    470 ; 32R6-NEXT:    cmp.le.d $f0, $f14, $f12
    471 ; 32R6-NEXT:    mfc1 $1, $f0
    472 ; 32R6-NEXT:    mtc1 $1, $f0
    473 ; 32R6-NEXT:    jr $ra
    474 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    475 ;
    476 ; M3-LABEL: tst_select_fcmp_oge_double:
    477 ; M3:       # %bb.0: # %entry
    478 ; M3-NEXT:    c.ult.d $f12, $f13
    479 ; M3-NEXT:    bc1f .LBB5_2
    480 ; M3-NEXT:    mov.d $f0, $f12
    481 ; M3-NEXT:  # %bb.1: # %entry
    482 ; M3-NEXT:    mov.d $f0, $f13
    483 ; M3-NEXT:  .LBB5_2: # %entry
    484 ; M3-NEXT:    jr $ra
    485 ; M3-NEXT:    nop
    486 ;
    487 ; CMOV64-LABEL: tst_select_fcmp_oge_double:
    488 ; CMOV64:       # %bb.0: # %entry
    489 ; CMOV64-NEXT:    mov.d $f0, $f13
    490 ; CMOV64-NEXT:    c.ult.d $f12, $f13
    491 ; CMOV64-NEXT:    jr $ra
    492 ; CMOV64-NEXT:    movf.d $f0, $f12, $fcc0
    493 ;
    494 ; 64R6-LABEL: tst_select_fcmp_oge_double:
    495 ; 64R6:       # %bb.0: # %entry
    496 ; 64R6-NEXT:    cmp.le.d $f0, $f13, $f12
    497 ; 64R6-NEXT:    mfc1 $1, $f0
    498 ; 64R6-NEXT:    mtc1 $1, $f0
    499 ; 64R6-NEXT:    jr $ra
    500 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    501 ;
    502 ; MM32R3-LABEL: tst_select_fcmp_oge_double:
    503 ; MM32R3:       # %bb.0: # %entry
    504 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    505 ; MM32R3:       c.ult.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
    506 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    507 ; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
    508 ;
    509 ; MM32R6-LABEL: tst_select_fcmp_oge_double:
    510 ; MM32R6:       # %bb.0: # %entry
    511 ; MM32R6-NEXT:    cmp.le.d $f0, $f14, $f12
    512 ; MM32R6-NEXT:    mfc1 $1, $f0
    513 ; MM32R6-NEXT:    mtc1 $1, $f0
    514 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    515 ; MM32R6-NEXT:    jrc $ra
    516 entry:
    517   %s = fcmp oge double %x, %y
    518   %r = select i1 %s, double %x, double %y
    519   ret double %r
    520 }
    521 
    522 define double @tst_select_fcmp_oeq_double(double %x, double %y) {
    523 ; M2-LABEL: tst_select_fcmp_oeq_double:
    524 ; M2:       # %bb.0: # %entry
    525 ; M2-NEXT:    c.eq.d $f12, $f14
    526 ; M2-NEXT:    bc1t $BB6_2
    527 ; M2-NEXT:    mov.d $f0, $f12
    528 ; M2-NEXT:  # %bb.1: # %entry
    529 ; M2-NEXT:    mov.d $f0, $f14
    530 ; M2-NEXT:  $BB6_2: # %entry
    531 ; M2-NEXT:    jr $ra
    532 ; M2-NEXT:    nop
    533 ;
    534 ; CMOV32R1-LABEL: tst_select_fcmp_oeq_double:
    535 ; CMOV32R1:       # %bb.0: # %entry
    536 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    537 ; CMOV32R1-NEXT:    c.eq.d $f12, $f14
    538 ; CMOV32R1-NEXT:    jr $ra
    539 ; CMOV32R1-NEXT:    movt.d $f0, $f12, $fcc0
    540 ;
    541 ; CMOV32R2-LABEL: tst_select_fcmp_oeq_double:
    542 ; CMOV32R2:       # %bb.0: # %entry
    543 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    544 ; CMOV32R2-NEXT:    c.eq.d $f12, $f14
    545 ; CMOV32R2-NEXT:    jr $ra
    546 ; CMOV32R2-NEXT:    movt.d $f0, $f12, $fcc0
    547 ;
    548 ; 32R6-LABEL: tst_select_fcmp_oeq_double:
    549 ; 32R6:       # %bb.0: # %entry
    550 ; 32R6-NEXT:    cmp.eq.d $f0, $f12, $f14
    551 ; 32R6-NEXT:    mfc1 $1, $f0
    552 ; 32R6-NEXT:    mtc1 $1, $f0
    553 ; 32R6-NEXT:    jr $ra
    554 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    555 ;
    556 ; M3-LABEL: tst_select_fcmp_oeq_double:
    557 ; M3:       # %bb.0: # %entry
    558 ; M3-NEXT:    c.eq.d $f12, $f13
    559 ; M3-NEXT:    bc1t .LBB6_2
    560 ; M3-NEXT:    mov.d $f0, $f12
    561 ; M3-NEXT:  # %bb.1: # %entry
    562 ; M3-NEXT:    mov.d $f0, $f13
    563 ; M3-NEXT:  .LBB6_2: # %entry
    564 ; M3-NEXT:    jr $ra
    565 ; M3-NEXT:    nop
    566 ;
    567 ; CMOV64-LABEL: tst_select_fcmp_oeq_double:
    568 ; CMOV64:       # %bb.0: # %entry
    569 ; CMOV64-NEXT:    mov.d $f0, $f13
    570 ; CMOV64-NEXT:    c.eq.d $f12, $f13
    571 ; CMOV64-NEXT:    jr $ra
    572 ; CMOV64-NEXT:    movt.d $f0, $f12, $fcc0
    573 ;
    574 ; 64R6-LABEL: tst_select_fcmp_oeq_double:
    575 ; 64R6:       # %bb.0: # %entry
    576 ; 64R6-NEXT:    cmp.eq.d $f0, $f12, $f13
    577 ; 64R6-NEXT:    mfc1 $1, $f0
    578 ; 64R6-NEXT:    mtc1 $1, $f0
    579 ; 64R6-NEXT:    jr $ra
    580 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    581 ;
    582 ; MM32R3-LABEL: tst_select_fcmp_oeq_double:
    583 ; MM32R3:       # %bb.0: # %entry
    584 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    585 ; MM32R3:       c.eq.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
    586 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    587 ; MM32R3:       movt.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVT_D32_MM
    588 ;
    589 ; MM32R6-LABEL: tst_select_fcmp_oeq_double:
    590 ; MM32R6:       # %bb.0: # %entry
    591 ; MM32R6-NEXT:    cmp.eq.d $f0, $f12, $f14
    592 ; MM32R6-NEXT:    mfc1 $1, $f0
    593 ; MM32R6-NEXT:    mtc1 $1, $f0
    594 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    595 ; MM32R6-NEXT:    jrc $ra
    596 entry:
    597   %s = fcmp oeq double %x, %y
    598   %r = select i1 %s, double %x, double %y
    599   ret double %r
    600 }
    601 
    602 define double @tst_select_fcmp_one_double(double %x, double %y) {
    603 ; M2-LABEL: tst_select_fcmp_one_double:
    604 ; M2:       # %bb.0: # %entry
    605 ; M2-NEXT:    c.ueq.d $f12, $f14
    606 ; M2-NEXT:    bc1f $BB7_2
    607 ; M2-NEXT:    mov.d $f0, $f12
    608 ; M2-NEXT:  # %bb.1: # %entry
    609 ; M2-NEXT:    mov.d $f0, $f14
    610 ; M2-NEXT:  $BB7_2: # %entry
    611 ; M2-NEXT:    jr $ra
    612 ; M2-NEXT:    nop
    613 ;
    614 ; CMOV32R1-LABEL: tst_select_fcmp_one_double:
    615 ; CMOV32R1:       # %bb.0: # %entry
    616 ; CMOV32R1-NEXT:    mov.d $f0, $f14
    617 ; CMOV32R1-NEXT:    c.ueq.d $f12, $f14
    618 ; CMOV32R1-NEXT:    jr $ra
    619 ; CMOV32R1-NEXT:    movf.d $f0, $f12, $fcc0
    620 ;
    621 ; CMOV32R2-LABEL: tst_select_fcmp_one_double:
    622 ; CMOV32R2:       # %bb.0: # %entry
    623 ; CMOV32R2-NEXT:    mov.d $f0, $f14
    624 ; CMOV32R2-NEXT:    c.ueq.d $f12, $f14
    625 ; CMOV32R2-NEXT:    jr $ra
    626 ; CMOV32R2-NEXT:    movf.d $f0, $f12, $fcc0
    627 ;
    628 ; 32R6-LABEL: tst_select_fcmp_one_double:
    629 ; 32R6:       # %bb.0: # %entry
    630 ; 32R6-NEXT:    cmp.ueq.d $f0, $f12, $f14
    631 ; 32R6-NEXT:    mfc1 $1, $f0
    632 ; 32R6-NEXT:    not $1, $1
    633 ; 32R6-NEXT:    mtc1 $1, $f0
    634 ; 32R6-NEXT:    jr $ra
    635 ; 32R6-NEXT:    sel.d $f0, $f14, $f12
    636 ;
    637 ; M3-LABEL: tst_select_fcmp_one_double:
    638 ; M3:       # %bb.0: # %entry
    639 ; M3-NEXT:    c.ueq.d $f12, $f13
    640 ; M3-NEXT:    bc1f .LBB7_2
    641 ; M3-NEXT:    mov.d $f0, $f12
    642 ; M3-NEXT:  # %bb.1: # %entry
    643 ; M3-NEXT:    mov.d $f0, $f13
    644 ; M3-NEXT:  .LBB7_2: # %entry
    645 ; M3-NEXT:    jr $ra
    646 ; M3-NEXT:    nop
    647 ;
    648 ; CMOV64-LABEL: tst_select_fcmp_one_double:
    649 ; CMOV64:       # %bb.0: # %entry
    650 ; CMOV64-NEXT:    mov.d $f0, $f13
    651 ; CMOV64-NEXT:    c.ueq.d $f12, $f13
    652 ; CMOV64-NEXT:    jr $ra
    653 ; CMOV64-NEXT:    movf.d $f0, $f12, $fcc0
    654 ;
    655 ; 64R6-LABEL: tst_select_fcmp_one_double:
    656 ; 64R6:       # %bb.0: # %entry
    657 ; 64R6-NEXT:    cmp.ueq.d $f0, $f12, $f13
    658 ; 64R6-NEXT:    mfc1 $1, $f0
    659 ; 64R6-NEXT:    not $1, $1
    660 ; 64R6-NEXT:    mtc1 $1, $f0
    661 ; 64R6-NEXT:    jr $ra
    662 ; 64R6-NEXT:    sel.d $f0, $f13, $f12
    663 ;
    664 ; MM32R3-LABEL: tst_select_fcmp_one_double:
    665 ; MM32R3:       # %bb.0: # %entry
    666 ; MM32R3:       mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
    667 ; MM32R3:       c.ueq.d $f12, $f14 # <MCInst #{{.*}} FCMP_D32_MM
    668 ; MM32R3:       jr $ra # <MCInst #{{.*}} JR_MM
    669 ; MM32R3:       movf.d $f0, $f12, $fcc0 # <MCInst #{{.*}} MOVF_D32_MM
    670 ;
    671 ; MM32R6-LABEL: tst_select_fcmp_one_double:
    672 ; MM32R6:       # %bb.0: # %entry
    673 ; MM32R6-NEXT:    cmp.ueq.d $f0, $f12, $f14
    674 ; MM32R6-NEXT:    mfc1 $1, $f0
    675 ; MM32R6-NEXT:    not $1, $1
    676 ; MM32R6-NEXT:    mtc1 $1, $f0
    677 ; MM32R6-NEXT:    sel.d $f0, $f14, $f12
    678 ; MM32R6-NEXT:    jrc $ra
    679 entry:
    680   %s = fcmp one double %x, %y
    681   %r = select i1 %s, double %x, double %y
    682   ret double %r
    683 }
    684