1 ; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2 ; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 3 ; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4 ; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 7 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 9 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 11 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12 ; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 13 14 ; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15 ; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 16 ; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17 ; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 18 ; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19 ; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 20 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 22 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 24 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 26 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27 ; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 28 29 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30 ; RUN: -check-prefixes=ALL,MMR3,MM32 31 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32 ; RUN: -check-prefixes=ALL,MMR6,MM32 33 34 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { 35 entry: 36 ; ALL-LABEL: urem_i1: 37 38 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1 39 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1 40 ; NOT-R6: divu $zero, $[[T1]], $[[T0]] 41 ; NOT-R6: teq $[[T0]], $zero, 7 42 ; NOT-R6: mfhi $[[T2:[0-9]+]] 43 ; NOT-R6: andi $[[T0]], $[[T0]], 1 44 ; NOT-R6: negu $2, $[[T0]] 45 46 ; R6: andi $[[T0:[0-9]+]], $5, 1 47 ; R6: andi $[[T1:[0-9]+]], $4, 1 48 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 49 ; R6: teq $[[T0]], $zero, 7 50 ; R6: negu $2, $[[T2]] 51 52 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 1 53 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 1 54 ; MMR3: divu $zero, $[[T1]], $[[T0]] 55 ; MMR3: teq $[[T0]], $zero, 7 56 ; MMR3: mfhi16 $[[T2:[0-9]+]] 57 ; MMR3: andi16 $[[T0]], $[[T0]], 1 58 ; MMR3: li16 $[[T1:[0-9]+]], 0 59 ; MMR3: subu16 $2, $[[T1]], $[[T0]] 60 61 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 1 62 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 1 63 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 64 ; MMR6: teq $[[T0]], $zero, 7 65 ; MMR6: li16 $[[T3:[0-9]+]], 0 66 ; MMR6: subu16 $2, $[[T3]], $[[T2]] 67 68 %r = urem i1 %a, %b 69 ret i1 %r 70 } 71 72 define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { 73 entry: 74 ; ALL-LABEL: urem_i8: 75 76 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 77 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255 78 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] 79 ; NOT-R2-R6: teq $[[T0]], $zero, 7 80 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] 81 ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24 82 ; NOT-R2-R6: sra $2, $[[T3]], 24 83 84 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255 85 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255 86 ; R2-R5: divu $zero, $[[T1]], $[[T0]] 87 ; R2-R5: teq $[[T0]], $zero, 7 88 ; R2-R5: mfhi $[[T2:[0-9]+]] 89 ; R2-R5: seb $2, $[[T2]] 90 91 ; R6: andi $[[T0:[0-9]+]], $5, 255 92 ; R6: andi $[[T1:[0-9]+]], $4, 255 93 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 94 ; R6: teq $[[T0]], $zero, 7 95 ; R6: seb $2, $[[T2]] 96 97 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 255 98 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 255 99 ; MMR3: divu $zero, $[[T1]], $[[T0]] 100 ; MMR3: teq $[[T0]], $zero, 7 101 ; MMR3: mfhi16 $[[T2:[0-9]+]] 102 ; MMR3: seb $2, $[[T2]] 103 104 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 255 105 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 255 106 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 107 ; MMR6: teq $[[T0]], $zero, 7 108 ; MMR6: seb $2, $[[T2]] 109 110 %r = urem i8 %a, %b 111 ret i8 %r 112 } 113 114 define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { 115 entry: 116 ; ALL-LABEL: urem_i16: 117 118 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 119 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535 120 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] 121 ; NOT-R2-R6: teq $[[T0]], $zero, 7 122 ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] 123 ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16 124 ; NOT-R2-R6: sra $2, $[[T3]], 16 125 126 ; R2-R5: andi $[[T0:[0-9]+]], $5, 65535 127 ; R2-R5: andi $[[T1:[0-9]+]], $4, 65535 128 ; R2-R5: divu $zero, $[[T1]], $[[T0]] 129 ; R2-R5: teq $[[T0]], $zero, 7 130 ; R2-R5: mfhi $[[T3:[0-9]+]] 131 ; R2-R5: seh $2, $[[T2]] 132 133 ; R6: andi $[[T0:[0-9]+]], $5, 65535 134 ; R6: andi $[[T1:[0-9]+]], $4, 65535 135 ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 136 ; R6: teq $[[T0]], $zero, 7 137 ; R6: seh $2, $[[T2]] 138 139 ; MMR3: andi16 $[[T0:[0-9]+]], $5, 65535 140 ; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535 141 ; MMR3: divu $zero, $[[T1]], $[[T0]] 142 ; MMR3: teq $[[T0]], $zero, 7 143 ; MMR3: mfhi16 $[[T2:[0-9]+]] 144 ; MMR3: seh $2, $[[T2]] 145 146 ; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535 147 ; MMR6: andi16 $[[T1:[0-9]+]], $4, 65535 148 ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] 149 ; MMR6: teq $[[T0]], $zero, 7 150 ; MMR6: seh $2, $[[T2]] 151 152 %r = urem i16 %a, %b 153 ret i16 %r 154 } 155 156 define signext i32 @urem_i32(i32 signext %a, i32 signext %b) { 157 entry: 158 ; ALL-LABEL: urem_i32: 159 160 ; NOT-R6: divu $zero, $4, $5 161 ; NOT-R6: teq $5, $zero, 7 162 ; NOT-R6: mfhi $2 163 164 ; R6: modu $2, $4, $5 165 ; R6: teq $5, $zero, 7 166 167 ; MMR3: divu $zero, $4, $5 168 ; MMR3: teq $5, $zero, 7 169 ; MMR3: mfhi16 $2 170 171 ; MMR6: modu $2, $4, $5 172 ; MMR6: teq $5, $zero, 7 173 174 %r = urem i32 %a, %b 175 ret i32 %r 176 } 177 178 define signext i64 @urem_i64(i64 signext %a, i64 signext %b) { 179 entry: 180 ; ALL-LABEL: urem_i64: 181 182 ; GP32: lw $25, %call16(__umoddi3)($gp) 183 184 ; GP64-NOT-R6: ddivu $zero, $4, $5 185 ; GP64-NOT-R6: teq $5, $zero, 7 186 ; GP64-NOT-R6: mfhi $2 187 188 ; 64R6: dmodu $2, $4, $5 189 ; 64R6: teq $5, $zero, 7 190 191 ; MM32: lw $25, %call16(__umoddi3)($2) 192 193 %r = urem i64 %a, %b 194 ret i64 %r 195 } 196 197 define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { 198 entry: 199 ; ALL-LABEL: urem_i128: 200 201 ; GP32: lw $25, %call16(__umodti3)($gp) 202 203 ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) 204 ; 64R6: ld $25, %call16(__umodti3)($gp) 205 206 ; MM32: lw $25, %call16(__umodti3)($16) 207 208 %r = urem i128 %a, %b 209 ret i128 %r 210 } 211
