1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MM 3 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC 4 5 # Test the long branch expansion of various branches 6 7 --- | 8 9 define i32 @a(double %a, double %b) { 10 entry: 11 %cmp = fcmp une double %a, %b 12 br i1 %cmp, label %if.then, label %return 13 14 if.then: 15 call void asm sideeffect ".space 810680", "~{$1}"() 16 ret i32 0 17 18 return: 19 ret i32 1 20 } 21 22 define i32 @b(double %a, double %b) { 23 entry: 24 %cmp = fcmp ueq double %a, %b 25 br i1 %cmp, label %if.then, label %return 26 27 if.then: 28 call void asm sideeffect ".space 810680", "~{$1}"() 29 ret i32 0 30 31 return: 32 ret i32 1 33 } 34 35 ... 36 --- 37 name: a 38 alignment: 2 39 exposesReturnsTwice: false 40 legalized: false 41 regBankSelected: false 42 selected: false 43 failedISel: false 44 tracksRegLiveness: true 45 registers: 46 liveins: 47 - { reg: '$d12_64', virtual-reg: '' } 48 - { reg: '$d14_64', virtual-reg: '' } 49 frameInfo: 50 isFrameAddressTaken: false 51 isReturnAddressTaken: false 52 hasStackMap: false 53 hasPatchPoint: false 54 stackSize: 0 55 offsetAdjustment: 0 56 maxAlignment: 1 57 adjustsStack: false 58 hasCalls: false 59 stackProtector: '' 60 maxCallFrameSize: 0 61 hasOpaqueSPAdjustment: false 62 hasVAStart: false 63 hasMustTailInVarArgFunc: false 64 localFrameSize: 0 65 savePoint: '' 66 restorePoint: '' 67 fixedStack: 68 stack: 69 constants: 70 body: | 71 ; MM-LABEL: name: a 72 ; MM: bb.0.entry: 73 ; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000) 74 ; MM: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64 75 ; MM: BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at 76 ; MM: bb.1.entry: 77 ; MM: successors: %bb.3(0x80000000) 78 ; MM: BC_MMR6 %bb.3 79 ; MM: bb.2.if.then: 80 ; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 81 ; MM: $v0 = LI16_MM 0 82 ; MM: JRC16_MM undef $ra, implicit $v0 83 ; MM: bb.3.return: 84 ; MM: $v0 = LI16_MM 1 85 ; MM: JRC16_MM undef $ra, implicit $v0 86 ; PIC-LABEL: name: a 87 ; PIC: bb.0.entry: 88 ; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000) 89 ; PIC: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64 90 ; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at 91 ; PIC: bb.1.entry: 92 ; PIC: successors: %bb.2(0x80000000) 93 ; PIC: $sp = ADDiu $sp, -8 94 ; PIC: SW $ra, $sp, 0 95 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 96 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 97 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra 98 ; PIC: bb.2.entry: 99 ; PIC: successors: %bb.4(0x80000000) 100 ; PIC: $at = ADDu $ra, $at 101 ; PIC: $ra = LW $sp, 0 102 ; PIC: $sp = ADDiu $sp, 8 103 ; PIC: JIC_MMR6 $at, 0, implicit-def $at 104 ; PIC: bb.3.if.then: 105 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 106 ; PIC: $v0 = LI16_MM 0 107 ; PIC: JRC16_MM undef $ra, implicit $v0 108 ; PIC: bb.4.return: 109 ; PIC: $v0 = LI16_MM 1 110 ; PIC: JRC16_MM undef $ra, implicit $v0 111 bb.0.entry: 112 successors: %bb.1(0x50000000), %bb.2(0x30000000) 113 liveins: $d12_64, $d14_64 114 115 $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64 116 BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $at 117 118 bb.1.if.then: 119 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 120 $v0 = LI16_MM 0 121 PseudoReturn undef $ra, implicit $v0 122 123 bb.2.return: 124 $v0 = LI16_MM 1 125 PseudoReturn undef $ra, implicit $v0 126 127 ... 128 --- 129 name: b 130 alignment: 2 131 exposesReturnsTwice: false 132 legalized: false 133 regBankSelected: false 134 selected: false 135 failedISel: false 136 tracksRegLiveness: true 137 registers: 138 liveins: 139 - { reg: '$d12_64', virtual-reg: '' } 140 - { reg: '$d14_64', virtual-reg: '' } 141 frameInfo: 142 isFrameAddressTaken: false 143 isReturnAddressTaken: false 144 hasStackMap: false 145 hasPatchPoint: false 146 stackSize: 0 147 offsetAdjustment: 0 148 maxAlignment: 1 149 adjustsStack: false 150 hasCalls: false 151 stackProtector: '' 152 maxCallFrameSize: 0 153 hasOpaqueSPAdjustment: false 154 hasVAStart: false 155 hasMustTailInVarArgFunc: false 156 localFrameSize: 0 157 savePoint: '' 158 restorePoint: '' 159 fixedStack: 160 stack: 161 constants: 162 body: | 163 ; MM-LABEL: name: b 164 ; MM: bb.0.entry: 165 ; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000) 166 ; MM: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64 167 ; MM: BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at 168 ; MM: bb.1.entry: 169 ; MM: successors: %bb.3(0x80000000) 170 ; MM: BC_MMR6 %bb.3 171 ; MM: bb.2.if.then: 172 ; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 173 ; MM: $v0 = LI16_MM 0 174 ; MM: JRC16_MM undef $ra, implicit $v0 175 ; MM: bb.3.return: 176 ; MM: $v0 = LI16_MM 1 177 ; MM: JRC16_MM undef $ra, implicit $v0 178 ; PIC-LABEL: name: b 179 ; PIC: bb.0.entry: 180 ; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000) 181 ; PIC: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64 182 ; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at 183 ; PIC: bb.1.entry: 184 ; PIC: successors: %bb.2(0x80000000) 185 ; PIC: $sp = ADDiu $sp, -8 186 ; PIC: SW $ra, $sp, 0 187 ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 188 ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 189 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra 190 ; PIC: bb.2.entry: 191 ; PIC: successors: %bb.4(0x80000000) 192 ; PIC: $at = ADDu $ra, $at 193 ; PIC: $ra = LW $sp, 0 194 ; PIC: $sp = ADDiu $sp, 8 195 ; PIC: JIC_MMR6 $at, 0, implicit-def $at 196 ; PIC: bb.3.if.then: 197 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 198 ; PIC: $v0 = LI16_MM 0 199 ; PIC: JRC16_MM undef $ra, implicit $v0 200 ; PIC: bb.4.return: 201 ; PIC: $v0 = LI16_MM 1 202 ; PIC: JRC16_MM undef $ra, implicit $v0 203 bb.0.entry: 204 successors: %bb.1(0x30000000), %bb.2(0x50000000) 205 liveins: $d12_64, $d14_64 206 207 $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64 208 BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $at 209 210 bb.1.if.then: 211 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 212 $v0 = LI16_MM 0 213 PseudoReturn undef $ra, implicit $v0 214 215 bb.2.return: 216 $v0 = LI16_MM 1 217 PseudoReturn undef $ra, implicit $v0 218 219 ... 220
