1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2 # RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64r5 -mattr=+fp64,+msa %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MSA 3 # RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64r5 -mattr=+fp64,+msa %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC 4 5 # Test the long branch expansion of various branches 6 7 8 9 --- | 10 11 define i32 @_Z4bz_8Dv16_a(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 12 entry: 13 %0 = bitcast i64 %d.coerce0 to <8 x i8> 14 %d.0.vec.expand = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 15 %1 = bitcast i64 %d.coerce1 to <8 x i8> 16 %d.8.vec.expand = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 17 %d.8.vecblend = shufflevector <16 x i8> %d.8.vec.expand, <16 x i8> %d.0.vec.expand, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 18 %2 = tail call i32 @llvm.mips.bz.b(<16 x i8> %d.8.vecblend) 19 %tobool = icmp eq i32 %2, 0 20 br i1 %tobool, label %return, label %if.then 21 22 if.then: 23 tail call void asm sideeffect ".space 810680", "~{$1}"() 24 br label %return 25 26 return: 27 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 28 ret i32 %retval.0 29 } 30 31 declare i32 @llvm.mips.bz.b(<16 x i8>) 32 33 define i32 @_Z5bz_16Dv8_s(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 34 entry: 35 %0 = bitcast i64 %d.coerce0 to <4 x i16> 36 %d.0.vec.expand = shufflevector <4 x i16> %0, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> 37 %1 = bitcast i64 %d.coerce1 to <4 x i16> 38 %d.8.vec.expand = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3> 39 %d.8.vecblend = shufflevector <8 x i16> %d.8.vec.expand, <8 x i16> %d.0.vec.expand, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 40 %2 = tail call i32 @llvm.mips.bz.h(<8 x i16> %d.8.vecblend) 41 %tobool = icmp eq i32 %2, 0 42 br i1 %tobool, label %return, label %if.then 43 44 if.then: 45 tail call void asm sideeffect ".space 810680", "~{$1}"() 46 br label %return 47 48 return: 49 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 50 ret i32 %retval.0 51 } 52 53 declare i32 @llvm.mips.bz.h(<8 x i16>) 54 55 define i32 @_Z5bz_32Dv4_i(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 56 entry: 57 %0 = bitcast i64 %d.coerce0 to <2 x i32> 58 %d.0.vec.expand = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 59 %1 = bitcast i64 %d.coerce1 to <2 x i32> 60 %d.8.vec.expand = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 61 %d.8.vecblend = shufflevector <4 x i32> %d.8.vec.expand, <4 x i32> %d.0.vec.expand, <4 x i32> <i32 4, i32 5, i32 2, i32 3> 62 %2 = tail call i32 @llvm.mips.bz.w(<4 x i32> %d.8.vecblend) 63 %tobool = icmp eq i32 %2, 0 64 br i1 %tobool, label %return, label %if.then 65 66 if.then: 67 tail call void asm sideeffect ".space 810680", "~{$1}"() 68 br label %return 69 70 return: 71 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 72 ret i32 %retval.0 73 } 74 75 declare i32 @llvm.mips.bz.w(<4 x i32>) 76 77 define i32 @_Z5bz_64Dv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 78 entry: 79 %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0 80 %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1 81 %0 = tail call i32 @llvm.mips.bz.d(<2 x i64> %d.8.vec.insert) 82 %tobool = icmp eq i32 %0, 0 83 br i1 %tobool, label %return, label %if.then 84 85 if.then: 86 tail call void asm sideeffect ".space 810680", "~{$1}"() 87 br label %return 88 89 return: 90 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 91 ret i32 %retval.0 92 } 93 94 declare i32 @llvm.mips.bz.d(<2 x i64>) 95 96 define i32 @_Z5bz_64_vDv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 97 entry: 98 %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0 99 %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1 100 %d.16.vec.insert = bitcast <2 x i64> %d.8.vec.insert to <16 x i8> 101 %0 = tail call i32 @llvm.mips.bz.v(<16 x i8> %d.16.vec.insert) 102 %tobool = icmp eq i32 %0, 0 103 br i1 %tobool, label %return, label %if.then 104 105 if.then: 106 tail call void asm sideeffect ".space 810680", "~{$1}"() 107 br label %return 108 109 return: 110 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 111 ret i32 %retval.0 112 } 113 114 declare i32 @llvm.mips.bz.v(<16 x i8>) 115 116 define i32 @_Z5bnz_8Dv16_a(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 117 entry: 118 %0 = bitcast i64 %d.coerce0 to <8 x i8> 119 %d.0.vec.expand = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 120 %1 = bitcast i64 %d.coerce1 to <8 x i8> 121 %d.8.vec.expand = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 122 %d.8.vecblend = shufflevector <16 x i8> %d.8.vec.expand, <16 x i8> %d.0.vec.expand, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 123 %2 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %d.8.vecblend) 124 %tobool = icmp eq i32 %2, 0 125 br i1 %tobool, label %return, label %if.then 126 127 if.then: 128 tail call void asm sideeffect ".space 810680", "~{$1}"() 129 br label %return 130 131 return: 132 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 133 ret i32 %retval.0 134 } 135 136 declare i32 @llvm.mips.bnz.b(<16 x i8>) 137 138 define i32 @_Z6bnz_16Dv8_s(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 139 entry: 140 %0 = bitcast i64 %d.coerce0 to <4 x i16> 141 %d.0.vec.expand = shufflevector <4 x i16> %0, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> 142 %1 = bitcast i64 %d.coerce1 to <4 x i16> 143 %d.8.vec.expand = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3> 144 %d.8.vecblend = shufflevector <8 x i16> %d.8.vec.expand, <8 x i16> %d.0.vec.expand, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7> 145 %2 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %d.8.vecblend) 146 %tobool = icmp eq i32 %2, 0 147 br i1 %tobool, label %return, label %if.then 148 149 if.then: 150 tail call void asm sideeffect ".space 810680", "~{$1}"() 151 br label %return 152 153 return: 154 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 155 ret i32 %retval.0 156 } 157 158 declare i32 @llvm.mips.bnz.h(<8 x i16>) 159 160 define i32 @_Z6bnz_32Dv4_i(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 161 entry: 162 %0 = bitcast i64 %d.coerce0 to <2 x i32> 163 %d.0.vec.expand = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 164 %1 = bitcast i64 %d.coerce1 to <2 x i32> 165 %d.8.vec.expand = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 166 %d.8.vecblend = shufflevector <4 x i32> %d.8.vec.expand, <4 x i32> %d.0.vec.expand, <4 x i32> <i32 4, i32 5, i32 2, i32 3> 167 %2 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %d.8.vecblend) 168 %tobool = icmp eq i32 %2, 0 169 br i1 %tobool, label %return, label %if.then 170 171 if.then: 172 tail call void asm sideeffect ".space 810680", "~{$1}"() 173 br label %return 174 175 return: 176 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 177 ret i32 %retval.0 178 } 179 180 declare i32 @llvm.mips.bnz.w(<4 x i32>) 181 182 define i32 @_Z6bnz_64Dv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 183 entry: 184 %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0 185 %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1 186 %0 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %d.8.vec.insert) 187 %tobool = icmp eq i32 %0, 0 188 br i1 %tobool, label %return, label %if.then 189 190 if.then: 191 tail call void asm sideeffect ".space 810680", "~{$1}"() 192 br label %return 193 194 return: 195 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 196 ret i32 %retval.0 197 } 198 199 declare i32 @llvm.mips.bnz.d(<2 x i64>) 200 201 define i32 @_Z6bnz_64_vDv2_x(i64 inreg %d.coerce0, i64 inreg %d.coerce1) { 202 entry: 203 %d.0.vec.insert = insertelement <2 x i64> undef, i64 %d.coerce0, i32 0 204 %d.8.vec.insert = insertelement <2 x i64> %d.0.vec.insert, i64 %d.coerce1, i32 1 205 %d.16.vec.insert = bitcast <2 x i64> %d.8.vec.insert to <16 x i8> 206 %0 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %d.16.vec.insert) 207 %tobool = icmp eq i32 %0, 0 208 br i1 %tobool, label %return, label %if.then 209 210 if.then: 211 tail call void asm sideeffect ".space 810680", "~{$1}"() 212 br label %return 213 214 return: 215 %retval.0 = phi i32 [ 1, %if.then ], [ 0, %entry ] 216 ret i32 %retval.0 217 } 218 219 declare i32 @llvm.mips.bnz.v(<16 x i8>) 220 221 ... 222 --- 223 name: _Z4bz_8Dv16_a 224 alignment: 3 225 exposesReturnsTwice: false 226 legalized: false 227 regBankSelected: false 228 selected: false 229 failedISel: false 230 tracksRegLiveness: true 231 registers: 232 liveins: 233 - { reg: '$a0_64', virtual-reg: '' } 234 - { reg: '$a1_64', virtual-reg: '' } 235 frameInfo: 236 isFrameAddressTaken: false 237 isReturnAddressTaken: false 238 hasStackMap: false 239 hasPatchPoint: false 240 stackSize: 0 241 offsetAdjustment: 0 242 maxAlignment: 1 243 adjustsStack: false 244 hasCalls: false 245 stackProtector: '' 246 maxCallFrameSize: 0 247 hasOpaqueSPAdjustment: false 248 hasVAStart: false 249 hasMustTailInVarArgFunc: false 250 localFrameSize: 0 251 savePoint: '' 252 restorePoint: '' 253 fixedStack: 254 stack: 255 constants: 256 body: | 257 ; MSA-LABEL: name: _Z4bz_8Dv16_a 258 ; MSA: bb.0.entry: 259 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 260 ; MSA: renamable $w0 = LDI_B 0 261 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 262 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 263 ; MSA: renamable $w0 = SHF_B killed renamable $w0, 27 264 ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177 265 ; MSA: BNZ_B $w0, %bb.2, implicit-def $at { 266 ; MSA: NOP 267 ; MSA: } 268 ; MSA: bb.1.entry: 269 ; MSA: successors: %bb.3(0x80000000) 270 ; MSA: J %bb.3, implicit-def $at { 271 ; MSA: NOP 272 ; MSA: } 273 ; MSA: bb.2.if.then: 274 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 275 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 276 ; MSA: renamable $v0 = ADDiu $zero, 1 277 ; MSA: } 278 ; MSA: bb.3: 279 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 280 ; MSA: renamable $v0 = ADDiu $zero, 0 281 ; MSA: } 282 ; PIC-LABEL: name: _Z4bz_8Dv16_a 283 ; PIC: bb.0.entry: 284 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 285 ; PIC: renamable $w0 = LDI_B 0 286 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 287 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 288 ; PIC: renamable $w0 = SHF_B killed renamable $w0, 27 289 ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177 290 ; PIC: BNZ_B $w0, %bb.3, implicit-def $at { 291 ; PIC: NOP 292 ; PIC: } 293 ; PIC: bb.1.entry: 294 ; PIC: successors: %bb.2(0x80000000) 295 ; PIC: $sp_64 = DADDiu $sp_64, -16 296 ; PIC: SD $ra_64, $sp_64, 0 297 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 298 ; PIC: $at_64 = DSLL $at_64, 16 299 ; PIC: BAL_BR %bb.2, implicit-def $ra { 300 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 301 ; PIC: } 302 ; PIC: bb.2.entry: 303 ; PIC: successors: %bb.4(0x80000000) 304 ; PIC: $at_64 = DADDu $ra_64, $at_64 305 ; PIC: $ra_64 = LD $sp_64, 0 306 ; PIC: JR64 $at_64 { 307 ; PIC: $sp_64 = DADDiu $sp_64, 16 308 ; PIC: } 309 ; PIC: bb.3.if.then: 310 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 311 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 312 ; PIC: renamable $v0 = ADDiu $zero, 1 313 ; PIC: } 314 ; PIC: bb.4: 315 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 316 ; PIC: renamable $v0 = ADDiu $zero, 0 317 ; PIC: } 318 bb.0.entry: 319 successors: %bb.1(0x40000000), %bb.2(0x40000000) 320 liveins: $a0_64, $a1_64 321 322 renamable $w0 = LDI_B 0 323 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 324 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 325 renamable $w0 = SHF_B killed renamable $w0, 27 326 renamable $w0 = SHF_W killed renamable $w0, 177 327 BZ_B killed renamable $w0, %bb.2, implicit-def dead $at 328 329 bb.1.if.then: 330 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 331 renamable $v0 = ADDiu $zero, 1 332 PseudoReturn64 undef $ra_64, implicit killed $v0 333 334 bb.2: 335 renamable $v0 = ADDiu $zero, 0 336 PseudoReturn64 undef $ra_64, implicit killed $v0 337 338 ... 339 --- 340 name: _Z5bz_16Dv8_s 341 alignment: 3 342 exposesReturnsTwice: false 343 legalized: false 344 regBankSelected: false 345 selected: false 346 failedISel: false 347 tracksRegLiveness: true 348 registers: 349 liveins: 350 - { reg: '$a0_64', virtual-reg: '' } 351 - { reg: '$a1_64', virtual-reg: '' } 352 frameInfo: 353 isFrameAddressTaken: false 354 isReturnAddressTaken: false 355 hasStackMap: false 356 hasPatchPoint: false 357 stackSize: 0 358 offsetAdjustment: 0 359 maxAlignment: 1 360 adjustsStack: false 361 hasCalls: false 362 stackProtector: '' 363 maxCallFrameSize: 0 364 hasOpaqueSPAdjustment: false 365 hasVAStart: false 366 hasMustTailInVarArgFunc: false 367 localFrameSize: 0 368 savePoint: '' 369 restorePoint: '' 370 fixedStack: 371 stack: 372 constants: 373 body: | 374 ; MSA-LABEL: name: _Z5bz_16Dv8_s 375 ; MSA: bb.0.entry: 376 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 377 ; MSA: renamable $w0 = LDI_B 0 378 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 379 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 380 ; MSA: renamable $w0 = SHF_H killed renamable $w0, 27 381 ; MSA: BNZ_H $w0, %bb.2, implicit-def $at { 382 ; MSA: NOP 383 ; MSA: } 384 ; MSA: bb.1.entry: 385 ; MSA: successors: %bb.3(0x80000000) 386 ; MSA: J %bb.3, implicit-def $at { 387 ; MSA: NOP 388 ; MSA: } 389 ; MSA: bb.2.if.then: 390 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 391 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 392 ; MSA: renamable $v0 = ADDiu $zero, 1 393 ; MSA: } 394 ; MSA: bb.3: 395 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 396 ; MSA: renamable $v0 = ADDiu $zero, 0 397 ; MSA: } 398 ; PIC-LABEL: name: _Z5bz_16Dv8_s 399 ; PIC: bb.0.entry: 400 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 401 ; PIC: renamable $w0 = LDI_B 0 402 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 403 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 404 ; PIC: renamable $w0 = SHF_H killed renamable $w0, 27 405 ; PIC: BNZ_H $w0, %bb.3, implicit-def $at { 406 ; PIC: NOP 407 ; PIC: } 408 ; PIC: bb.1.entry: 409 ; PIC: successors: %bb.2(0x80000000) 410 ; PIC: $sp_64 = DADDiu $sp_64, -16 411 ; PIC: SD $ra_64, $sp_64, 0 412 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 413 ; PIC: $at_64 = DSLL $at_64, 16 414 ; PIC: BAL_BR %bb.2, implicit-def $ra { 415 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 416 ; PIC: } 417 ; PIC: bb.2.entry: 418 ; PIC: successors: %bb.4(0x80000000) 419 ; PIC: $at_64 = DADDu $ra_64, $at_64 420 ; PIC: $ra_64 = LD $sp_64, 0 421 ; PIC: JR64 $at_64 { 422 ; PIC: $sp_64 = DADDiu $sp_64, 16 423 ; PIC: } 424 ; PIC: bb.3.if.then: 425 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 426 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 427 ; PIC: renamable $v0 = ADDiu $zero, 1 428 ; PIC: } 429 ; PIC: bb.4: 430 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 431 ; PIC: renamable $v0 = ADDiu $zero, 0 432 ; PIC: } 433 bb.0.entry: 434 successors: %bb.1(0x40000000), %bb.2(0x40000000) 435 liveins: $a0_64, $a1_64 436 437 renamable $w0 = LDI_B 0 438 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 439 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 440 renamable $w0 = SHF_H killed renamable $w0, 27 441 BZ_H killed renamable $w0, %bb.2, implicit-def dead $at 442 443 bb.1.if.then: 444 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 445 renamable $v0 = ADDiu $zero, 1 446 PseudoReturn64 undef $ra_64, implicit killed $v0 447 448 bb.2: 449 renamable $v0 = ADDiu $zero, 0 450 PseudoReturn64 undef $ra_64, implicit killed $v0 451 452 ... 453 --- 454 name: _Z5bz_32Dv4_i 455 alignment: 3 456 exposesReturnsTwice: false 457 legalized: false 458 regBankSelected: false 459 selected: false 460 failedISel: false 461 tracksRegLiveness: true 462 registers: 463 liveins: 464 - { reg: '$a0_64', virtual-reg: '' } 465 - { reg: '$a1_64', virtual-reg: '' } 466 frameInfo: 467 isFrameAddressTaken: false 468 isReturnAddressTaken: false 469 hasStackMap: false 470 hasPatchPoint: false 471 stackSize: 0 472 offsetAdjustment: 0 473 maxAlignment: 1 474 adjustsStack: false 475 hasCalls: false 476 stackProtector: '' 477 maxCallFrameSize: 0 478 hasOpaqueSPAdjustment: false 479 hasVAStart: false 480 hasMustTailInVarArgFunc: false 481 localFrameSize: 0 482 savePoint: '' 483 restorePoint: '' 484 fixedStack: 485 stack: 486 constants: 487 body: | 488 ; MSA-LABEL: name: _Z5bz_32Dv4_i 489 ; MSA: bb.0.entry: 490 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 491 ; MSA: renamable $w0 = LDI_B 0 492 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 493 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 494 ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177 495 ; MSA: BNZ_W $w0, %bb.2, implicit-def $at { 496 ; MSA: NOP 497 ; MSA: } 498 ; MSA: bb.1.entry: 499 ; MSA: successors: %bb.3(0x80000000) 500 ; MSA: J %bb.3, implicit-def $at { 501 ; MSA: NOP 502 ; MSA: } 503 ; MSA: bb.2.if.then: 504 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 505 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 506 ; MSA: renamable $v0 = ADDiu $zero, 1 507 ; MSA: } 508 ; MSA: bb.3: 509 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 510 ; MSA: renamable $v0 = ADDiu $zero, 0 511 ; MSA: } 512 ; PIC-LABEL: name: _Z5bz_32Dv4_i 513 ; PIC: bb.0.entry: 514 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 515 ; PIC: renamable $w0 = LDI_B 0 516 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 517 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 518 ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177 519 ; PIC: BNZ_W $w0, %bb.3, implicit-def $at { 520 ; PIC: NOP 521 ; PIC: } 522 ; PIC: bb.1.entry: 523 ; PIC: successors: %bb.2(0x80000000) 524 ; PIC: $sp_64 = DADDiu $sp_64, -16 525 ; PIC: SD $ra_64, $sp_64, 0 526 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 527 ; PIC: $at_64 = DSLL $at_64, 16 528 ; PIC: BAL_BR %bb.2, implicit-def $ra { 529 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 530 ; PIC: } 531 ; PIC: bb.2.entry: 532 ; PIC: successors: %bb.4(0x80000000) 533 ; PIC: $at_64 = DADDu $ra_64, $at_64 534 ; PIC: $ra_64 = LD $sp_64, 0 535 ; PIC: JR64 $at_64 { 536 ; PIC: $sp_64 = DADDiu $sp_64, 16 537 ; PIC: } 538 ; PIC: bb.3.if.then: 539 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 540 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 541 ; PIC: renamable $v0 = ADDiu $zero, 1 542 ; PIC: } 543 ; PIC: bb.4: 544 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 545 ; PIC: renamable $v0 = ADDiu $zero, 0 546 ; PIC: } 547 bb.0.entry: 548 successors: %bb.1(0x40000000), %bb.2(0x40000000) 549 liveins: $a0_64, $a1_64 550 551 renamable $w0 = LDI_B 0 552 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 553 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 554 renamable $w0 = SHF_W killed renamable $w0, 177 555 BZ_W killed renamable $w0, %bb.2, implicit-def dead $at 556 557 bb.1.if.then: 558 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 559 renamable $v0 = ADDiu $zero, 1 560 PseudoReturn64 undef $ra_64, implicit killed $v0 561 562 bb.2: 563 renamable $v0 = ADDiu $zero, 0 564 PseudoReturn64 undef $ra_64, implicit killed $v0 565 566 ... 567 --- 568 name: _Z5bz_64Dv2_x 569 alignment: 3 570 exposesReturnsTwice: false 571 legalized: false 572 regBankSelected: false 573 selected: false 574 failedISel: false 575 tracksRegLiveness: true 576 registers: 577 liveins: 578 - { reg: '$a0_64', virtual-reg: '' } 579 - { reg: '$a1_64', virtual-reg: '' } 580 frameInfo: 581 isFrameAddressTaken: false 582 isReturnAddressTaken: false 583 hasStackMap: false 584 hasPatchPoint: false 585 stackSize: 0 586 offsetAdjustment: 0 587 maxAlignment: 1 588 adjustsStack: false 589 hasCalls: false 590 stackProtector: '' 591 maxCallFrameSize: 0 592 hasOpaqueSPAdjustment: false 593 hasVAStart: false 594 hasMustTailInVarArgFunc: false 595 localFrameSize: 0 596 savePoint: '' 597 restorePoint: '' 598 fixedStack: 599 stack: 600 constants: 601 body: | 602 ; MSA-LABEL: name: _Z5bz_64Dv2_x 603 ; MSA: bb.0.entry: 604 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 605 ; MSA: renamable $w0 = LDI_B 0 606 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 607 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 608 ; MSA: BNZ_D $w0, %bb.2, implicit-def $at { 609 ; MSA: NOP 610 ; MSA: } 611 ; MSA: bb.1.entry: 612 ; MSA: successors: %bb.3(0x80000000) 613 ; MSA: J %bb.3, implicit-def $at { 614 ; MSA: NOP 615 ; MSA: } 616 ; MSA: bb.2.if.then: 617 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 618 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 619 ; MSA: renamable $v0 = ADDiu $zero, 1 620 ; MSA: } 621 ; MSA: bb.3: 622 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 623 ; MSA: renamable $v0 = ADDiu $zero, 0 624 ; MSA: } 625 ; PIC-LABEL: name: _Z5bz_64Dv2_x 626 ; PIC: bb.0.entry: 627 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 628 ; PIC: renamable $w0 = LDI_B 0 629 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 630 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 631 ; PIC: BNZ_D $w0, %bb.3, implicit-def $at { 632 ; PIC: NOP 633 ; PIC: } 634 ; PIC: bb.1.entry: 635 ; PIC: successors: %bb.2(0x80000000) 636 ; PIC: $sp_64 = DADDiu $sp_64, -16 637 ; PIC: SD $ra_64, $sp_64, 0 638 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 639 ; PIC: $at_64 = DSLL $at_64, 16 640 ; PIC: BAL_BR %bb.2, implicit-def $ra { 641 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 642 ; PIC: } 643 ; PIC: bb.2.entry: 644 ; PIC: successors: %bb.4(0x80000000) 645 ; PIC: $at_64 = DADDu $ra_64, $at_64 646 ; PIC: $ra_64 = LD $sp_64, 0 647 ; PIC: JR64 $at_64 { 648 ; PIC: $sp_64 = DADDiu $sp_64, 16 649 ; PIC: } 650 ; PIC: bb.3.if.then: 651 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 652 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 653 ; PIC: renamable $v0 = ADDiu $zero, 1 654 ; PIC: } 655 ; PIC: bb.4: 656 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 657 ; PIC: renamable $v0 = ADDiu $zero, 0 658 ; PIC: } 659 bb.0.entry: 660 successors: %bb.1(0x40000000), %bb.2(0x40000000) 661 liveins: $a0_64, $a1_64 662 663 renamable $w0 = LDI_B 0 664 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 665 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 666 BZ_D killed renamable $w0, %bb.2, implicit-def dead $at 667 668 bb.1.if.then: 669 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 670 renamable $v0 = ADDiu $zero, 1 671 PseudoReturn64 undef $ra_64, implicit killed $v0 672 673 bb.2: 674 renamable $v0 = ADDiu $zero, 0 675 PseudoReturn64 undef $ra_64, implicit killed $v0 676 677 ... 678 --- 679 name: _Z5bz_64_vDv2_x 680 alignment: 3 681 exposesReturnsTwice: false 682 legalized: false 683 regBankSelected: false 684 selected: false 685 failedISel: false 686 tracksRegLiveness: true 687 registers: 688 liveins: 689 - { reg: '$a0_64', virtual-reg: '' } 690 - { reg: '$a1_64', virtual-reg: '' } 691 frameInfo: 692 isFrameAddressTaken: false 693 isReturnAddressTaken: false 694 hasStackMap: false 695 hasPatchPoint: false 696 stackSize: 0 697 offsetAdjustment: 0 698 maxAlignment: 1 699 adjustsStack: false 700 hasCalls: false 701 stackProtector: '' 702 maxCallFrameSize: 0 703 hasOpaqueSPAdjustment: false 704 hasVAStart: false 705 hasMustTailInVarArgFunc: false 706 localFrameSize: 0 707 savePoint: '' 708 restorePoint: '' 709 fixedStack: 710 stack: 711 constants: 712 body: | 713 ; MSA-LABEL: name: _Z5bz_64_vDv2_x 714 ; MSA: bb.0.entry: 715 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 716 ; MSA: renamable $w0 = LDI_B 0 717 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 718 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 719 ; MSA: BNZ_V $w0, %bb.2, implicit-def $at { 720 ; MSA: NOP 721 ; MSA: } 722 ; MSA: bb.1.entry: 723 ; MSA: successors: %bb.3(0x80000000) 724 ; MSA: J %bb.3, implicit-def $at { 725 ; MSA: NOP 726 ; MSA: } 727 ; MSA: bb.2.if.then: 728 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 729 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 730 ; MSA: renamable $v0 = ADDiu $zero, 1 731 ; MSA: } 732 ; MSA: bb.3: 733 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 734 ; MSA: renamable $v0 = ADDiu $zero, 0 735 ; MSA: } 736 ; PIC-LABEL: name: _Z5bz_64_vDv2_x 737 ; PIC: bb.0.entry: 738 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 739 ; PIC: renamable $w0 = LDI_B 0 740 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 741 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 742 ; PIC: BNZ_V $w0, %bb.3, implicit-def $at { 743 ; PIC: NOP 744 ; PIC: } 745 ; PIC: bb.1.entry: 746 ; PIC: successors: %bb.2(0x80000000) 747 ; PIC: $sp_64 = DADDiu $sp_64, -16 748 ; PIC: SD $ra_64, $sp_64, 0 749 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 750 ; PIC: $at_64 = DSLL $at_64, 16 751 ; PIC: BAL_BR %bb.2, implicit-def $ra { 752 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 753 ; PIC: } 754 ; PIC: bb.2.entry: 755 ; PIC: successors: %bb.4(0x80000000) 756 ; PIC: $at_64 = DADDu $ra_64, $at_64 757 ; PIC: $ra_64 = LD $sp_64, 0 758 ; PIC: JR64 $at_64 { 759 ; PIC: $sp_64 = DADDiu $sp_64, 16 760 ; PIC: } 761 ; PIC: bb.3.if.then: 762 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 763 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 764 ; PIC: renamable $v0 = ADDiu $zero, 1 765 ; PIC: } 766 ; PIC: bb.4: 767 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 768 ; PIC: renamable $v0 = ADDiu $zero, 0 769 ; PIC: } 770 bb.0.entry: 771 successors: %bb.1(0x40000000), %bb.2(0x40000000) 772 liveins: $a0_64, $a1_64 773 774 renamable $w0 = LDI_B 0 775 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 776 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 777 BZ_V killed renamable $w0, %bb.2, implicit-def dead $at 778 779 bb.1.if.then: 780 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 781 renamable $v0 = ADDiu $zero, 1 782 PseudoReturn64 undef $ra_64, implicit killed $v0 783 784 bb.2: 785 renamable $v0 = ADDiu $zero, 0 786 PseudoReturn64 undef $ra_64, implicit killed $v0 787 788 ... 789 --- 790 name: _Z5bnz_8Dv16_a 791 alignment: 3 792 exposesReturnsTwice: false 793 legalized: false 794 regBankSelected: false 795 selected: false 796 failedISel: false 797 tracksRegLiveness: true 798 registers: 799 liveins: 800 - { reg: '$a0_64', virtual-reg: '' } 801 - { reg: '$a1_64', virtual-reg: '' } 802 frameInfo: 803 isFrameAddressTaken: false 804 isReturnAddressTaken: false 805 hasStackMap: false 806 hasPatchPoint: false 807 stackSize: 0 808 offsetAdjustment: 0 809 maxAlignment: 1 810 adjustsStack: false 811 hasCalls: false 812 stackProtector: '' 813 maxCallFrameSize: 0 814 hasOpaqueSPAdjustment: false 815 hasVAStart: false 816 hasMustTailInVarArgFunc: false 817 localFrameSize: 0 818 savePoint: '' 819 restorePoint: '' 820 fixedStack: 821 stack: 822 constants: 823 body: | 824 ; MSA-LABEL: name: _Z5bnz_8Dv16_a 825 ; MSA: bb.0.entry: 826 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 827 ; MSA: renamable $w0 = LDI_B 0 828 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 829 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 830 ; MSA: renamable $w0 = SHF_B killed renamable $w0, 27 831 ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177 832 ; MSA: BZ_B $w0, %bb.2, implicit-def $at { 833 ; MSA: NOP 834 ; MSA: } 835 ; MSA: bb.1.entry: 836 ; MSA: successors: %bb.3(0x80000000) 837 ; MSA: J %bb.3, implicit-def $at { 838 ; MSA: NOP 839 ; MSA: } 840 ; MSA: bb.2.if.then: 841 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 842 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 843 ; MSA: renamable $v0 = ADDiu $zero, 1 844 ; MSA: } 845 ; MSA: bb.3: 846 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 847 ; MSA: renamable $v0 = ADDiu $zero, 0 848 ; MSA: } 849 ; PIC-LABEL: name: _Z5bnz_8Dv16_a 850 ; PIC: bb.0.entry: 851 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 852 ; PIC: renamable $w0 = LDI_B 0 853 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 854 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 855 ; PIC: renamable $w0 = SHF_B killed renamable $w0, 27 856 ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177 857 ; PIC: BZ_B $w0, %bb.3, implicit-def $at { 858 ; PIC: NOP 859 ; PIC: } 860 ; PIC: bb.1.entry: 861 ; PIC: successors: %bb.2(0x80000000) 862 ; PIC: $sp_64 = DADDiu $sp_64, -16 863 ; PIC: SD $ra_64, $sp_64, 0 864 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 865 ; PIC: $at_64 = DSLL $at_64, 16 866 ; PIC: BAL_BR %bb.2, implicit-def $ra { 867 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 868 ; PIC: } 869 ; PIC: bb.2.entry: 870 ; PIC: successors: %bb.4(0x80000000) 871 ; PIC: $at_64 = DADDu $ra_64, $at_64 872 ; PIC: $ra_64 = LD $sp_64, 0 873 ; PIC: JR64 $at_64 { 874 ; PIC: $sp_64 = DADDiu $sp_64, 16 875 ; PIC: } 876 ; PIC: bb.3.if.then: 877 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 878 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 879 ; PIC: renamable $v0 = ADDiu $zero, 1 880 ; PIC: } 881 ; PIC: bb.4: 882 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 883 ; PIC: renamable $v0 = ADDiu $zero, 0 884 ; PIC: } 885 bb.0.entry: 886 successors: %bb.1(0x40000000), %bb.2(0x40000000) 887 liveins: $a0_64, $a1_64 888 889 renamable $w0 = LDI_B 0 890 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 891 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 892 renamable $w0 = SHF_B killed renamable $w0, 27 893 renamable $w0 = SHF_W killed renamable $w0, 177 894 BNZ_B killed renamable $w0, %bb.2, implicit-def dead $at 895 896 bb.1.if.then: 897 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 898 renamable $v0 = ADDiu $zero, 1 899 PseudoReturn64 undef $ra_64, implicit killed $v0 900 901 bb.2: 902 renamable $v0 = ADDiu $zero, 0 903 PseudoReturn64 undef $ra_64, implicit killed $v0 904 905 ... 906 --- 907 name: _Z6bnz_16Dv8_s 908 alignment: 3 909 exposesReturnsTwice: false 910 legalized: false 911 regBankSelected: false 912 selected: false 913 failedISel: false 914 tracksRegLiveness: true 915 registers: 916 liveins: 917 - { reg: '$a0_64', virtual-reg: '' } 918 - { reg: '$a1_64', virtual-reg: '' } 919 frameInfo: 920 isFrameAddressTaken: false 921 isReturnAddressTaken: false 922 hasStackMap: false 923 hasPatchPoint: false 924 stackSize: 0 925 offsetAdjustment: 0 926 maxAlignment: 1 927 adjustsStack: false 928 hasCalls: false 929 stackProtector: '' 930 maxCallFrameSize: 0 931 hasOpaqueSPAdjustment: false 932 hasVAStart: false 933 hasMustTailInVarArgFunc: false 934 localFrameSize: 0 935 savePoint: '' 936 restorePoint: '' 937 fixedStack: 938 stack: 939 constants: 940 body: | 941 ; MSA-LABEL: name: _Z6bnz_16Dv8_s 942 ; MSA: bb.0.entry: 943 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 944 ; MSA: renamable $w0 = LDI_B 0 945 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 946 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 947 ; MSA: renamable $w0 = SHF_H killed renamable $w0, 27 948 ; MSA: BZ_H $w0, %bb.2, implicit-def $at { 949 ; MSA: NOP 950 ; MSA: } 951 ; MSA: bb.1.entry: 952 ; MSA: successors: %bb.3(0x80000000) 953 ; MSA: J %bb.3, implicit-def $at { 954 ; MSA: NOP 955 ; MSA: } 956 ; MSA: bb.2.if.then: 957 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 958 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 959 ; MSA: renamable $v0 = ADDiu $zero, 1 960 ; MSA: } 961 ; MSA: bb.3: 962 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 963 ; MSA: renamable $v0 = ADDiu $zero, 0 964 ; MSA: } 965 ; PIC-LABEL: name: _Z6bnz_16Dv8_s 966 ; PIC: bb.0.entry: 967 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 968 ; PIC: renamable $w0 = LDI_B 0 969 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 970 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 971 ; PIC: renamable $w0 = SHF_H killed renamable $w0, 27 972 ; PIC: BZ_H $w0, %bb.3, implicit-def $at { 973 ; PIC: NOP 974 ; PIC: } 975 ; PIC: bb.1.entry: 976 ; PIC: successors: %bb.2(0x80000000) 977 ; PIC: $sp_64 = DADDiu $sp_64, -16 978 ; PIC: SD $ra_64, $sp_64, 0 979 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 980 ; PIC: $at_64 = DSLL $at_64, 16 981 ; PIC: BAL_BR %bb.2, implicit-def $ra { 982 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 983 ; PIC: } 984 ; PIC: bb.2.entry: 985 ; PIC: successors: %bb.4(0x80000000) 986 ; PIC: $at_64 = DADDu $ra_64, $at_64 987 ; PIC: $ra_64 = LD $sp_64, 0 988 ; PIC: JR64 $at_64 { 989 ; PIC: $sp_64 = DADDiu $sp_64, 16 990 ; PIC: } 991 ; PIC: bb.3.if.then: 992 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 993 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 994 ; PIC: renamable $v0 = ADDiu $zero, 1 995 ; PIC: } 996 ; PIC: bb.4: 997 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 998 ; PIC: renamable $v0 = ADDiu $zero, 0 999 ; PIC: } 1000 bb.0.entry: 1001 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1002 liveins: $a0_64, $a1_64 1003 1004 renamable $w0 = LDI_B 0 1005 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1006 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1007 renamable $w0 = SHF_H killed renamable $w0, 27 1008 BNZ_H killed renamable $w0, %bb.2, implicit-def dead $at 1009 1010 bb.1.if.then: 1011 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1012 renamable $v0 = ADDiu $zero, 1 1013 PseudoReturn64 undef $ra_64, implicit killed $v0 1014 1015 bb.2: 1016 renamable $v0 = ADDiu $zero, 0 1017 PseudoReturn64 undef $ra_64, implicit killed $v0 1018 1019 ... 1020 --- 1021 name: _Z6bnz_32Dv4_i 1022 alignment: 3 1023 exposesReturnsTwice: false 1024 legalized: false 1025 regBankSelected: false 1026 selected: false 1027 failedISel: false 1028 tracksRegLiveness: true 1029 registers: 1030 liveins: 1031 - { reg: '$a0_64', virtual-reg: '' } 1032 - { reg: '$a1_64', virtual-reg: '' } 1033 frameInfo: 1034 isFrameAddressTaken: false 1035 isReturnAddressTaken: false 1036 hasStackMap: false 1037 hasPatchPoint: false 1038 stackSize: 0 1039 offsetAdjustment: 0 1040 maxAlignment: 1 1041 adjustsStack: false 1042 hasCalls: false 1043 stackProtector: '' 1044 maxCallFrameSize: 0 1045 hasOpaqueSPAdjustment: false 1046 hasVAStart: false 1047 hasMustTailInVarArgFunc: false 1048 localFrameSize: 0 1049 savePoint: '' 1050 restorePoint: '' 1051 fixedStack: 1052 stack: 1053 constants: 1054 body: | 1055 ; MSA-LABEL: name: _Z6bnz_32Dv4_i 1056 ; MSA: bb.0.entry: 1057 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 1058 ; MSA: renamable $w0 = LDI_B 0 1059 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1060 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1061 ; MSA: renamable $w0 = SHF_W killed renamable $w0, 177 1062 ; MSA: BZ_W $w0, %bb.2, implicit-def $at { 1063 ; MSA: NOP 1064 ; MSA: } 1065 ; MSA: bb.1.entry: 1066 ; MSA: successors: %bb.3(0x80000000) 1067 ; MSA: J %bb.3, implicit-def $at { 1068 ; MSA: NOP 1069 ; MSA: } 1070 ; MSA: bb.2.if.then: 1071 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1072 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1073 ; MSA: renamable $v0 = ADDiu $zero, 1 1074 ; MSA: } 1075 ; MSA: bb.3: 1076 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1077 ; MSA: renamable $v0 = ADDiu $zero, 0 1078 ; MSA: } 1079 ; PIC-LABEL: name: _Z6bnz_32Dv4_i 1080 ; PIC: bb.0.entry: 1081 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 1082 ; PIC: renamable $w0 = LDI_B 0 1083 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1084 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1085 ; PIC: renamable $w0 = SHF_W killed renamable $w0, 177 1086 ; PIC: BZ_W $w0, %bb.3, implicit-def $at { 1087 ; PIC: NOP 1088 ; PIC: } 1089 ; PIC: bb.1.entry: 1090 ; PIC: successors: %bb.2(0x80000000) 1091 ; PIC: $sp_64 = DADDiu $sp_64, -16 1092 ; PIC: SD $ra_64, $sp_64, 0 1093 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 1094 ; PIC: $at_64 = DSLL $at_64, 16 1095 ; PIC: BAL_BR %bb.2, implicit-def $ra { 1096 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 1097 ; PIC: } 1098 ; PIC: bb.2.entry: 1099 ; PIC: successors: %bb.4(0x80000000) 1100 ; PIC: $at_64 = DADDu $ra_64, $at_64 1101 ; PIC: $ra_64 = LD $sp_64, 0 1102 ; PIC: JR64 $at_64 { 1103 ; PIC: $sp_64 = DADDiu $sp_64, 16 1104 ; PIC: } 1105 ; PIC: bb.3.if.then: 1106 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1107 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1108 ; PIC: renamable $v0 = ADDiu $zero, 1 1109 ; PIC: } 1110 ; PIC: bb.4: 1111 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1112 ; PIC: renamable $v0 = ADDiu $zero, 0 1113 ; PIC: } 1114 bb.0.entry: 1115 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1116 liveins: $a0_64, $a1_64 1117 1118 renamable $w0 = LDI_B 0 1119 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1120 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1121 renamable $w0 = SHF_W killed renamable $w0, 177 1122 BNZ_W killed renamable $w0, %bb.2, implicit-def dead $at 1123 1124 bb.1.if.then: 1125 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1126 renamable $v0 = ADDiu $zero, 1 1127 PseudoReturn64 undef $ra_64, implicit killed $v0 1128 1129 bb.2: 1130 renamable $v0 = ADDiu $zero, 0 1131 PseudoReturn64 undef $ra_64, implicit killed $v0 1132 1133 ... 1134 --- 1135 name: _Z6bnz_64Dv2_x 1136 alignment: 3 1137 exposesReturnsTwice: false 1138 legalized: false 1139 regBankSelected: false 1140 selected: false 1141 failedISel: false 1142 tracksRegLiveness: true 1143 registers: 1144 liveins: 1145 - { reg: '$a0_64', virtual-reg: '' } 1146 - { reg: '$a1_64', virtual-reg: '' } 1147 frameInfo: 1148 isFrameAddressTaken: false 1149 isReturnAddressTaken: false 1150 hasStackMap: false 1151 hasPatchPoint: false 1152 stackSize: 0 1153 offsetAdjustment: 0 1154 maxAlignment: 1 1155 adjustsStack: false 1156 hasCalls: false 1157 stackProtector: '' 1158 maxCallFrameSize: 0 1159 hasOpaqueSPAdjustment: false 1160 hasVAStart: false 1161 hasMustTailInVarArgFunc: false 1162 localFrameSize: 0 1163 savePoint: '' 1164 restorePoint: '' 1165 fixedStack: 1166 stack: 1167 constants: 1168 body: | 1169 ; MSA-LABEL: name: _Z6bnz_64Dv2_x 1170 ; MSA: bb.0.entry: 1171 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 1172 ; MSA: renamable $w0 = LDI_B 0 1173 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1174 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1175 ; MSA: BZ_D $w0, %bb.2, implicit-def $at { 1176 ; MSA: NOP 1177 ; MSA: } 1178 ; MSA: bb.1.entry: 1179 ; MSA: successors: %bb.3(0x80000000) 1180 ; MSA: J %bb.3, implicit-def $at { 1181 ; MSA: NOP 1182 ; MSA: } 1183 ; MSA: bb.2.if.then: 1184 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1185 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1186 ; MSA: renamable $v0 = ADDiu $zero, 1 1187 ; MSA: } 1188 ; MSA: bb.3: 1189 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1190 ; MSA: renamable $v0 = ADDiu $zero, 0 1191 ; MSA: } 1192 ; PIC-LABEL: name: _Z6bnz_64Dv2_x 1193 ; PIC: bb.0.entry: 1194 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 1195 ; PIC: renamable $w0 = LDI_B 0 1196 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1197 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1198 ; PIC: BZ_D $w0, %bb.3, implicit-def $at { 1199 ; PIC: NOP 1200 ; PIC: } 1201 ; PIC: bb.1.entry: 1202 ; PIC: successors: %bb.2(0x80000000) 1203 ; PIC: $sp_64 = DADDiu $sp_64, -16 1204 ; PIC: SD $ra_64, $sp_64, 0 1205 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 1206 ; PIC: $at_64 = DSLL $at_64, 16 1207 ; PIC: BAL_BR %bb.2, implicit-def $ra { 1208 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 1209 ; PIC: } 1210 ; PIC: bb.2.entry: 1211 ; PIC: successors: %bb.4(0x80000000) 1212 ; PIC: $at_64 = DADDu $ra_64, $at_64 1213 ; PIC: $ra_64 = LD $sp_64, 0 1214 ; PIC: JR64 $at_64 { 1215 ; PIC: $sp_64 = DADDiu $sp_64, 16 1216 ; PIC: } 1217 ; PIC: bb.3.if.then: 1218 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1219 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1220 ; PIC: renamable $v0 = ADDiu $zero, 1 1221 ; PIC: } 1222 ; PIC: bb.4: 1223 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1224 ; PIC: renamable $v0 = ADDiu $zero, 0 1225 ; PIC: } 1226 bb.0.entry: 1227 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1228 liveins: $a0_64, $a1_64 1229 1230 renamable $w0 = LDI_B 0 1231 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1232 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1233 BNZ_D killed renamable $w0, %bb.2, implicit-def dead $at 1234 1235 bb.1.if.then: 1236 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1237 renamable $v0 = ADDiu $zero, 1 1238 PseudoReturn64 undef $ra_64, implicit killed $v0 1239 1240 bb.2: 1241 renamable $v0 = ADDiu $zero, 0 1242 PseudoReturn64 undef $ra_64, implicit killed $v0 1243 1244 ... 1245 --- 1246 name: _Z6bnz_64_vDv2_x 1247 alignment: 3 1248 exposesReturnsTwice: false 1249 legalized: false 1250 regBankSelected: false 1251 selected: false 1252 failedISel: false 1253 tracksRegLiveness: true 1254 registers: 1255 liveins: 1256 - { reg: '$a0_64', virtual-reg: '' } 1257 - { reg: '$a1_64', virtual-reg: '' } 1258 frameInfo: 1259 isFrameAddressTaken: false 1260 isReturnAddressTaken: false 1261 hasStackMap: false 1262 hasPatchPoint: false 1263 stackSize: 0 1264 offsetAdjustment: 0 1265 maxAlignment: 1 1266 adjustsStack: false 1267 hasCalls: false 1268 stackProtector: '' 1269 maxCallFrameSize: 0 1270 hasOpaqueSPAdjustment: false 1271 hasVAStart: false 1272 hasMustTailInVarArgFunc: false 1273 localFrameSize: 0 1274 savePoint: '' 1275 restorePoint: '' 1276 fixedStack: 1277 stack: 1278 constants: 1279 body: | 1280 ; MSA-LABEL: name: _Z6bnz_64_vDv2_x 1281 ; MSA: bb.0.entry: 1282 ; MSA: successors: %bb.2(0x40000000), %bb.1(0x40000000) 1283 ; MSA: renamable $w0 = LDI_B 0 1284 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1285 ; MSA: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1286 ; MSA: BZ_V $w0, %bb.2, implicit-def $at { 1287 ; MSA: NOP 1288 ; MSA: } 1289 ; MSA: bb.1.entry: 1290 ; MSA: successors: %bb.3(0x80000000) 1291 ; MSA: J %bb.3, implicit-def $at { 1292 ; MSA: NOP 1293 ; MSA: } 1294 ; MSA: bb.2.if.then: 1295 ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1296 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1297 ; MSA: renamable $v0 = ADDiu $zero, 1 1298 ; MSA: } 1299 ; MSA: bb.3: 1300 ; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1301 ; MSA: renamable $v0 = ADDiu $zero, 0 1302 ; MSA: } 1303 ; PIC-LABEL: name: _Z6bnz_64_vDv2_x 1304 ; PIC: bb.0.entry: 1305 ; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000) 1306 ; PIC: renamable $w0 = LDI_B 0 1307 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1308 ; PIC: renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1309 ; PIC: BZ_V $w0, %bb.3, implicit-def $at { 1310 ; PIC: NOP 1311 ; PIC: } 1312 ; PIC: bb.1.entry: 1313 ; PIC: successors: %bb.2(0x80000000) 1314 ; PIC: $sp_64 = DADDiu $sp_64, -16 1315 ; PIC: SD $ra_64, $sp_64, 0 1316 ; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2 1317 ; PIC: $at_64 = DSLL $at_64, 16 1318 ; PIC: BAL_BR %bb.2, implicit-def $ra { 1319 ; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2 1320 ; PIC: } 1321 ; PIC: bb.2.entry: 1322 ; PIC: successors: %bb.4(0x80000000) 1323 ; PIC: $at_64 = DADDu $ra_64, $at_64 1324 ; PIC: $ra_64 = LD $sp_64, 0 1325 ; PIC: JR64 $at_64 { 1326 ; PIC: $sp_64 = DADDiu $sp_64, 16 1327 ; PIC: } 1328 ; PIC: bb.3.if.then: 1329 ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1330 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1331 ; PIC: renamable $v0 = ADDiu $zero, 1 1332 ; PIC: } 1333 ; PIC: bb.4: 1334 ; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 { 1335 ; PIC: renamable $v0 = ADDiu $zero, 0 1336 ; PIC: } 1337 bb.0.entry: 1338 successors: %bb.1(0x40000000), %bb.2(0x40000000) 1339 liveins: $a0_64, $a1_64 1340 1341 renamable $w0 = LDI_B 0 1342 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a0_64, 0 1343 renamable $w0 = INSERT_D killed renamable $w0, killed renamable $a1_64, 1 1344 BNZ_V killed renamable $w0, %bb.2, implicit-def dead $at 1345 1346 bb.1.if.then: 1347 INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at 1348 renamable $v0 = ADDiu $zero, 1 1349 PseudoReturn64 undef $ra_64, implicit killed $v0 1350 1351 bb.2: 1352 renamable $v0 = ADDiu $zero, 0 1353 PseudoReturn64 undef $ra_64, implicit killed $v0 1354 1355 ... 1356
