1 ; RUN: llc < %s -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s 2 3 ; Test that fexup[rl].w don't crash LLVM during type legalization. 4 5 @g = local_unnamed_addr global <8 x half> <half 0xH5BF8, half 0xH5BF8, half 0xH5BF8, half 0xH5BF8, half 0xH73C0, half 0xH73C0, half 0xH73C0, half 0xH73C0>, align 16 6 @i = local_unnamed_addr global <4 x float> zeroinitializer, align 16 7 @j = local_unnamed_addr global <4 x float> zeroinitializer, align 16 8 9 define i32 @test() local_unnamed_addr { 10 entry: 11 %0 = load <8 x half>, <8 x half>* @g, align 16 12 %1 = tail call <4 x float> @llvm.mips.fexupl.w(<8 x half> %0) 13 store <4 x float> %1, <4 x float>* @i, align 16 14 ; CHECK: ld.h $w[[W0:[0-9]+]], 0(${{[0-9]+}}) 15 ; CHECK: fexupl.w $w[[W1:[0-9]+]], $w[[W0]] 16 ; CHECK: st.w $w[[W1]], 0(${{[0-9]+}}) 17 18 %2 = tail call <4 x float> @llvm.mips.fexupr.w(<8 x half> %0) 19 store <4 x float> %2, <4 x float>* @j, align 16 20 21 ; CHECK: fexupr.w $w[[W2:[0-9]+]], $w[[W0]] 22 ; CHECK: st.w $w[[W2]], 0(${{[0-9]+}}) 23 24 ret i32 0 25 } 26 27 declare <4 x float> @llvm.mips.fexupl.w(<8 x half>) 28 declare <4 x float> @llvm.mips.fexupr.w(<8 x half>) 29
