1 ; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s 2 3 ; Test that the register allocator honours +nooddspreg and does not pick an odd 4 ; single precision subregister of an MSA register. 5 6 @f1 = external global float 7 8 @f2 = external global float 9 10 @v3 = external global <4 x float> 11 12 @d1 = external global double 13 14 define void @test() { 15 ; CHECK-LABEL: test: 16 entry: 17 ; CHECK-NOT: lwc1 $f{{[13579]+}} 18 ; CHECK: lwc1 $f{{[02468]+}} 19 %0 = load float, float * @f1 20 %1 = insertelement <4 x float> undef, float %0, i32 0 21 %2 = insertelement <4 x float> %1, float %0, i32 1 22 %3 = insertelement <4 x float> %2, float %0, i32 2 23 %4 = insertelement <4 x float> %3, float %0, i32 3 24 25 ; CHECK-NOT: lwc1 $f{{[13579]+}} 26 ; CHECK: lwc1 $f{{[02468]+}} 27 %5 = load float, float * @f2 28 %6 = insertelement <4 x float> undef, float %5, i32 0 29 %7 = insertelement <4 x float> %6, float %5, i32 1 30 %8 = insertelement <4 x float> %7, float %5, i32 2 31 %9 = insertelement <4 x float> %8, float %5, i32 3 32 33 %10 = fadd <4 x float> %4, %9 34 store <4 x float> %10, <4 x float> * @v3 35 ret void 36 } 37 38 ; Test that the register allocator hnours +noodspreg and does not pick an odd 39 ; single precision register for a load to perform a conversion to a double. 40 41 define void @test2() { 42 ; CHECK-LABEL: test2: 43 entry: 44 ; CHECK-NOT: lwc1 $f{{[13579]+}} 45 ; CHECK: lwc1 $f{{[02468]+}} 46 %0 = load float, float * @f1 47 %1 = fpext float %0 to double 48 ; CHECK-NOT: lwc1 $f{{[13579]+}} 49 ; CHECK: lwc1 $f{{[02468]+}} 50 %2 = load float, float * @f2 51 %3 = fpext float %2 to double 52 %4 = fadd double %1, %3 53 store double%4, double * @d1 54 ret void 55 } 56
