1 ; RUN: llc -march=mipsel < %s | FileCheck %s 2 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6 3 4 @g1 = external global i32 5 6 ; CHECK-LABEL: seteq0: 7 ; CHECK: sltiu ${{[0-9]+}}, $4, 1 8 ; MMR6: sltiu ${{[0-9]+}}, $4, 1 9 ; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM 10 11 define i32 @seteq0(i32 %a) { 12 entry: 13 %cmp = icmp eq i32 %a, 0 14 %conv = zext i1 %cmp to i32 15 ret i32 %conv 16 } 17 18 ; CHECK-LABEL: setne0: 19 ; CHECK: sltu ${{[0-9]+}}, $zero, $4 20 ; MMR6: sltu ${{[0-9]+}}, $zero, $4 21 ; MMR6: <MCInst #{{[0-9]+}} SLTu_MM 22 23 define i32 @setne0(i32 %a) { 24 entry: 25 %cmp = icmp ne i32 %a, 0 26 %conv = zext i1 %cmp to i32 27 ret i32 %conv 28 } 29 30 ; CHECK-LABEL: slti_beq0: 31 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768 32 ; MMR6: slti $[[R0:[0-9]+]], $4, -32768 33 ; MMR6: <MCInst #{{[0-9]+}} SLTi_MM 34 ; CHECK: beqz $[[R0]] 35 36 define void @slti_beq0(i32 %a) { 37 entry: 38 %cmp = icmp slt i32 %a, -32768 39 br i1 %cmp, label %if.then, label %if.end 40 41 if.then: 42 store i32 %a, i32* @g1, align 4 43 br label %if.end 44 45 if.end: 46 ret void 47 } 48 49 ; CHECK-LABEL: slti_beq1: 50 ; CHECK: slt ${{[0-9]+}} 51 ; MMR6: slt ${{[0-9]+}} 52 ; MMR6: <MCInst #{{[0-9]+}} SLT_MM 53 54 define void @slti_beq1(i32 %a) { 55 entry: 56 %cmp = icmp slt i32 %a, -32769 57 br i1 %cmp, label %if.then, label %if.end 58 59 if.then: 60 store i32 %a, i32* @g1, align 4 61 br label %if.end 62 63 if.end: 64 ret void 65 } 66 67 ; CHECK-LABEL: slti_beq2: 68 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767 69 ; MMR6: slti $[[R0:[0-9]+]], $4, 32767 70 ; MMR6: <MCInst #{{[0-9]+}} SLTi_MM 71 ; CHECK: beqz $[[R0]] 72 73 define void @slti_beq2(i32 %a) { 74 entry: 75 %cmp = icmp slt i32 %a, 32767 76 br i1 %cmp, label %if.then, label %if.end 77 78 if.then: 79 store i32 %a, i32* @g1, align 4 80 br label %if.end 81 82 if.end: 83 ret void 84 } 85 86 ; CHECK-LABEL: slti_beq3: 87 ; CHECK: slt ${{[0-9]+}} 88 ; MMR6: slt ${{[0-9]+}} 89 ; MMR6: <MCInst #{{[0-9]+}} SLT_MM 90 91 define void @slti_beq3(i32 %a) { 92 entry: 93 %cmp = icmp slt i32 %a, 32768 94 br i1 %cmp, label %if.then, label %if.end 95 96 if.then: 97 store i32 %a, i32* @g1, align 4 98 br label %if.end 99 100 if.end: 101 ret void 102 } 103 104 ; CHECK-LABEL: sltiu_beq0: 105 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767 106 ; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767 107 ; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM 108 ; CHECK: beqz $[[R0]] 109 110 define void @sltiu_beq0(i32 %a) { 111 entry: 112 %cmp = icmp ult i32 %a, 32767 113 br i1 %cmp, label %if.then, label %if.end 114 115 if.then: 116 store i32 %a, i32* @g1, align 4 117 br label %if.end 118 119 if.end: 120 ret void 121 } 122 123 ; CHECK-LABEL: sltiu_beq1: 124 ; CHECK: sltu ${{[0-9]+}} 125 ; MMR6: sltu ${{[0-9]+}} 126 ; MMR6: <MCInst #{{[0-9]+}} SLTu_MM 127 128 define void @sltiu_beq1(i32 %a) { 129 entry: 130 %cmp = icmp ult i32 %a, 32768 131 br i1 %cmp, label %if.then, label %if.end 132 133 if.then: 134 store i32 %a, i32* @g1, align 4 135 br label %if.end 136 137 if.end: 138 ret void 139 } 140 141 ; CHECK-LABEL: sltiu_beq2: 142 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768 143 ; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768 144 ; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM 145 ; CHECK: beqz $[[R0]] 146 147 define void @sltiu_beq2(i32 %a) { 148 entry: 149 %cmp = icmp ult i32 %a, -32768 150 br i1 %cmp, label %if.then, label %if.end 151 152 if.then: 153 store i32 %a, i32* @g1, align 4 154 br label %if.end 155 156 if.end: 157 ret void 158 } 159 160 ; CHECK-LABEL: sltiu_beq3: 161 ; CHECK: sltu ${{[0-9]+}} 162 ; MMR6: sltu ${{[0-9]+}} 163 ; MMR6: <MCInst #{{[0-9]+}} SLTu_MM 164 165 define void @sltiu_beq3(i32 %a) { 166 entry: 167 %cmp = icmp ult i32 %a, -32769 168 br i1 %cmp, label %if.then, label %if.end 169 170 if.then: 171 store i32 %a, i32* @g1, align 4 172 br label %if.end 173 174 if.end: 175 ret void 176 } 177
