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      1 # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
      2 # RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
      3 
      4 # Test that MIPS unaligned load/store instructions can be mapped to their
      5 # corresponding microMIPS instructions.
      6 --- |
      7   define void @g(i32* %a, i32* %b) {
      8   entry:
      9     %0 = load i32, i32* %a, align 1
     10     store i32 %0, i32* %b, align 1
     11     ret void
     12   }
     13 
     14   define void @g2(i32* %a, i32* %b) {
     15   entry:
     16     %0 = load i32, i32* %a, align 1
     17     store i32 %0, i32* %b, align 1
     18     ret void
     19   }
     20 ...
     21 ---
     22 name:            g
     23 alignment:       2
     24 exposesReturnsTwice: false
     25 legalized:       false
     26 regBankSelected: false
     27 selected:        false
     28 failedISel:      false
     29 tracksRegLiveness: true
     30 liveins:
     31   - { reg: '$a0', virtual-reg: '%0' }
     32   - { reg: '$a1', virtual-reg: '%1' }
     33 frameInfo:
     34   isFrameAddressTaken: false
     35   isReturnAddressTaken: false
     36   hasStackMap:     false
     37   hasPatchPoint:   false
     38   stackSize:       0
     39   offsetAdjustment: 0
     40   maxAlignment:    1
     41   adjustsStack:    false
     42   hasCalls:        false
     43   stackProtector:  ''
     44   maxCallFrameSize: 4294967295
     45   hasOpaqueSPAdjustment: false
     46   hasVAStart:      false
     47   hasMustTailInVarArgFunc: false
     48   savePoint:       ''
     49   restorePoint:    ''
     50 fixedStack:
     51 stack:
     52 constants:
     53 body:             |
     54   bb.0.entry:
     55     liveins: $a0, $a1
     56 
     57     %1:gpr32 = COPY $a1
     58     %0:gpr32 = COPY $a0
     59     %3:gpr32 = IMPLICIT_DEF
     60     %2:gpr32 = LWL %0, 0, %3 :: (load 4 from %ir.a, align 1)
     61     %4:gpr32 = LWR %0, 3, %2 :: (load 4 from %ir.a, align 1)
     62     SWL %4, %1, 0 :: (store 4 into %ir.b, align 1)
     63     SWR %4, %1, 3 :: (store 4 into %ir.b, align 1)
     64     RetRA
     65 
     66 ...
     67 ---
     68 name:            g2
     69 alignment:       2
     70 exposesReturnsTwice: false
     71 legalized:       false
     72 regBankSelected: false
     73 selected:        false
     74 failedISel:      false
     75 tracksRegLiveness: true
     76 liveins:
     77   - { reg: '$a0', virtual-reg: '%0' }
     78   - { reg: '$a1', virtual-reg: '%1' }
     79 frameInfo:
     80   isFrameAddressTaken: false
     81   isReturnAddressTaken: false
     82   hasStackMap:     false
     83   hasPatchPoint:   false
     84   stackSize:       0
     85   offsetAdjustment: 0
     86   maxAlignment:    1
     87   adjustsStack:    false
     88   hasCalls:        false
     89   stackProtector:  ''
     90   maxCallFrameSize: 4294967295
     91   hasOpaqueSPAdjustment: false
     92   hasVAStart:      false
     93   hasMustTailInVarArgFunc: false
     94   savePoint:       ''
     95   restorePoint:    ''
     96 fixedStack:
     97 stack:
     98 constants:
     99 body:             |
    100   bb.0.entry:
    101     liveins: $a0, $a1
    102 
    103     %1:gpr32 = COPY $a1
    104     %0:gpr32 = COPY $a0
    105     %3:gpr32 = IMPLICIT_DEF
    106     %2:gpr32 = LWLE %0, 0, %3 :: (load 4 from %ir.a, align 1)
    107     %4:gpr32 = LWRE %0, 3, %2 :: (load 4 from %ir.a, align 1)
    108     SWLE %4, %1, 0 :: (store 4 into %ir.b, align 1)
    109     SWRE %4, %1, 3 :: (store 4 into %ir.b, align 1)
    110     RetRA
    111 
    112 ...
    113 
    114 # CHECK-LABEL: g:
    115 # CHECK:  0: 60 24 00 00   lwl $1, 0($4)
    116 # CHECK:  4: 60 24 10 03   lwr $1, 3($4)
    117 # CHECK:  8: 60 25 80 00   swl $1, 0($5)
    118 # CHECK:  c: 60 25 90 03   swr $1, 3($5)
    119 
    120 # CHECK-LABEL: g2:
    121 # CHECK: 14: 60 24 64 00   lwle  $1, 0($4)
    122 # CHECK: 18: 60 24 66 03   lwre  $1, 3($4)
    123 # CHECK: 1c: 60 25 a0 00   swle  $1, 0($5)
    124 # CHECK: 20: 60 25 a2 03   swre  $1, 3($5)
    125