1 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2 ; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MIPS 3 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MICROMIPS 4 5 ; Test that the correct ISA version of the unaligned memory operations is 6 ; selected up front. 7 8 define void @g2(i32* %a, i32* %b) { 9 ; MIPS-LABEL: name: g2 10 ; MIPS: bb.0.entry: 11 ; MIPS: liveins: $a0, $a1 12 ; MIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a1 13 ; MIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0 14 ; MIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF 15 ; MIPS: [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1) 16 ; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load 4 from %ir.a, align 1) 17 ; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store 4 into %ir.b, align 1) 18 ; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store 4 into %ir.b, align 1) 19 ; MIPS: RetRA 20 ; MICROMIPS-LABEL: name: g2 21 ; MICROMIPS: bb.0.entry: 22 ; MICROMIPS: liveins: $a0, $a1 23 ; MICROMIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a1 24 ; MICROMIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0 25 ; MICROMIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF 26 ; MICROMIPS: [[LWL_MM:%[0-9]+]]:gpr32 = LWL_MM [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1) 27 ; MICROMIPS: [[LWR_MM:%[0-9]+]]:gpr32 = LWR_MM [[COPY1]], 3, [[LWL_MM]] :: (load 4 from %ir.a, align 1) 28 ; MICROMIPS: SWL_MM [[LWR_MM]], [[COPY]], 0 :: (store 4 into %ir.b, align 1) 29 ; MICROMIPS: SWR_MM [[LWR_MM]], [[COPY]], 3 :: (store 4 into %ir.b, align 1) 30 ; MICROMIPS: RetRA 31 entry: 32 %0 = load i32, i32* %a, align 1 33 store i32 %0, i32* %b, align 1 34 ret void 35 } 36
