1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; Make sure that a negative value for the compare-and-swap is zero extended 3 ; from i8/i16 to i32 since it will be compared for equality. 4 ; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s 5 ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-P7 6 7 @str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00" 8 @str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00" 9 @str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00" 10 11 define signext i32 @main() { 12 ; CHECK-LABEL: main: 13 ; CHECK: li 3, -32477 14 ; CHECK: li 6, 234 15 ; CHECK: sth 3, 46(1) 16 ; CHECK: lis 3, 0 17 ; CHECK: ori 4, 3, 33059 18 ; CHECK: sync 19 ; CHECK: .LBB0_1: # %L.entry 20 ; CHECK: lharx 3, 0, 5 21 ; CHECK: cmpw 4, 3 22 ; CHECK: bne 0, .LBB0_3 23 ; CHECK: sthcx. 6, 0, 5 24 ; CHECK: bne 0, .LBB0_1 25 ; CHECK: b .LBB0_4 26 ; CHECK: .LBB0_3: # %L.entry 27 ; CHECK: sthcx. 3, 0, 5 28 ; CHECK: .LBB0_4: # %L.entry 29 ; CHECK: cmplwi 3, 33059 30 ; CHECK: lwsync 31 ; CHECK: lhz 3, 46(1) 32 ; CHECK: cmplwi 3, 234 33 ; 34 ; CHECK-P7-LABEL: main: 35 ; CHECK-P7: li 3, -32477 36 ; CHECK-P7: lis 4, 0 37 ; CHECK-P7: li 7, 0 38 ; CHECK-P7: li 5, 234 39 ; CHECK-P7: sth 3, 46(1) 40 ; CHECK-P7: ori 4, 4, 33059 41 ; CHECK-P7: rlwinm 3, 6, 3, 27, 27 42 ; CHECK-P7: ori 7, 7, 65535 43 ; CHECK-P7: sync 44 ; CHECK-P7: slw 8, 5, 3 45 ; CHECK-P7: slw 9, 4, 3 46 ; CHECK-P7: rldicr 4, 6, 0, 61 47 ; CHECK-P7: slw 5, 7, 3 48 ; CHECK-P7: and 7, 8, 5 49 ; CHECK-P7: and 8, 9, 5 50 ; CHECK-P7: .LBB0_1: # %L.entry 51 ; CHECK-P7: lwarx 9, 0, 4 52 ; CHECK-P7: and 6, 9, 5 53 ; CHECK-P7: cmpw 0, 6, 8 54 ; CHECK-P7: bne 0, .LBB0_3 55 ; CHECK-P7: andc 9, 9, 5 56 ; CHECK-P7: or 9, 9, 7 57 ; CHECK-P7: stwcx. 9, 0, 4 58 ; CHECK-P7: bne 0, .LBB0_1 59 ; CHECK-P7: b .LBB0_4 60 ; CHECK-P7: .LBB0_3: # %L.entry 61 ; CHECK-P7: stwcx. 9, 0, 4 62 ; CHECK-P7: .LBB0_4: # %L.entry 63 ; CHECK-P7: srw 3, 6, 3 64 ; CHECK-P7: lwsync 65 ; CHECK-P7: cmplwi 3, 33059 66 ; CHECK-P7: lhz 3, 46(1) 67 ; CHECK-P7: cmplwi 3, 234 68 L.entry: 69 %value.addr = alloca i16, align 2 70 store i16 -32477, i16* %value.addr, align 2 71 %0 = cmpxchg i16* %value.addr, i16 -32477, i16 234 seq_cst seq_cst 72 %1 = extractvalue { i16, i1 } %0, 1 73 br i1 %1, label %L.B0000, label %L.B0003 74 75 L.B0003: ; preds = %L.entry 76 %puts = call i32 @puts(i8* getelementptr inbounds ([46 x i8], [46 x i8]* @str, i64 0, i64 0)) 77 ret i32 1 78 79 L.B0000: ; preds = %L.entry 80 %2 = load i16, i16* %value.addr, align 2 81 %3 = icmp eq i16 %2, 234 82 br i1 %3, label %L.B0001, label %L.B0005 83 84 L.B0005: ; preds = %L.B0000 85 %puts1 = call i32 @puts(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @str.1, i64 0, i64 0)) 86 ret i32 1 87 88 L.B0001: ; preds = %L.B0000 89 %puts2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @str.2, i64 0, i64 0)) 90 ret i32 0 91 } 92 93 ; Function Attrs: nounwind 94 declare i32 @puts(i8* nocapture readonly) #0 95
