1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE 3 4 define i8 @test0(i8* %ptr) { 5 ; PPC64LE-LABEL: test0: 6 ; PPC64LE: # %bb.0: 7 ; PPC64LE-NEXT: lbz 3, 0(3) 8 ; PPC64LE-NEXT: blr 9 %val = load atomic i8, i8* %ptr unordered, align 1 10 ret i8 %val 11 } 12 13 define i8 @test1(i8* %ptr) { 14 ; PPC64LE-LABEL: test1: 15 ; PPC64LE: # %bb.0: 16 ; PPC64LE-NEXT: lbz 3, 0(3) 17 ; PPC64LE-NEXT: blr 18 %val = load atomic i8, i8* %ptr monotonic, align 1 19 ret i8 %val 20 } 21 22 define i8 @test2(i8* %ptr) { 23 ; PPC64LE-LABEL: test2: 24 ; PPC64LE: # %bb.0: 25 ; PPC64LE-NEXT: lbz 3, 0(3) 26 ; PPC64LE-NEXT: cmpd 7, 3, 3 27 ; PPC64LE-NEXT: bne- 7, .+4 28 ; PPC64LE-NEXT: isync 29 ; PPC64LE-NEXT: blr 30 %val = load atomic i8, i8* %ptr acquire, align 1 31 ret i8 %val 32 } 33 34 define i8 @test3(i8* %ptr) { 35 ; PPC64LE-LABEL: test3: 36 ; PPC64LE: # %bb.0: 37 ; PPC64LE-NEXT: sync 38 ; PPC64LE-NEXT: lbz 3, 0(3) 39 ; PPC64LE-NEXT: cmpd 7, 3, 3 40 ; PPC64LE-NEXT: bne- 7, .+4 41 ; PPC64LE-NEXT: isync 42 ; PPC64LE-NEXT: blr 43 %val = load atomic i8, i8* %ptr seq_cst, align 1 44 ret i8 %val 45 } 46 47 define i16 @test4(i16* %ptr) { 48 ; PPC64LE-LABEL: test4: 49 ; PPC64LE: # %bb.0: 50 ; PPC64LE-NEXT: lhz 3, 0(3) 51 ; PPC64LE-NEXT: blr 52 %val = load atomic i16, i16* %ptr unordered, align 2 53 ret i16 %val 54 } 55 56 define i16 @test5(i16* %ptr) { 57 ; PPC64LE-LABEL: test5: 58 ; PPC64LE: # %bb.0: 59 ; PPC64LE-NEXT: lhz 3, 0(3) 60 ; PPC64LE-NEXT: blr 61 %val = load atomic i16, i16* %ptr monotonic, align 2 62 ret i16 %val 63 } 64 65 define i16 @test6(i16* %ptr) { 66 ; PPC64LE-LABEL: test6: 67 ; PPC64LE: # %bb.0: 68 ; PPC64LE-NEXT: lhz 3, 0(3) 69 ; PPC64LE-NEXT: cmpd 7, 3, 3 70 ; PPC64LE-NEXT: bne- 7, .+4 71 ; PPC64LE-NEXT: isync 72 ; PPC64LE-NEXT: blr 73 %val = load atomic i16, i16* %ptr acquire, align 2 74 ret i16 %val 75 } 76 77 define i16 @test7(i16* %ptr) { 78 ; PPC64LE-LABEL: test7: 79 ; PPC64LE: # %bb.0: 80 ; PPC64LE-NEXT: sync 81 ; PPC64LE-NEXT: lhz 3, 0(3) 82 ; PPC64LE-NEXT: cmpd 7, 3, 3 83 ; PPC64LE-NEXT: bne- 7, .+4 84 ; PPC64LE-NEXT: isync 85 ; PPC64LE-NEXT: blr 86 %val = load atomic i16, i16* %ptr seq_cst, align 2 87 ret i16 %val 88 } 89 90 define i32 @test8(i32* %ptr) { 91 ; PPC64LE-LABEL: test8: 92 ; PPC64LE: # %bb.0: 93 ; PPC64LE-NEXT: lwz 3, 0(3) 94 ; PPC64LE-NEXT: blr 95 %val = load atomic i32, i32* %ptr unordered, align 4 96 ret i32 %val 97 } 98 99 define i32 @test9(i32* %ptr) { 100 ; PPC64LE-LABEL: test9: 101 ; PPC64LE: # %bb.0: 102 ; PPC64LE-NEXT: lwz 3, 0(3) 103 ; PPC64LE-NEXT: blr 104 %val = load atomic i32, i32* %ptr monotonic, align 4 105 ret i32 %val 106 } 107 108 define i32 @test10(i32* %ptr) { 109 ; PPC64LE-LABEL: test10: 110 ; PPC64LE: # %bb.0: 111 ; PPC64LE-NEXT: lwz 3, 0(3) 112 ; PPC64LE-NEXT: cmpd 7, 3, 3 113 ; PPC64LE-NEXT: bne- 7, .+4 114 ; PPC64LE-NEXT: isync 115 ; PPC64LE-NEXT: blr 116 %val = load atomic i32, i32* %ptr acquire, align 4 117 ret i32 %val 118 } 119 120 define i32 @test11(i32* %ptr) { 121 ; PPC64LE-LABEL: test11: 122 ; PPC64LE: # %bb.0: 123 ; PPC64LE-NEXT: sync 124 ; PPC64LE-NEXT: lwz 3, 0(3) 125 ; PPC64LE-NEXT: cmpd 7, 3, 3 126 ; PPC64LE-NEXT: bne- 7, .+4 127 ; PPC64LE-NEXT: isync 128 ; PPC64LE-NEXT: blr 129 %val = load atomic i32, i32* %ptr seq_cst, align 4 130 ret i32 %val 131 } 132 133 define i64 @test12(i64* %ptr) { 134 ; PPC64LE-LABEL: test12: 135 ; PPC64LE: # %bb.0: 136 ; PPC64LE-NEXT: ld 3, 0(3) 137 ; PPC64LE-NEXT: blr 138 %val = load atomic i64, i64* %ptr unordered, align 8 139 ret i64 %val 140 } 141 142 define i64 @test13(i64* %ptr) { 143 ; PPC64LE-LABEL: test13: 144 ; PPC64LE: # %bb.0: 145 ; PPC64LE-NEXT: ld 3, 0(3) 146 ; PPC64LE-NEXT: blr 147 %val = load atomic i64, i64* %ptr monotonic, align 8 148 ret i64 %val 149 } 150 151 define i64 @test14(i64* %ptr) { 152 ; PPC64LE-LABEL: test14: 153 ; PPC64LE: # %bb.0: 154 ; PPC64LE-NEXT: ld 3, 0(3) 155 ; PPC64LE-NEXT: cmpd 7, 3, 3 156 ; PPC64LE-NEXT: bne- 7, .+4 157 ; PPC64LE-NEXT: isync 158 ; PPC64LE-NEXT: blr 159 %val = load atomic i64, i64* %ptr acquire, align 8 160 ret i64 %val 161 } 162 163 define i64 @test15(i64* %ptr) { 164 ; PPC64LE-LABEL: test15: 165 ; PPC64LE: # %bb.0: 166 ; PPC64LE-NEXT: sync 167 ; PPC64LE-NEXT: ld 3, 0(3) 168 ; PPC64LE-NEXT: cmpd 7, 3, 3 169 ; PPC64LE-NEXT: bne- 7, .+4 170 ; PPC64LE-NEXT: isync 171 ; PPC64LE-NEXT: blr 172 %val = load atomic i64, i64* %ptr seq_cst, align 8 173 ret i64 %val 174 } 175 176 define void @test16(i8* %ptr, i8 %val) { 177 ; PPC64LE-LABEL: test16: 178 ; PPC64LE: # %bb.0: 179 ; PPC64LE-NEXT: stb 4, 0(3) 180 ; PPC64LE-NEXT: blr 181 store atomic i8 %val, i8* %ptr unordered, align 1 182 ret void 183 } 184 185 define void @test17(i8* %ptr, i8 %val) { 186 ; PPC64LE-LABEL: test17: 187 ; PPC64LE: # %bb.0: 188 ; PPC64LE-NEXT: stb 4, 0(3) 189 ; PPC64LE-NEXT: blr 190 store atomic i8 %val, i8* %ptr monotonic, align 1 191 ret void 192 } 193 194 define void @test18(i8* %ptr, i8 %val) { 195 ; PPC64LE-LABEL: test18: 196 ; PPC64LE: # %bb.0: 197 ; PPC64LE-NEXT: lwsync 198 ; PPC64LE-NEXT: stb 4, 0(3) 199 ; PPC64LE-NEXT: blr 200 store atomic i8 %val, i8* %ptr release, align 1 201 ret void 202 } 203 204 define void @test19(i8* %ptr, i8 %val) { 205 ; PPC64LE-LABEL: test19: 206 ; PPC64LE: # %bb.0: 207 ; PPC64LE-NEXT: sync 208 ; PPC64LE-NEXT: stb 4, 0(3) 209 ; PPC64LE-NEXT: blr 210 store atomic i8 %val, i8* %ptr seq_cst, align 1 211 ret void 212 } 213 214 define void @test20(i16* %ptr, i16 %val) { 215 ; PPC64LE-LABEL: test20: 216 ; PPC64LE: # %bb.0: 217 ; PPC64LE-NEXT: sth 4, 0(3) 218 ; PPC64LE-NEXT: blr 219 store atomic i16 %val, i16* %ptr unordered, align 2 220 ret void 221 } 222 223 define void @test21(i16* %ptr, i16 %val) { 224 ; PPC64LE-LABEL: test21: 225 ; PPC64LE: # %bb.0: 226 ; PPC64LE-NEXT: sth 4, 0(3) 227 ; PPC64LE-NEXT: blr 228 store atomic i16 %val, i16* %ptr monotonic, align 2 229 ret void 230 } 231 232 define void @test22(i16* %ptr, i16 %val) { 233 ; PPC64LE-LABEL: test22: 234 ; PPC64LE: # %bb.0: 235 ; PPC64LE-NEXT: lwsync 236 ; PPC64LE-NEXT: sth 4, 0(3) 237 ; PPC64LE-NEXT: blr 238 store atomic i16 %val, i16* %ptr release, align 2 239 ret void 240 } 241 242 define void @test23(i16* %ptr, i16 %val) { 243 ; PPC64LE-LABEL: test23: 244 ; PPC64LE: # %bb.0: 245 ; PPC64LE-NEXT: sync 246 ; PPC64LE-NEXT: sth 4, 0(3) 247 ; PPC64LE-NEXT: blr 248 store atomic i16 %val, i16* %ptr seq_cst, align 2 249 ret void 250 } 251 252 define void @test24(i32* %ptr, i32 %val) { 253 ; PPC64LE-LABEL: test24: 254 ; PPC64LE: # %bb.0: 255 ; PPC64LE-NEXT: stw 4, 0(3) 256 ; PPC64LE-NEXT: blr 257 store atomic i32 %val, i32* %ptr unordered, align 4 258 ret void 259 } 260 261 define void @test25(i32* %ptr, i32 %val) { 262 ; PPC64LE-LABEL: test25: 263 ; PPC64LE: # %bb.0: 264 ; PPC64LE-NEXT: stw 4, 0(3) 265 ; PPC64LE-NEXT: blr 266 store atomic i32 %val, i32* %ptr monotonic, align 4 267 ret void 268 } 269 270 define void @test26(i32* %ptr, i32 %val) { 271 ; PPC64LE-LABEL: test26: 272 ; PPC64LE: # %bb.0: 273 ; PPC64LE-NEXT: lwsync 274 ; PPC64LE-NEXT: stw 4, 0(3) 275 ; PPC64LE-NEXT: blr 276 store atomic i32 %val, i32* %ptr release, align 4 277 ret void 278 } 279 280 define void @test27(i32* %ptr, i32 %val) { 281 ; PPC64LE-LABEL: test27: 282 ; PPC64LE: # %bb.0: 283 ; PPC64LE-NEXT: sync 284 ; PPC64LE-NEXT: stw 4, 0(3) 285 ; PPC64LE-NEXT: blr 286 store atomic i32 %val, i32* %ptr seq_cst, align 4 287 ret void 288 } 289 290 define void @test28(i64* %ptr, i64 %val) { 291 ; PPC64LE-LABEL: test28: 292 ; PPC64LE: # %bb.0: 293 ; PPC64LE-NEXT: std 4, 0(3) 294 ; PPC64LE-NEXT: blr 295 store atomic i64 %val, i64* %ptr unordered, align 8 296 ret void 297 } 298 299 define void @test29(i64* %ptr, i64 %val) { 300 ; PPC64LE-LABEL: test29: 301 ; PPC64LE: # %bb.0: 302 ; PPC64LE-NEXT: std 4, 0(3) 303 ; PPC64LE-NEXT: blr 304 store atomic i64 %val, i64* %ptr monotonic, align 8 305 ret void 306 } 307 308 define void @test30(i64* %ptr, i64 %val) { 309 ; PPC64LE-LABEL: test30: 310 ; PPC64LE: # %bb.0: 311 ; PPC64LE-NEXT: lwsync 312 ; PPC64LE-NEXT: std 4, 0(3) 313 ; PPC64LE-NEXT: blr 314 store atomic i64 %val, i64* %ptr release, align 8 315 ret void 316 } 317 318 define void @test31(i64* %ptr, i64 %val) { 319 ; PPC64LE-LABEL: test31: 320 ; PPC64LE: # %bb.0: 321 ; PPC64LE-NEXT: sync 322 ; PPC64LE-NEXT: std 4, 0(3) 323 ; PPC64LE-NEXT: blr 324 store atomic i64 %val, i64* %ptr seq_cst, align 8 325 ret void 326 } 327 328 define void @test32() { 329 ; PPC64LE-LABEL: test32: 330 ; PPC64LE: # %bb.0: 331 ; PPC64LE-NEXT: lwsync 332 ; PPC64LE-NEXT: blr 333 fence acquire 334 ret void 335 } 336 337 define void @test33() { 338 ; PPC64LE-LABEL: test33: 339 ; PPC64LE: # %bb.0: 340 ; PPC64LE-NEXT: lwsync 341 ; PPC64LE-NEXT: blr 342 fence release 343 ret void 344 } 345 346 define void @test34() { 347 ; PPC64LE-LABEL: test34: 348 ; PPC64LE: # %bb.0: 349 ; PPC64LE-NEXT: lwsync 350 ; PPC64LE-NEXT: blr 351 fence acq_rel 352 ret void 353 } 354 355 define void @test35() { 356 ; PPC64LE-LABEL: test35: 357 ; PPC64LE: # %bb.0: 358 ; PPC64LE-NEXT: sync 359 ; PPC64LE-NEXT: blr 360 fence seq_cst 361 ret void 362 } 363 364 define void @test36() { 365 ; PPC64LE-LABEL: test36: 366 ; PPC64LE: # %bb.0: 367 ; PPC64LE-NEXT: lwsync 368 ; PPC64LE-NEXT: blr 369 fence syncscope("singlethread") acquire 370 ret void 371 } 372 373 define void @test37() { 374 ; PPC64LE-LABEL: test37: 375 ; PPC64LE: # %bb.0: 376 ; PPC64LE-NEXT: lwsync 377 ; PPC64LE-NEXT: blr 378 fence syncscope("singlethread") release 379 ret void 380 } 381 382 define void @test38() { 383 ; PPC64LE-LABEL: test38: 384 ; PPC64LE: # %bb.0: 385 ; PPC64LE-NEXT: lwsync 386 ; PPC64LE-NEXT: blr 387 fence syncscope("singlethread") acq_rel 388 ret void 389 } 390 391 define void @test39() { 392 ; PPC64LE-LABEL: test39: 393 ; PPC64LE: # %bb.0: 394 ; PPC64LE-NEXT: sync 395 ; PPC64LE-NEXT: blr 396 fence syncscope("singlethread") seq_cst 397 ret void 398 } 399 400 define void @test40(i8* %ptr, i8 %cmp, i8 %val) { 401 ; PPC64LE-LABEL: test40: 402 ; PPC64LE: # %bb.0: 403 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 404 ; PPC64LE-NEXT: b .LBB40_2 405 ; PPC64LE-NEXT: .p2align 5 406 ; PPC64LE-NEXT: .LBB40_1: 407 ; PPC64LE-NEXT: stbcx. 5, 0, 3 408 ; PPC64LE-NEXT: beqlr 0 409 ; PPC64LE-NEXT: .LBB40_2: 410 ; PPC64LE-NEXT: lbarx 6, 0, 3 411 ; PPC64LE-NEXT: cmpw 4, 6 412 ; PPC64LE-NEXT: beq 0, .LBB40_1 413 ; PPC64LE-NEXT: # %bb.3: 414 ; PPC64LE-NEXT: stbcx. 6, 0, 3 415 ; PPC64LE-NEXT: blr 416 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic 417 ret void 418 } 419 420 define void @test41(i8* %ptr, i8 %cmp, i8 %val) { 421 ; PPC64LE-LABEL: test41: 422 ; PPC64LE: # %bb.0: 423 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 424 ; PPC64LE-NEXT: .LBB41_1: 425 ; PPC64LE-NEXT: lbarx 6, 0, 3 426 ; PPC64LE-NEXT: cmpw 4, 6 427 ; PPC64LE-NEXT: bne 0, .LBB41_4 428 ; PPC64LE-NEXT: # %bb.2: 429 ; PPC64LE-NEXT: stbcx. 5, 0, 3 430 ; PPC64LE-NEXT: bne 0, .LBB41_1 431 ; PPC64LE-NEXT: # %bb.3: 432 ; PPC64LE-NEXT: lwsync 433 ; PPC64LE-NEXT: blr 434 ; PPC64LE-NEXT: .LBB41_4: 435 ; PPC64LE-NEXT: stbcx. 6, 0, 3 436 ; PPC64LE-NEXT: lwsync 437 ; PPC64LE-NEXT: blr 438 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic 439 ret void 440 } 441 442 define void @test42(i8* %ptr, i8 %cmp, i8 %val) { 443 ; PPC64LE-LABEL: test42: 444 ; PPC64LE: # %bb.0: 445 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 446 ; PPC64LE-NEXT: .LBB42_1: 447 ; PPC64LE-NEXT: lbarx 6, 0, 3 448 ; PPC64LE-NEXT: cmpw 4, 6 449 ; PPC64LE-NEXT: bne 0, .LBB42_4 450 ; PPC64LE-NEXT: # %bb.2: 451 ; PPC64LE-NEXT: stbcx. 5, 0, 3 452 ; PPC64LE-NEXT: bne 0, .LBB42_1 453 ; PPC64LE-NEXT: # %bb.3: 454 ; PPC64LE-NEXT: lwsync 455 ; PPC64LE-NEXT: blr 456 ; PPC64LE-NEXT: .LBB42_4: 457 ; PPC64LE-NEXT: stbcx. 6, 0, 3 458 ; PPC64LE-NEXT: lwsync 459 ; PPC64LE-NEXT: blr 460 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire 461 ret void 462 } 463 464 define void @test43(i8* %ptr, i8 %cmp, i8 %val) { 465 ; PPC64LE-LABEL: test43: 466 ; PPC64LE: # %bb.0: 467 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 468 ; PPC64LE-NEXT: lwsync 469 ; PPC64LE-NEXT: b .LBB43_2 470 ; PPC64LE-NEXT: .p2align 5 471 ; PPC64LE-NEXT: .LBB43_1: 472 ; PPC64LE-NEXT: stbcx. 5, 0, 3 473 ; PPC64LE-NEXT: beqlr 0 474 ; PPC64LE-NEXT: .LBB43_2: 475 ; PPC64LE-NEXT: lbarx 6, 0, 3 476 ; PPC64LE-NEXT: cmpw 4, 6 477 ; PPC64LE-NEXT: beq 0, .LBB43_1 478 ; PPC64LE-NEXT: # %bb.3: 479 ; PPC64LE-NEXT: stbcx. 6, 0, 3 480 ; PPC64LE-NEXT: blr 481 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic 482 ret void 483 } 484 485 define void @test44(i8* %ptr, i8 %cmp, i8 %val) { 486 ; PPC64LE-LABEL: test44: 487 ; PPC64LE: # %bb.0: 488 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 489 ; PPC64LE-NEXT: lwsync 490 ; PPC64LE-NEXT: b .LBB44_2 491 ; PPC64LE-NEXT: .p2align 5 492 ; PPC64LE-NEXT: .LBB44_1: 493 ; PPC64LE-NEXT: stbcx. 5, 0, 3 494 ; PPC64LE-NEXT: beqlr 0 495 ; PPC64LE-NEXT: .LBB44_2: 496 ; PPC64LE-NEXT: lbarx 6, 0, 3 497 ; PPC64LE-NEXT: cmpw 4, 6 498 ; PPC64LE-NEXT: beq 0, .LBB44_1 499 ; PPC64LE-NEXT: # %bb.3: 500 ; PPC64LE-NEXT: stbcx. 6, 0, 3 501 ; PPC64LE-NEXT: blr 502 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire 503 ret void 504 } 505 506 define void @test45(i8* %ptr, i8 %cmp, i8 %val) { 507 ; PPC64LE-LABEL: test45: 508 ; PPC64LE: # %bb.0: 509 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 510 ; PPC64LE-NEXT: lwsync 511 ; PPC64LE-NEXT: .LBB45_1: 512 ; PPC64LE-NEXT: lbarx 6, 0, 3 513 ; PPC64LE-NEXT: cmpw 4, 6 514 ; PPC64LE-NEXT: bne 0, .LBB45_4 515 ; PPC64LE-NEXT: # %bb.2: 516 ; PPC64LE-NEXT: stbcx. 5, 0, 3 517 ; PPC64LE-NEXT: bne 0, .LBB45_1 518 ; PPC64LE-NEXT: # %bb.3: 519 ; PPC64LE-NEXT: lwsync 520 ; PPC64LE-NEXT: blr 521 ; PPC64LE-NEXT: .LBB45_4: 522 ; PPC64LE-NEXT: stbcx. 6, 0, 3 523 ; PPC64LE-NEXT: lwsync 524 ; PPC64LE-NEXT: blr 525 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic 526 ret void 527 } 528 529 define void @test46(i8* %ptr, i8 %cmp, i8 %val) { 530 ; PPC64LE-LABEL: test46: 531 ; PPC64LE: # %bb.0: 532 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 533 ; PPC64LE-NEXT: lwsync 534 ; PPC64LE-NEXT: .LBB46_1: 535 ; PPC64LE-NEXT: lbarx 6, 0, 3 536 ; PPC64LE-NEXT: cmpw 4, 6 537 ; PPC64LE-NEXT: bne 0, .LBB46_4 538 ; PPC64LE-NEXT: # %bb.2: 539 ; PPC64LE-NEXT: stbcx. 5, 0, 3 540 ; PPC64LE-NEXT: bne 0, .LBB46_1 541 ; PPC64LE-NEXT: # %bb.3: 542 ; PPC64LE-NEXT: lwsync 543 ; PPC64LE-NEXT: blr 544 ; PPC64LE-NEXT: .LBB46_4: 545 ; PPC64LE-NEXT: stbcx. 6, 0, 3 546 ; PPC64LE-NEXT: lwsync 547 ; PPC64LE-NEXT: blr 548 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire 549 ret void 550 } 551 552 define void @test47(i8* %ptr, i8 %cmp, i8 %val) { 553 ; PPC64LE-LABEL: test47: 554 ; PPC64LE: # %bb.0: 555 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 556 ; PPC64LE-NEXT: sync 557 ; PPC64LE-NEXT: .LBB47_1: 558 ; PPC64LE-NEXT: lbarx 6, 0, 3 559 ; PPC64LE-NEXT: cmpw 4, 6 560 ; PPC64LE-NEXT: bne 0, .LBB47_4 561 ; PPC64LE-NEXT: # %bb.2: 562 ; PPC64LE-NEXT: stbcx. 5, 0, 3 563 ; PPC64LE-NEXT: bne 0, .LBB47_1 564 ; PPC64LE-NEXT: # %bb.3: 565 ; PPC64LE-NEXT: lwsync 566 ; PPC64LE-NEXT: blr 567 ; PPC64LE-NEXT: .LBB47_4: 568 ; PPC64LE-NEXT: stbcx. 6, 0, 3 569 ; PPC64LE-NEXT: lwsync 570 ; PPC64LE-NEXT: blr 571 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic 572 ret void 573 } 574 575 define void @test48(i8* %ptr, i8 %cmp, i8 %val) { 576 ; PPC64LE-LABEL: test48: 577 ; PPC64LE: # %bb.0: 578 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 579 ; PPC64LE-NEXT: sync 580 ; PPC64LE-NEXT: .LBB48_1: 581 ; PPC64LE-NEXT: lbarx 6, 0, 3 582 ; PPC64LE-NEXT: cmpw 4, 6 583 ; PPC64LE-NEXT: bne 0, .LBB48_4 584 ; PPC64LE-NEXT: # %bb.2: 585 ; PPC64LE-NEXT: stbcx. 5, 0, 3 586 ; PPC64LE-NEXT: bne 0, .LBB48_1 587 ; PPC64LE-NEXT: # %bb.3: 588 ; PPC64LE-NEXT: lwsync 589 ; PPC64LE-NEXT: blr 590 ; PPC64LE-NEXT: .LBB48_4: 591 ; PPC64LE-NEXT: stbcx. 6, 0, 3 592 ; PPC64LE-NEXT: lwsync 593 ; PPC64LE-NEXT: blr 594 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire 595 ret void 596 } 597 598 define void @test49(i8* %ptr, i8 %cmp, i8 %val) { 599 ; PPC64LE-LABEL: test49: 600 ; PPC64LE: # %bb.0: 601 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 602 ; PPC64LE-NEXT: sync 603 ; PPC64LE-NEXT: .LBB49_1: 604 ; PPC64LE-NEXT: lbarx 6, 0, 3 605 ; PPC64LE-NEXT: cmpw 4, 6 606 ; PPC64LE-NEXT: bne 0, .LBB49_4 607 ; PPC64LE-NEXT: # %bb.2: 608 ; PPC64LE-NEXT: stbcx. 5, 0, 3 609 ; PPC64LE-NEXT: bne 0, .LBB49_1 610 ; PPC64LE-NEXT: # %bb.3: 611 ; PPC64LE-NEXT: lwsync 612 ; PPC64LE-NEXT: blr 613 ; PPC64LE-NEXT: .LBB49_4: 614 ; PPC64LE-NEXT: stbcx. 6, 0, 3 615 ; PPC64LE-NEXT: lwsync 616 ; PPC64LE-NEXT: blr 617 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst 618 ret void 619 } 620 621 define void @test50(i16* %ptr, i16 %cmp, i16 %val) { 622 ; PPC64LE-LABEL: test50: 623 ; PPC64LE: # %bb.0: 624 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 625 ; PPC64LE-NEXT: b .LBB50_2 626 ; PPC64LE-NEXT: .p2align 5 627 ; PPC64LE-NEXT: .LBB50_1: 628 ; PPC64LE-NEXT: sthcx. 5, 0, 3 629 ; PPC64LE-NEXT: beqlr 0 630 ; PPC64LE-NEXT: .LBB50_2: 631 ; PPC64LE-NEXT: lharx 6, 0, 3 632 ; PPC64LE-NEXT: cmpw 4, 6 633 ; PPC64LE-NEXT: beq 0, .LBB50_1 634 ; PPC64LE-NEXT: # %bb.3: 635 ; PPC64LE-NEXT: sthcx. 6, 0, 3 636 ; PPC64LE-NEXT: blr 637 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic 638 ret void 639 } 640 641 define void @test51(i16* %ptr, i16 %cmp, i16 %val) { 642 ; PPC64LE-LABEL: test51: 643 ; PPC64LE: # %bb.0: 644 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 645 ; PPC64LE-NEXT: .LBB51_1: 646 ; PPC64LE-NEXT: lharx 6, 0, 3 647 ; PPC64LE-NEXT: cmpw 4, 6 648 ; PPC64LE-NEXT: bne 0, .LBB51_4 649 ; PPC64LE-NEXT: # %bb.2: 650 ; PPC64LE-NEXT: sthcx. 5, 0, 3 651 ; PPC64LE-NEXT: bne 0, .LBB51_1 652 ; PPC64LE-NEXT: # %bb.3: 653 ; PPC64LE-NEXT: lwsync 654 ; PPC64LE-NEXT: blr 655 ; PPC64LE-NEXT: .LBB51_4: 656 ; PPC64LE-NEXT: sthcx. 6, 0, 3 657 ; PPC64LE-NEXT: lwsync 658 ; PPC64LE-NEXT: blr 659 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic 660 ret void 661 } 662 663 define void @test52(i16* %ptr, i16 %cmp, i16 %val) { 664 ; PPC64LE-LABEL: test52: 665 ; PPC64LE: # %bb.0: 666 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 667 ; PPC64LE-NEXT: .LBB52_1: 668 ; PPC64LE-NEXT: lharx 6, 0, 3 669 ; PPC64LE-NEXT: cmpw 4, 6 670 ; PPC64LE-NEXT: bne 0, .LBB52_4 671 ; PPC64LE-NEXT: # %bb.2: 672 ; PPC64LE-NEXT: sthcx. 5, 0, 3 673 ; PPC64LE-NEXT: bne 0, .LBB52_1 674 ; PPC64LE-NEXT: # %bb.3: 675 ; PPC64LE-NEXT: lwsync 676 ; PPC64LE-NEXT: blr 677 ; PPC64LE-NEXT: .LBB52_4: 678 ; PPC64LE-NEXT: sthcx. 6, 0, 3 679 ; PPC64LE-NEXT: lwsync 680 ; PPC64LE-NEXT: blr 681 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire 682 ret void 683 } 684 685 define void @test53(i16* %ptr, i16 %cmp, i16 %val) { 686 ; PPC64LE-LABEL: test53: 687 ; PPC64LE: # %bb.0: 688 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 689 ; PPC64LE-NEXT: lwsync 690 ; PPC64LE-NEXT: b .LBB53_2 691 ; PPC64LE-NEXT: .p2align 5 692 ; PPC64LE-NEXT: .LBB53_1: 693 ; PPC64LE-NEXT: sthcx. 5, 0, 3 694 ; PPC64LE-NEXT: beqlr 0 695 ; PPC64LE-NEXT: .LBB53_2: 696 ; PPC64LE-NEXT: lharx 6, 0, 3 697 ; PPC64LE-NEXT: cmpw 4, 6 698 ; PPC64LE-NEXT: beq 0, .LBB53_1 699 ; PPC64LE-NEXT: # %bb.3: 700 ; PPC64LE-NEXT: sthcx. 6, 0, 3 701 ; PPC64LE-NEXT: blr 702 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic 703 ret void 704 } 705 706 define void @test54(i16* %ptr, i16 %cmp, i16 %val) { 707 ; PPC64LE-LABEL: test54: 708 ; PPC64LE: # %bb.0: 709 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 710 ; PPC64LE-NEXT: lwsync 711 ; PPC64LE-NEXT: b .LBB54_2 712 ; PPC64LE-NEXT: .p2align 5 713 ; PPC64LE-NEXT: .LBB54_1: 714 ; PPC64LE-NEXT: sthcx. 5, 0, 3 715 ; PPC64LE-NEXT: beqlr 0 716 ; PPC64LE-NEXT: .LBB54_2: 717 ; PPC64LE-NEXT: lharx 6, 0, 3 718 ; PPC64LE-NEXT: cmpw 4, 6 719 ; PPC64LE-NEXT: beq 0, .LBB54_1 720 ; PPC64LE-NEXT: # %bb.3: 721 ; PPC64LE-NEXT: sthcx. 6, 0, 3 722 ; PPC64LE-NEXT: blr 723 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire 724 ret void 725 } 726 727 define void @test55(i16* %ptr, i16 %cmp, i16 %val) { 728 ; PPC64LE-LABEL: test55: 729 ; PPC64LE: # %bb.0: 730 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 731 ; PPC64LE-NEXT: lwsync 732 ; PPC64LE-NEXT: .LBB55_1: 733 ; PPC64LE-NEXT: lharx 6, 0, 3 734 ; PPC64LE-NEXT: cmpw 4, 6 735 ; PPC64LE-NEXT: bne 0, .LBB55_4 736 ; PPC64LE-NEXT: # %bb.2: 737 ; PPC64LE-NEXT: sthcx. 5, 0, 3 738 ; PPC64LE-NEXT: bne 0, .LBB55_1 739 ; PPC64LE-NEXT: # %bb.3: 740 ; PPC64LE-NEXT: lwsync 741 ; PPC64LE-NEXT: blr 742 ; PPC64LE-NEXT: .LBB55_4: 743 ; PPC64LE-NEXT: sthcx. 6, 0, 3 744 ; PPC64LE-NEXT: lwsync 745 ; PPC64LE-NEXT: blr 746 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic 747 ret void 748 } 749 750 define void @test56(i16* %ptr, i16 %cmp, i16 %val) { 751 ; PPC64LE-LABEL: test56: 752 ; PPC64LE: # %bb.0: 753 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 754 ; PPC64LE-NEXT: lwsync 755 ; PPC64LE-NEXT: .LBB56_1: 756 ; PPC64LE-NEXT: lharx 6, 0, 3 757 ; PPC64LE-NEXT: cmpw 4, 6 758 ; PPC64LE-NEXT: bne 0, .LBB56_4 759 ; PPC64LE-NEXT: # %bb.2: 760 ; PPC64LE-NEXT: sthcx. 5, 0, 3 761 ; PPC64LE-NEXT: bne 0, .LBB56_1 762 ; PPC64LE-NEXT: # %bb.3: 763 ; PPC64LE-NEXT: lwsync 764 ; PPC64LE-NEXT: blr 765 ; PPC64LE-NEXT: .LBB56_4: 766 ; PPC64LE-NEXT: sthcx. 6, 0, 3 767 ; PPC64LE-NEXT: lwsync 768 ; PPC64LE-NEXT: blr 769 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire 770 ret void 771 } 772 773 define void @test57(i16* %ptr, i16 %cmp, i16 %val) { 774 ; PPC64LE-LABEL: test57: 775 ; PPC64LE: # %bb.0: 776 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 777 ; PPC64LE-NEXT: sync 778 ; PPC64LE-NEXT: .LBB57_1: 779 ; PPC64LE-NEXT: lharx 6, 0, 3 780 ; PPC64LE-NEXT: cmpw 4, 6 781 ; PPC64LE-NEXT: bne 0, .LBB57_4 782 ; PPC64LE-NEXT: # %bb.2: 783 ; PPC64LE-NEXT: sthcx. 5, 0, 3 784 ; PPC64LE-NEXT: bne 0, .LBB57_1 785 ; PPC64LE-NEXT: # %bb.3: 786 ; PPC64LE-NEXT: lwsync 787 ; PPC64LE-NEXT: blr 788 ; PPC64LE-NEXT: .LBB57_4: 789 ; PPC64LE-NEXT: sthcx. 6, 0, 3 790 ; PPC64LE-NEXT: lwsync 791 ; PPC64LE-NEXT: blr 792 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic 793 ret void 794 } 795 796 define void @test58(i16* %ptr, i16 %cmp, i16 %val) { 797 ; PPC64LE-LABEL: test58: 798 ; PPC64LE: # %bb.0: 799 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 800 ; PPC64LE-NEXT: sync 801 ; PPC64LE-NEXT: .LBB58_1: 802 ; PPC64LE-NEXT: lharx 6, 0, 3 803 ; PPC64LE-NEXT: cmpw 4, 6 804 ; PPC64LE-NEXT: bne 0, .LBB58_4 805 ; PPC64LE-NEXT: # %bb.2: 806 ; PPC64LE-NEXT: sthcx. 5, 0, 3 807 ; PPC64LE-NEXT: bne 0, .LBB58_1 808 ; PPC64LE-NEXT: # %bb.3: 809 ; PPC64LE-NEXT: lwsync 810 ; PPC64LE-NEXT: blr 811 ; PPC64LE-NEXT: .LBB58_4: 812 ; PPC64LE-NEXT: sthcx. 6, 0, 3 813 ; PPC64LE-NEXT: lwsync 814 ; PPC64LE-NEXT: blr 815 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire 816 ret void 817 } 818 819 define void @test59(i16* %ptr, i16 %cmp, i16 %val) { 820 ; PPC64LE-LABEL: test59: 821 ; PPC64LE: # %bb.0: 822 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 823 ; PPC64LE-NEXT: sync 824 ; PPC64LE-NEXT: .LBB59_1: 825 ; PPC64LE-NEXT: lharx 6, 0, 3 826 ; PPC64LE-NEXT: cmpw 4, 6 827 ; PPC64LE-NEXT: bne 0, .LBB59_4 828 ; PPC64LE-NEXT: # %bb.2: 829 ; PPC64LE-NEXT: sthcx. 5, 0, 3 830 ; PPC64LE-NEXT: bne 0, .LBB59_1 831 ; PPC64LE-NEXT: # %bb.3: 832 ; PPC64LE-NEXT: lwsync 833 ; PPC64LE-NEXT: blr 834 ; PPC64LE-NEXT: .LBB59_4: 835 ; PPC64LE-NEXT: sthcx. 6, 0, 3 836 ; PPC64LE-NEXT: lwsync 837 ; PPC64LE-NEXT: blr 838 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst 839 ret void 840 } 841 842 define void @test60(i32* %ptr, i32 %cmp, i32 %val) { 843 ; PPC64LE-LABEL: test60: 844 ; PPC64LE: # %bb.0: 845 ; PPC64LE-NEXT: b .LBB60_2 846 ; PPC64LE-NEXT: .p2align 5 847 ; PPC64LE-NEXT: .LBB60_1: 848 ; PPC64LE-NEXT: stwcx. 5, 0, 3 849 ; PPC64LE-NEXT: beqlr 0 850 ; PPC64LE-NEXT: .LBB60_2: 851 ; PPC64LE-NEXT: lwarx 6, 0, 3 852 ; PPC64LE-NEXT: cmpw 4, 6 853 ; PPC64LE-NEXT: beq 0, .LBB60_1 854 ; PPC64LE-NEXT: # %bb.3: 855 ; PPC64LE-NEXT: stwcx. 6, 0, 3 856 ; PPC64LE-NEXT: blr 857 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic 858 ret void 859 } 860 861 define void @test61(i32* %ptr, i32 %cmp, i32 %val) { 862 ; PPC64LE-LABEL: test61: 863 ; PPC64LE: # %bb.0: 864 ; PPC64LE-NEXT: .LBB61_1: 865 ; PPC64LE-NEXT: lwarx 6, 0, 3 866 ; PPC64LE-NEXT: cmpw 4, 6 867 ; PPC64LE-NEXT: bne 0, .LBB61_4 868 ; PPC64LE-NEXT: # %bb.2: 869 ; PPC64LE-NEXT: stwcx. 5, 0, 3 870 ; PPC64LE-NEXT: bne 0, .LBB61_1 871 ; PPC64LE-NEXT: # %bb.3: 872 ; PPC64LE-NEXT: lwsync 873 ; PPC64LE-NEXT: blr 874 ; PPC64LE-NEXT: .LBB61_4: 875 ; PPC64LE-NEXT: stwcx. 6, 0, 3 876 ; PPC64LE-NEXT: lwsync 877 ; PPC64LE-NEXT: blr 878 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic 879 ret void 880 } 881 882 define void @test62(i32* %ptr, i32 %cmp, i32 %val) { 883 ; PPC64LE-LABEL: test62: 884 ; PPC64LE: # %bb.0: 885 ; PPC64LE-NEXT: .LBB62_1: 886 ; PPC64LE-NEXT: lwarx 6, 0, 3 887 ; PPC64LE-NEXT: cmpw 4, 6 888 ; PPC64LE-NEXT: bne 0, .LBB62_4 889 ; PPC64LE-NEXT: # %bb.2: 890 ; PPC64LE-NEXT: stwcx. 5, 0, 3 891 ; PPC64LE-NEXT: bne 0, .LBB62_1 892 ; PPC64LE-NEXT: # %bb.3: 893 ; PPC64LE-NEXT: lwsync 894 ; PPC64LE-NEXT: blr 895 ; PPC64LE-NEXT: .LBB62_4: 896 ; PPC64LE-NEXT: stwcx. 6, 0, 3 897 ; PPC64LE-NEXT: lwsync 898 ; PPC64LE-NEXT: blr 899 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire 900 ret void 901 } 902 903 define void @test63(i32* %ptr, i32 %cmp, i32 %val) { 904 ; PPC64LE-LABEL: test63: 905 ; PPC64LE: # %bb.0: 906 ; PPC64LE-NEXT: lwsync 907 ; PPC64LE-NEXT: b .LBB63_2 908 ; PPC64LE-NEXT: .p2align 5 909 ; PPC64LE-NEXT: .LBB63_1: 910 ; PPC64LE-NEXT: stwcx. 5, 0, 3 911 ; PPC64LE-NEXT: beqlr 0 912 ; PPC64LE-NEXT: .LBB63_2: 913 ; PPC64LE-NEXT: lwarx 6, 0, 3 914 ; PPC64LE-NEXT: cmpw 4, 6 915 ; PPC64LE-NEXT: beq 0, .LBB63_1 916 ; PPC64LE-NEXT: # %bb.3: 917 ; PPC64LE-NEXT: stwcx. 6, 0, 3 918 ; PPC64LE-NEXT: blr 919 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic 920 ret void 921 } 922 923 define void @test64(i32* %ptr, i32 %cmp, i32 %val) { 924 ; PPC64LE-LABEL: test64: 925 ; PPC64LE: # %bb.0: 926 ; PPC64LE-NEXT: lwsync 927 ; PPC64LE-NEXT: b .LBB64_2 928 ; PPC64LE-NEXT: .p2align 5 929 ; PPC64LE-NEXT: .LBB64_1: 930 ; PPC64LE-NEXT: stwcx. 5, 0, 3 931 ; PPC64LE-NEXT: beqlr 0 932 ; PPC64LE-NEXT: .LBB64_2: 933 ; PPC64LE-NEXT: lwarx 6, 0, 3 934 ; PPC64LE-NEXT: cmpw 4, 6 935 ; PPC64LE-NEXT: beq 0, .LBB64_1 936 ; PPC64LE-NEXT: # %bb.3: 937 ; PPC64LE-NEXT: stwcx. 6, 0, 3 938 ; PPC64LE-NEXT: blr 939 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire 940 ret void 941 } 942 943 define void @test65(i32* %ptr, i32 %cmp, i32 %val) { 944 ; PPC64LE-LABEL: test65: 945 ; PPC64LE: # %bb.0: 946 ; PPC64LE-NEXT: lwsync 947 ; PPC64LE-NEXT: .LBB65_1: 948 ; PPC64LE-NEXT: lwarx 6, 0, 3 949 ; PPC64LE-NEXT: cmpw 4, 6 950 ; PPC64LE-NEXT: bne 0, .LBB65_4 951 ; PPC64LE-NEXT: # %bb.2: 952 ; PPC64LE-NEXT: stwcx. 5, 0, 3 953 ; PPC64LE-NEXT: bne 0, .LBB65_1 954 ; PPC64LE-NEXT: # %bb.3: 955 ; PPC64LE-NEXT: lwsync 956 ; PPC64LE-NEXT: blr 957 ; PPC64LE-NEXT: .LBB65_4: 958 ; PPC64LE-NEXT: stwcx. 6, 0, 3 959 ; PPC64LE-NEXT: lwsync 960 ; PPC64LE-NEXT: blr 961 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic 962 ret void 963 } 964 965 define void @test66(i32* %ptr, i32 %cmp, i32 %val) { 966 ; PPC64LE-LABEL: test66: 967 ; PPC64LE: # %bb.0: 968 ; PPC64LE-NEXT: lwsync 969 ; PPC64LE-NEXT: .LBB66_1: 970 ; PPC64LE-NEXT: lwarx 6, 0, 3 971 ; PPC64LE-NEXT: cmpw 4, 6 972 ; PPC64LE-NEXT: bne 0, .LBB66_4 973 ; PPC64LE-NEXT: # %bb.2: 974 ; PPC64LE-NEXT: stwcx. 5, 0, 3 975 ; PPC64LE-NEXT: bne 0, .LBB66_1 976 ; PPC64LE-NEXT: # %bb.3: 977 ; PPC64LE-NEXT: lwsync 978 ; PPC64LE-NEXT: blr 979 ; PPC64LE-NEXT: .LBB66_4: 980 ; PPC64LE-NEXT: stwcx. 6, 0, 3 981 ; PPC64LE-NEXT: lwsync 982 ; PPC64LE-NEXT: blr 983 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire 984 ret void 985 } 986 987 define void @test67(i32* %ptr, i32 %cmp, i32 %val) { 988 ; PPC64LE-LABEL: test67: 989 ; PPC64LE: # %bb.0: 990 ; PPC64LE-NEXT: sync 991 ; PPC64LE-NEXT: .LBB67_1: 992 ; PPC64LE-NEXT: lwarx 6, 0, 3 993 ; PPC64LE-NEXT: cmpw 4, 6 994 ; PPC64LE-NEXT: bne 0, .LBB67_4 995 ; PPC64LE-NEXT: # %bb.2: 996 ; PPC64LE-NEXT: stwcx. 5, 0, 3 997 ; PPC64LE-NEXT: bne 0, .LBB67_1 998 ; PPC64LE-NEXT: # %bb.3: 999 ; PPC64LE-NEXT: lwsync 1000 ; PPC64LE-NEXT: blr 1001 ; PPC64LE-NEXT: .LBB67_4: 1002 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1003 ; PPC64LE-NEXT: lwsync 1004 ; PPC64LE-NEXT: blr 1005 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic 1006 ret void 1007 } 1008 1009 define void @test68(i32* %ptr, i32 %cmp, i32 %val) { 1010 ; PPC64LE-LABEL: test68: 1011 ; PPC64LE: # %bb.0: 1012 ; PPC64LE-NEXT: sync 1013 ; PPC64LE-NEXT: .LBB68_1: 1014 ; PPC64LE-NEXT: lwarx 6, 0, 3 1015 ; PPC64LE-NEXT: cmpw 4, 6 1016 ; PPC64LE-NEXT: bne 0, .LBB68_4 1017 ; PPC64LE-NEXT: # %bb.2: 1018 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1019 ; PPC64LE-NEXT: bne 0, .LBB68_1 1020 ; PPC64LE-NEXT: # %bb.3: 1021 ; PPC64LE-NEXT: lwsync 1022 ; PPC64LE-NEXT: blr 1023 ; PPC64LE-NEXT: .LBB68_4: 1024 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1025 ; PPC64LE-NEXT: lwsync 1026 ; PPC64LE-NEXT: blr 1027 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire 1028 ret void 1029 } 1030 1031 define void @test69(i32* %ptr, i32 %cmp, i32 %val) { 1032 ; PPC64LE-LABEL: test69: 1033 ; PPC64LE: # %bb.0: 1034 ; PPC64LE-NEXT: sync 1035 ; PPC64LE-NEXT: .LBB69_1: 1036 ; PPC64LE-NEXT: lwarx 6, 0, 3 1037 ; PPC64LE-NEXT: cmpw 4, 6 1038 ; PPC64LE-NEXT: bne 0, .LBB69_4 1039 ; PPC64LE-NEXT: # %bb.2: 1040 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1041 ; PPC64LE-NEXT: bne 0, .LBB69_1 1042 ; PPC64LE-NEXT: # %bb.3: 1043 ; PPC64LE-NEXT: lwsync 1044 ; PPC64LE-NEXT: blr 1045 ; PPC64LE-NEXT: .LBB69_4: 1046 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1047 ; PPC64LE-NEXT: lwsync 1048 ; PPC64LE-NEXT: blr 1049 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst 1050 ret void 1051 } 1052 1053 define void @test70(i64* %ptr, i64 %cmp, i64 %val) { 1054 ; PPC64LE-LABEL: test70: 1055 ; PPC64LE: # %bb.0: 1056 ; PPC64LE-NEXT: b .LBB70_2 1057 ; PPC64LE-NEXT: .p2align 5 1058 ; PPC64LE-NEXT: .LBB70_1: 1059 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1060 ; PPC64LE-NEXT: beqlr 0 1061 ; PPC64LE-NEXT: .LBB70_2: 1062 ; PPC64LE-NEXT: ldarx 6, 0, 3 1063 ; PPC64LE-NEXT: cmpd 4, 6 1064 ; PPC64LE-NEXT: beq 0, .LBB70_1 1065 ; PPC64LE-NEXT: # %bb.3: 1066 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1067 ; PPC64LE-NEXT: blr 1068 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic 1069 ret void 1070 } 1071 1072 define void @test71(i64* %ptr, i64 %cmp, i64 %val) { 1073 ; PPC64LE-LABEL: test71: 1074 ; PPC64LE: # %bb.0: 1075 ; PPC64LE-NEXT: .LBB71_1: 1076 ; PPC64LE-NEXT: ldarx 6, 0, 3 1077 ; PPC64LE-NEXT: cmpd 4, 6 1078 ; PPC64LE-NEXT: bne 0, .LBB71_4 1079 ; PPC64LE-NEXT: # %bb.2: 1080 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1081 ; PPC64LE-NEXT: bne 0, .LBB71_1 1082 ; PPC64LE-NEXT: # %bb.3: 1083 ; PPC64LE-NEXT: lwsync 1084 ; PPC64LE-NEXT: blr 1085 ; PPC64LE-NEXT: .LBB71_4: 1086 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1087 ; PPC64LE-NEXT: lwsync 1088 ; PPC64LE-NEXT: blr 1089 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic 1090 ret void 1091 } 1092 1093 define void @test72(i64* %ptr, i64 %cmp, i64 %val) { 1094 ; PPC64LE-LABEL: test72: 1095 ; PPC64LE: # %bb.0: 1096 ; PPC64LE-NEXT: .LBB72_1: 1097 ; PPC64LE-NEXT: ldarx 6, 0, 3 1098 ; PPC64LE-NEXT: cmpd 4, 6 1099 ; PPC64LE-NEXT: bne 0, .LBB72_4 1100 ; PPC64LE-NEXT: # %bb.2: 1101 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1102 ; PPC64LE-NEXT: bne 0, .LBB72_1 1103 ; PPC64LE-NEXT: # %bb.3: 1104 ; PPC64LE-NEXT: lwsync 1105 ; PPC64LE-NEXT: blr 1106 ; PPC64LE-NEXT: .LBB72_4: 1107 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1108 ; PPC64LE-NEXT: lwsync 1109 ; PPC64LE-NEXT: blr 1110 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire 1111 ret void 1112 } 1113 1114 define void @test73(i64* %ptr, i64 %cmp, i64 %val) { 1115 ; PPC64LE-LABEL: test73: 1116 ; PPC64LE: # %bb.0: 1117 ; PPC64LE-NEXT: lwsync 1118 ; PPC64LE-NEXT: b .LBB73_2 1119 ; PPC64LE-NEXT: .p2align 5 1120 ; PPC64LE-NEXT: .LBB73_1: 1121 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1122 ; PPC64LE-NEXT: beqlr 0 1123 ; PPC64LE-NEXT: .LBB73_2: 1124 ; PPC64LE-NEXT: ldarx 6, 0, 3 1125 ; PPC64LE-NEXT: cmpd 4, 6 1126 ; PPC64LE-NEXT: beq 0, .LBB73_1 1127 ; PPC64LE-NEXT: # %bb.3: 1128 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1129 ; PPC64LE-NEXT: blr 1130 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic 1131 ret void 1132 } 1133 1134 define void @test74(i64* %ptr, i64 %cmp, i64 %val) { 1135 ; PPC64LE-LABEL: test74: 1136 ; PPC64LE: # %bb.0: 1137 ; PPC64LE-NEXT: lwsync 1138 ; PPC64LE-NEXT: b .LBB74_2 1139 ; PPC64LE-NEXT: .p2align 5 1140 ; PPC64LE-NEXT: .LBB74_1: 1141 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1142 ; PPC64LE-NEXT: beqlr 0 1143 ; PPC64LE-NEXT: .LBB74_2: 1144 ; PPC64LE-NEXT: ldarx 6, 0, 3 1145 ; PPC64LE-NEXT: cmpd 4, 6 1146 ; PPC64LE-NEXT: beq 0, .LBB74_1 1147 ; PPC64LE-NEXT: # %bb.3: 1148 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1149 ; PPC64LE-NEXT: blr 1150 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire 1151 ret void 1152 } 1153 1154 define void @test75(i64* %ptr, i64 %cmp, i64 %val) { 1155 ; PPC64LE-LABEL: test75: 1156 ; PPC64LE: # %bb.0: 1157 ; PPC64LE-NEXT: lwsync 1158 ; PPC64LE-NEXT: .LBB75_1: 1159 ; PPC64LE-NEXT: ldarx 6, 0, 3 1160 ; PPC64LE-NEXT: cmpd 4, 6 1161 ; PPC64LE-NEXT: bne 0, .LBB75_4 1162 ; PPC64LE-NEXT: # %bb.2: 1163 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1164 ; PPC64LE-NEXT: bne 0, .LBB75_1 1165 ; PPC64LE-NEXT: # %bb.3: 1166 ; PPC64LE-NEXT: lwsync 1167 ; PPC64LE-NEXT: blr 1168 ; PPC64LE-NEXT: .LBB75_4: 1169 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1170 ; PPC64LE-NEXT: lwsync 1171 ; PPC64LE-NEXT: blr 1172 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic 1173 ret void 1174 } 1175 1176 define void @test76(i64* %ptr, i64 %cmp, i64 %val) { 1177 ; PPC64LE-LABEL: test76: 1178 ; PPC64LE: # %bb.0: 1179 ; PPC64LE-NEXT: lwsync 1180 ; PPC64LE-NEXT: .LBB76_1: 1181 ; PPC64LE-NEXT: ldarx 6, 0, 3 1182 ; PPC64LE-NEXT: cmpd 4, 6 1183 ; PPC64LE-NEXT: bne 0, .LBB76_4 1184 ; PPC64LE-NEXT: # %bb.2: 1185 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1186 ; PPC64LE-NEXT: bne 0, .LBB76_1 1187 ; PPC64LE-NEXT: # %bb.3: 1188 ; PPC64LE-NEXT: lwsync 1189 ; PPC64LE-NEXT: blr 1190 ; PPC64LE-NEXT: .LBB76_4: 1191 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1192 ; PPC64LE-NEXT: lwsync 1193 ; PPC64LE-NEXT: blr 1194 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire 1195 ret void 1196 } 1197 1198 define void @test77(i64* %ptr, i64 %cmp, i64 %val) { 1199 ; PPC64LE-LABEL: test77: 1200 ; PPC64LE: # %bb.0: 1201 ; PPC64LE-NEXT: sync 1202 ; PPC64LE-NEXT: .LBB77_1: 1203 ; PPC64LE-NEXT: ldarx 6, 0, 3 1204 ; PPC64LE-NEXT: cmpd 4, 6 1205 ; PPC64LE-NEXT: bne 0, .LBB77_4 1206 ; PPC64LE-NEXT: # %bb.2: 1207 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1208 ; PPC64LE-NEXT: bne 0, .LBB77_1 1209 ; PPC64LE-NEXT: # %bb.3: 1210 ; PPC64LE-NEXT: lwsync 1211 ; PPC64LE-NEXT: blr 1212 ; PPC64LE-NEXT: .LBB77_4: 1213 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1214 ; PPC64LE-NEXT: lwsync 1215 ; PPC64LE-NEXT: blr 1216 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic 1217 ret void 1218 } 1219 1220 define void @test78(i64* %ptr, i64 %cmp, i64 %val) { 1221 ; PPC64LE-LABEL: test78: 1222 ; PPC64LE: # %bb.0: 1223 ; PPC64LE-NEXT: sync 1224 ; PPC64LE-NEXT: .LBB78_1: 1225 ; PPC64LE-NEXT: ldarx 6, 0, 3 1226 ; PPC64LE-NEXT: cmpd 4, 6 1227 ; PPC64LE-NEXT: bne 0, .LBB78_4 1228 ; PPC64LE-NEXT: # %bb.2: 1229 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1230 ; PPC64LE-NEXT: bne 0, .LBB78_1 1231 ; PPC64LE-NEXT: # %bb.3: 1232 ; PPC64LE-NEXT: lwsync 1233 ; PPC64LE-NEXT: blr 1234 ; PPC64LE-NEXT: .LBB78_4: 1235 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1236 ; PPC64LE-NEXT: lwsync 1237 ; PPC64LE-NEXT: blr 1238 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire 1239 ret void 1240 } 1241 1242 define void @test79(i64* %ptr, i64 %cmp, i64 %val) { 1243 ; PPC64LE-LABEL: test79: 1244 ; PPC64LE: # %bb.0: 1245 ; PPC64LE-NEXT: sync 1246 ; PPC64LE-NEXT: .LBB79_1: 1247 ; PPC64LE-NEXT: ldarx 6, 0, 3 1248 ; PPC64LE-NEXT: cmpd 4, 6 1249 ; PPC64LE-NEXT: bne 0, .LBB79_4 1250 ; PPC64LE-NEXT: # %bb.2: 1251 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1252 ; PPC64LE-NEXT: bne 0, .LBB79_1 1253 ; PPC64LE-NEXT: # %bb.3: 1254 ; PPC64LE-NEXT: lwsync 1255 ; PPC64LE-NEXT: blr 1256 ; PPC64LE-NEXT: .LBB79_4: 1257 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1258 ; PPC64LE-NEXT: lwsync 1259 ; PPC64LE-NEXT: blr 1260 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst 1261 ret void 1262 } 1263 1264 define void @test80(i8* %ptr, i8 %cmp, i8 %val) { 1265 ; PPC64LE-LABEL: test80: 1266 ; PPC64LE: # %bb.0: 1267 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1268 ; PPC64LE-NEXT: b .LBB80_2 1269 ; PPC64LE-NEXT: .p2align 5 1270 ; PPC64LE-NEXT: .LBB80_1: 1271 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1272 ; PPC64LE-NEXT: beqlr 0 1273 ; PPC64LE-NEXT: .LBB80_2: 1274 ; PPC64LE-NEXT: lbarx 6, 0, 3 1275 ; PPC64LE-NEXT: cmpw 4, 6 1276 ; PPC64LE-NEXT: beq 0, .LBB80_1 1277 ; PPC64LE-NEXT: # %bb.3: 1278 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1279 ; PPC64LE-NEXT: blr 1280 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic 1281 ret void 1282 } 1283 1284 define void @test81(i8* %ptr, i8 %cmp, i8 %val) { 1285 ; PPC64LE-LABEL: test81: 1286 ; PPC64LE: # %bb.0: 1287 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1288 ; PPC64LE-NEXT: .LBB81_1: 1289 ; PPC64LE-NEXT: lbarx 6, 0, 3 1290 ; PPC64LE-NEXT: cmpw 4, 6 1291 ; PPC64LE-NEXT: bne 0, .LBB81_4 1292 ; PPC64LE-NEXT: # %bb.2: 1293 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1294 ; PPC64LE-NEXT: bne 0, .LBB81_1 1295 ; PPC64LE-NEXT: # %bb.3: 1296 ; PPC64LE-NEXT: lwsync 1297 ; PPC64LE-NEXT: blr 1298 ; PPC64LE-NEXT: .LBB81_4: 1299 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1300 ; PPC64LE-NEXT: lwsync 1301 ; PPC64LE-NEXT: blr 1302 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic 1303 ret void 1304 } 1305 1306 define void @test82(i8* %ptr, i8 %cmp, i8 %val) { 1307 ; PPC64LE-LABEL: test82: 1308 ; PPC64LE: # %bb.0: 1309 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1310 ; PPC64LE-NEXT: .LBB82_1: 1311 ; PPC64LE-NEXT: lbarx 6, 0, 3 1312 ; PPC64LE-NEXT: cmpw 4, 6 1313 ; PPC64LE-NEXT: bne 0, .LBB82_4 1314 ; PPC64LE-NEXT: # %bb.2: 1315 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1316 ; PPC64LE-NEXT: bne 0, .LBB82_1 1317 ; PPC64LE-NEXT: # %bb.3: 1318 ; PPC64LE-NEXT: lwsync 1319 ; PPC64LE-NEXT: blr 1320 ; PPC64LE-NEXT: .LBB82_4: 1321 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1322 ; PPC64LE-NEXT: lwsync 1323 ; PPC64LE-NEXT: blr 1324 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire 1325 ret void 1326 } 1327 1328 define void @test83(i8* %ptr, i8 %cmp, i8 %val) { 1329 ; PPC64LE-LABEL: test83: 1330 ; PPC64LE: # %bb.0: 1331 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1332 ; PPC64LE-NEXT: lwsync 1333 ; PPC64LE-NEXT: b .LBB83_2 1334 ; PPC64LE-NEXT: .p2align 5 1335 ; PPC64LE-NEXT: .LBB83_1: 1336 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1337 ; PPC64LE-NEXT: beqlr 0 1338 ; PPC64LE-NEXT: .LBB83_2: 1339 ; PPC64LE-NEXT: lbarx 6, 0, 3 1340 ; PPC64LE-NEXT: cmpw 4, 6 1341 ; PPC64LE-NEXT: beq 0, .LBB83_1 1342 ; PPC64LE-NEXT: # %bb.3: 1343 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1344 ; PPC64LE-NEXT: blr 1345 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic 1346 ret void 1347 } 1348 1349 define void @test84(i8* %ptr, i8 %cmp, i8 %val) { 1350 ; PPC64LE-LABEL: test84: 1351 ; PPC64LE: # %bb.0: 1352 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1353 ; PPC64LE-NEXT: lwsync 1354 ; PPC64LE-NEXT: b .LBB84_2 1355 ; PPC64LE-NEXT: .p2align 5 1356 ; PPC64LE-NEXT: .LBB84_1: 1357 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1358 ; PPC64LE-NEXT: beqlr 0 1359 ; PPC64LE-NEXT: .LBB84_2: 1360 ; PPC64LE-NEXT: lbarx 6, 0, 3 1361 ; PPC64LE-NEXT: cmpw 4, 6 1362 ; PPC64LE-NEXT: beq 0, .LBB84_1 1363 ; PPC64LE-NEXT: # %bb.3: 1364 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1365 ; PPC64LE-NEXT: blr 1366 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire 1367 ret void 1368 } 1369 1370 define void @test85(i8* %ptr, i8 %cmp, i8 %val) { 1371 ; PPC64LE-LABEL: test85: 1372 ; PPC64LE: # %bb.0: 1373 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1374 ; PPC64LE-NEXT: lwsync 1375 ; PPC64LE-NEXT: .LBB85_1: 1376 ; PPC64LE-NEXT: lbarx 6, 0, 3 1377 ; PPC64LE-NEXT: cmpw 4, 6 1378 ; PPC64LE-NEXT: bne 0, .LBB85_4 1379 ; PPC64LE-NEXT: # %bb.2: 1380 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1381 ; PPC64LE-NEXT: bne 0, .LBB85_1 1382 ; PPC64LE-NEXT: # %bb.3: 1383 ; PPC64LE-NEXT: lwsync 1384 ; PPC64LE-NEXT: blr 1385 ; PPC64LE-NEXT: .LBB85_4: 1386 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1387 ; PPC64LE-NEXT: lwsync 1388 ; PPC64LE-NEXT: blr 1389 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic 1390 ret void 1391 } 1392 1393 define void @test86(i8* %ptr, i8 %cmp, i8 %val) { 1394 ; PPC64LE-LABEL: test86: 1395 ; PPC64LE: # %bb.0: 1396 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1397 ; PPC64LE-NEXT: lwsync 1398 ; PPC64LE-NEXT: .LBB86_1: 1399 ; PPC64LE-NEXT: lbarx 6, 0, 3 1400 ; PPC64LE-NEXT: cmpw 4, 6 1401 ; PPC64LE-NEXT: bne 0, .LBB86_4 1402 ; PPC64LE-NEXT: # %bb.2: 1403 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1404 ; PPC64LE-NEXT: bne 0, .LBB86_1 1405 ; PPC64LE-NEXT: # %bb.3: 1406 ; PPC64LE-NEXT: lwsync 1407 ; PPC64LE-NEXT: blr 1408 ; PPC64LE-NEXT: .LBB86_4: 1409 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1410 ; PPC64LE-NEXT: lwsync 1411 ; PPC64LE-NEXT: blr 1412 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire 1413 ret void 1414 } 1415 1416 define void @test87(i8* %ptr, i8 %cmp, i8 %val) { 1417 ; PPC64LE-LABEL: test87: 1418 ; PPC64LE: # %bb.0: 1419 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1420 ; PPC64LE-NEXT: sync 1421 ; PPC64LE-NEXT: .LBB87_1: 1422 ; PPC64LE-NEXT: lbarx 6, 0, 3 1423 ; PPC64LE-NEXT: cmpw 4, 6 1424 ; PPC64LE-NEXT: bne 0, .LBB87_4 1425 ; PPC64LE-NEXT: # %bb.2: 1426 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1427 ; PPC64LE-NEXT: bne 0, .LBB87_1 1428 ; PPC64LE-NEXT: # %bb.3: 1429 ; PPC64LE-NEXT: lwsync 1430 ; PPC64LE-NEXT: blr 1431 ; PPC64LE-NEXT: .LBB87_4: 1432 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1433 ; PPC64LE-NEXT: lwsync 1434 ; PPC64LE-NEXT: blr 1435 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic 1436 ret void 1437 } 1438 1439 define void @test88(i8* %ptr, i8 %cmp, i8 %val) { 1440 ; PPC64LE-LABEL: test88: 1441 ; PPC64LE: # %bb.0: 1442 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1443 ; PPC64LE-NEXT: sync 1444 ; PPC64LE-NEXT: .LBB88_1: 1445 ; PPC64LE-NEXT: lbarx 6, 0, 3 1446 ; PPC64LE-NEXT: cmpw 4, 6 1447 ; PPC64LE-NEXT: bne 0, .LBB88_4 1448 ; PPC64LE-NEXT: # %bb.2: 1449 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1450 ; PPC64LE-NEXT: bne 0, .LBB88_1 1451 ; PPC64LE-NEXT: # %bb.3: 1452 ; PPC64LE-NEXT: lwsync 1453 ; PPC64LE-NEXT: blr 1454 ; PPC64LE-NEXT: .LBB88_4: 1455 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1456 ; PPC64LE-NEXT: lwsync 1457 ; PPC64LE-NEXT: blr 1458 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire 1459 ret void 1460 } 1461 1462 define void @test89(i8* %ptr, i8 %cmp, i8 %val) { 1463 ; PPC64LE-LABEL: test89: 1464 ; PPC64LE: # %bb.0: 1465 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 1466 ; PPC64LE-NEXT: sync 1467 ; PPC64LE-NEXT: .LBB89_1: 1468 ; PPC64LE-NEXT: lbarx 6, 0, 3 1469 ; PPC64LE-NEXT: cmpw 4, 6 1470 ; PPC64LE-NEXT: bne 0, .LBB89_4 1471 ; PPC64LE-NEXT: # %bb.2: 1472 ; PPC64LE-NEXT: stbcx. 5, 0, 3 1473 ; PPC64LE-NEXT: bne 0, .LBB89_1 1474 ; PPC64LE-NEXT: # %bb.3: 1475 ; PPC64LE-NEXT: lwsync 1476 ; PPC64LE-NEXT: blr 1477 ; PPC64LE-NEXT: .LBB89_4: 1478 ; PPC64LE-NEXT: stbcx. 6, 0, 3 1479 ; PPC64LE-NEXT: lwsync 1480 ; PPC64LE-NEXT: blr 1481 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst 1482 ret void 1483 } 1484 1485 define void @test90(i16* %ptr, i16 %cmp, i16 %val) { 1486 ; PPC64LE-LABEL: test90: 1487 ; PPC64LE: # %bb.0: 1488 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1489 ; PPC64LE-NEXT: b .LBB90_2 1490 ; PPC64LE-NEXT: .p2align 5 1491 ; PPC64LE-NEXT: .LBB90_1: 1492 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1493 ; PPC64LE-NEXT: beqlr 0 1494 ; PPC64LE-NEXT: .LBB90_2: 1495 ; PPC64LE-NEXT: lharx 6, 0, 3 1496 ; PPC64LE-NEXT: cmpw 4, 6 1497 ; PPC64LE-NEXT: beq 0, .LBB90_1 1498 ; PPC64LE-NEXT: # %bb.3: 1499 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1500 ; PPC64LE-NEXT: blr 1501 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic 1502 ret void 1503 } 1504 1505 define void @test91(i16* %ptr, i16 %cmp, i16 %val) { 1506 ; PPC64LE-LABEL: test91: 1507 ; PPC64LE: # %bb.0: 1508 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1509 ; PPC64LE-NEXT: .LBB91_1: 1510 ; PPC64LE-NEXT: lharx 6, 0, 3 1511 ; PPC64LE-NEXT: cmpw 4, 6 1512 ; PPC64LE-NEXT: bne 0, .LBB91_4 1513 ; PPC64LE-NEXT: # %bb.2: 1514 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1515 ; PPC64LE-NEXT: bne 0, .LBB91_1 1516 ; PPC64LE-NEXT: # %bb.3: 1517 ; PPC64LE-NEXT: lwsync 1518 ; PPC64LE-NEXT: blr 1519 ; PPC64LE-NEXT: .LBB91_4: 1520 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1521 ; PPC64LE-NEXT: lwsync 1522 ; PPC64LE-NEXT: blr 1523 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic 1524 ret void 1525 } 1526 1527 define void @test92(i16* %ptr, i16 %cmp, i16 %val) { 1528 ; PPC64LE-LABEL: test92: 1529 ; PPC64LE: # %bb.0: 1530 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1531 ; PPC64LE-NEXT: .LBB92_1: 1532 ; PPC64LE-NEXT: lharx 6, 0, 3 1533 ; PPC64LE-NEXT: cmpw 4, 6 1534 ; PPC64LE-NEXT: bne 0, .LBB92_4 1535 ; PPC64LE-NEXT: # %bb.2: 1536 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1537 ; PPC64LE-NEXT: bne 0, .LBB92_1 1538 ; PPC64LE-NEXT: # %bb.3: 1539 ; PPC64LE-NEXT: lwsync 1540 ; PPC64LE-NEXT: blr 1541 ; PPC64LE-NEXT: .LBB92_4: 1542 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1543 ; PPC64LE-NEXT: lwsync 1544 ; PPC64LE-NEXT: blr 1545 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire 1546 ret void 1547 } 1548 1549 define void @test93(i16* %ptr, i16 %cmp, i16 %val) { 1550 ; PPC64LE-LABEL: test93: 1551 ; PPC64LE: # %bb.0: 1552 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1553 ; PPC64LE-NEXT: lwsync 1554 ; PPC64LE-NEXT: b .LBB93_2 1555 ; PPC64LE-NEXT: .p2align 5 1556 ; PPC64LE-NEXT: .LBB93_1: 1557 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1558 ; PPC64LE-NEXT: beqlr 0 1559 ; PPC64LE-NEXT: .LBB93_2: 1560 ; PPC64LE-NEXT: lharx 6, 0, 3 1561 ; PPC64LE-NEXT: cmpw 4, 6 1562 ; PPC64LE-NEXT: beq 0, .LBB93_1 1563 ; PPC64LE-NEXT: # %bb.3: 1564 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1565 ; PPC64LE-NEXT: blr 1566 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic 1567 ret void 1568 } 1569 1570 define void @test94(i16* %ptr, i16 %cmp, i16 %val) { 1571 ; PPC64LE-LABEL: test94: 1572 ; PPC64LE: # %bb.0: 1573 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1574 ; PPC64LE-NEXT: lwsync 1575 ; PPC64LE-NEXT: b .LBB94_2 1576 ; PPC64LE-NEXT: .p2align 5 1577 ; PPC64LE-NEXT: .LBB94_1: 1578 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1579 ; PPC64LE-NEXT: beqlr 0 1580 ; PPC64LE-NEXT: .LBB94_2: 1581 ; PPC64LE-NEXT: lharx 6, 0, 3 1582 ; PPC64LE-NEXT: cmpw 4, 6 1583 ; PPC64LE-NEXT: beq 0, .LBB94_1 1584 ; PPC64LE-NEXT: # %bb.3: 1585 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1586 ; PPC64LE-NEXT: blr 1587 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire 1588 ret void 1589 } 1590 1591 define void @test95(i16* %ptr, i16 %cmp, i16 %val) { 1592 ; PPC64LE-LABEL: test95: 1593 ; PPC64LE: # %bb.0: 1594 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1595 ; PPC64LE-NEXT: lwsync 1596 ; PPC64LE-NEXT: .LBB95_1: 1597 ; PPC64LE-NEXT: lharx 6, 0, 3 1598 ; PPC64LE-NEXT: cmpw 4, 6 1599 ; PPC64LE-NEXT: bne 0, .LBB95_4 1600 ; PPC64LE-NEXT: # %bb.2: 1601 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1602 ; PPC64LE-NEXT: bne 0, .LBB95_1 1603 ; PPC64LE-NEXT: # %bb.3: 1604 ; PPC64LE-NEXT: lwsync 1605 ; PPC64LE-NEXT: blr 1606 ; PPC64LE-NEXT: .LBB95_4: 1607 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1608 ; PPC64LE-NEXT: lwsync 1609 ; PPC64LE-NEXT: blr 1610 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic 1611 ret void 1612 } 1613 1614 define void @test96(i16* %ptr, i16 %cmp, i16 %val) { 1615 ; PPC64LE-LABEL: test96: 1616 ; PPC64LE: # %bb.0: 1617 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1618 ; PPC64LE-NEXT: lwsync 1619 ; PPC64LE-NEXT: .LBB96_1: 1620 ; PPC64LE-NEXT: lharx 6, 0, 3 1621 ; PPC64LE-NEXT: cmpw 4, 6 1622 ; PPC64LE-NEXT: bne 0, .LBB96_4 1623 ; PPC64LE-NEXT: # %bb.2: 1624 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1625 ; PPC64LE-NEXT: bne 0, .LBB96_1 1626 ; PPC64LE-NEXT: # %bb.3: 1627 ; PPC64LE-NEXT: lwsync 1628 ; PPC64LE-NEXT: blr 1629 ; PPC64LE-NEXT: .LBB96_4: 1630 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1631 ; PPC64LE-NEXT: lwsync 1632 ; PPC64LE-NEXT: blr 1633 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire 1634 ret void 1635 } 1636 1637 define void @test97(i16* %ptr, i16 %cmp, i16 %val) { 1638 ; PPC64LE-LABEL: test97: 1639 ; PPC64LE: # %bb.0: 1640 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1641 ; PPC64LE-NEXT: sync 1642 ; PPC64LE-NEXT: .LBB97_1: 1643 ; PPC64LE-NEXT: lharx 6, 0, 3 1644 ; PPC64LE-NEXT: cmpw 4, 6 1645 ; PPC64LE-NEXT: bne 0, .LBB97_4 1646 ; PPC64LE-NEXT: # %bb.2: 1647 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1648 ; PPC64LE-NEXT: bne 0, .LBB97_1 1649 ; PPC64LE-NEXT: # %bb.3: 1650 ; PPC64LE-NEXT: lwsync 1651 ; PPC64LE-NEXT: blr 1652 ; PPC64LE-NEXT: .LBB97_4: 1653 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1654 ; PPC64LE-NEXT: lwsync 1655 ; PPC64LE-NEXT: blr 1656 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic 1657 ret void 1658 } 1659 1660 define void @test98(i16* %ptr, i16 %cmp, i16 %val) { 1661 ; PPC64LE-LABEL: test98: 1662 ; PPC64LE: # %bb.0: 1663 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1664 ; PPC64LE-NEXT: sync 1665 ; PPC64LE-NEXT: .LBB98_1: 1666 ; PPC64LE-NEXT: lharx 6, 0, 3 1667 ; PPC64LE-NEXT: cmpw 4, 6 1668 ; PPC64LE-NEXT: bne 0, .LBB98_4 1669 ; PPC64LE-NEXT: # %bb.2: 1670 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1671 ; PPC64LE-NEXT: bne 0, .LBB98_1 1672 ; PPC64LE-NEXT: # %bb.3: 1673 ; PPC64LE-NEXT: lwsync 1674 ; PPC64LE-NEXT: blr 1675 ; PPC64LE-NEXT: .LBB98_4: 1676 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1677 ; PPC64LE-NEXT: lwsync 1678 ; PPC64LE-NEXT: blr 1679 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire 1680 ret void 1681 } 1682 1683 define void @test99(i16* %ptr, i16 %cmp, i16 %val) { 1684 ; PPC64LE-LABEL: test99: 1685 ; PPC64LE: # %bb.0: 1686 ; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 1687 ; PPC64LE-NEXT: sync 1688 ; PPC64LE-NEXT: .LBB99_1: 1689 ; PPC64LE-NEXT: lharx 6, 0, 3 1690 ; PPC64LE-NEXT: cmpw 4, 6 1691 ; PPC64LE-NEXT: bne 0, .LBB99_4 1692 ; PPC64LE-NEXT: # %bb.2: 1693 ; PPC64LE-NEXT: sthcx. 5, 0, 3 1694 ; PPC64LE-NEXT: bne 0, .LBB99_1 1695 ; PPC64LE-NEXT: # %bb.3: 1696 ; PPC64LE-NEXT: lwsync 1697 ; PPC64LE-NEXT: blr 1698 ; PPC64LE-NEXT: .LBB99_4: 1699 ; PPC64LE-NEXT: sthcx. 6, 0, 3 1700 ; PPC64LE-NEXT: lwsync 1701 ; PPC64LE-NEXT: blr 1702 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst seq_cst 1703 ret void 1704 } 1705 1706 define void @test100(i32* %ptr, i32 %cmp, i32 %val) { 1707 ; PPC64LE-LABEL: test100: 1708 ; PPC64LE: # %bb.0: 1709 ; PPC64LE-NEXT: b .LBB100_2 1710 ; PPC64LE-NEXT: .p2align 5 1711 ; PPC64LE-NEXT: .LBB100_1: 1712 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1713 ; PPC64LE-NEXT: beqlr 0 1714 ; PPC64LE-NEXT: .LBB100_2: 1715 ; PPC64LE-NEXT: lwarx 6, 0, 3 1716 ; PPC64LE-NEXT: cmpw 4, 6 1717 ; PPC64LE-NEXT: beq 0, .LBB100_1 1718 ; PPC64LE-NEXT: # %bb.3: 1719 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1720 ; PPC64LE-NEXT: blr 1721 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic 1722 ret void 1723 } 1724 1725 define void @test101(i32* %ptr, i32 %cmp, i32 %val) { 1726 ; PPC64LE-LABEL: test101: 1727 ; PPC64LE: # %bb.0: 1728 ; PPC64LE-NEXT: .LBB101_1: 1729 ; PPC64LE-NEXT: lwarx 6, 0, 3 1730 ; PPC64LE-NEXT: cmpw 4, 6 1731 ; PPC64LE-NEXT: bne 0, .LBB101_4 1732 ; PPC64LE-NEXT: # %bb.2: 1733 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1734 ; PPC64LE-NEXT: bne 0, .LBB101_1 1735 ; PPC64LE-NEXT: # %bb.3: 1736 ; PPC64LE-NEXT: lwsync 1737 ; PPC64LE-NEXT: blr 1738 ; PPC64LE-NEXT: .LBB101_4: 1739 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1740 ; PPC64LE-NEXT: lwsync 1741 ; PPC64LE-NEXT: blr 1742 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire monotonic 1743 ret void 1744 } 1745 1746 define void @test102(i32* %ptr, i32 %cmp, i32 %val) { 1747 ; PPC64LE-LABEL: test102: 1748 ; PPC64LE: # %bb.0: 1749 ; PPC64LE-NEXT: .LBB102_1: 1750 ; PPC64LE-NEXT: lwarx 6, 0, 3 1751 ; PPC64LE-NEXT: cmpw 4, 6 1752 ; PPC64LE-NEXT: bne 0, .LBB102_4 1753 ; PPC64LE-NEXT: # %bb.2: 1754 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1755 ; PPC64LE-NEXT: bne 0, .LBB102_1 1756 ; PPC64LE-NEXT: # %bb.3: 1757 ; PPC64LE-NEXT: lwsync 1758 ; PPC64LE-NEXT: blr 1759 ; PPC64LE-NEXT: .LBB102_4: 1760 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1761 ; PPC64LE-NEXT: lwsync 1762 ; PPC64LE-NEXT: blr 1763 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire acquire 1764 ret void 1765 } 1766 1767 define void @test103(i32* %ptr, i32 %cmp, i32 %val) { 1768 ; PPC64LE-LABEL: test103: 1769 ; PPC64LE: # %bb.0: 1770 ; PPC64LE-NEXT: lwsync 1771 ; PPC64LE-NEXT: b .LBB103_2 1772 ; PPC64LE-NEXT: .p2align 5 1773 ; PPC64LE-NEXT: .LBB103_1: 1774 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1775 ; PPC64LE-NEXT: beqlr 0 1776 ; PPC64LE-NEXT: .LBB103_2: 1777 ; PPC64LE-NEXT: lwarx 6, 0, 3 1778 ; PPC64LE-NEXT: cmpw 4, 6 1779 ; PPC64LE-NEXT: beq 0, .LBB103_1 1780 ; PPC64LE-NEXT: # %bb.3: 1781 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1782 ; PPC64LE-NEXT: blr 1783 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic 1784 ret void 1785 } 1786 1787 define void @test104(i32* %ptr, i32 %cmp, i32 %val) { 1788 ; PPC64LE-LABEL: test104: 1789 ; PPC64LE: # %bb.0: 1790 ; PPC64LE-NEXT: lwsync 1791 ; PPC64LE-NEXT: b .LBB104_2 1792 ; PPC64LE-NEXT: .p2align 5 1793 ; PPC64LE-NEXT: .LBB104_1: 1794 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1795 ; PPC64LE-NEXT: beqlr 0 1796 ; PPC64LE-NEXT: .LBB104_2: 1797 ; PPC64LE-NEXT: lwarx 6, 0, 3 1798 ; PPC64LE-NEXT: cmpw 4, 6 1799 ; PPC64LE-NEXT: beq 0, .LBB104_1 1800 ; PPC64LE-NEXT: # %bb.3: 1801 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1802 ; PPC64LE-NEXT: blr 1803 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire 1804 ret void 1805 } 1806 1807 define void @test105(i32* %ptr, i32 %cmp, i32 %val) { 1808 ; PPC64LE-LABEL: test105: 1809 ; PPC64LE: # %bb.0: 1810 ; PPC64LE-NEXT: lwsync 1811 ; PPC64LE-NEXT: .LBB105_1: 1812 ; PPC64LE-NEXT: lwarx 6, 0, 3 1813 ; PPC64LE-NEXT: cmpw 4, 6 1814 ; PPC64LE-NEXT: bne 0, .LBB105_4 1815 ; PPC64LE-NEXT: # %bb.2: 1816 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1817 ; PPC64LE-NEXT: bne 0, .LBB105_1 1818 ; PPC64LE-NEXT: # %bb.3: 1819 ; PPC64LE-NEXT: lwsync 1820 ; PPC64LE-NEXT: blr 1821 ; PPC64LE-NEXT: .LBB105_4: 1822 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1823 ; PPC64LE-NEXT: lwsync 1824 ; PPC64LE-NEXT: blr 1825 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel monotonic 1826 ret void 1827 } 1828 1829 define void @test106(i32* %ptr, i32 %cmp, i32 %val) { 1830 ; PPC64LE-LABEL: test106: 1831 ; PPC64LE: # %bb.0: 1832 ; PPC64LE-NEXT: lwsync 1833 ; PPC64LE-NEXT: .LBB106_1: 1834 ; PPC64LE-NEXT: lwarx 6, 0, 3 1835 ; PPC64LE-NEXT: cmpw 4, 6 1836 ; PPC64LE-NEXT: bne 0, .LBB106_4 1837 ; PPC64LE-NEXT: # %bb.2: 1838 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1839 ; PPC64LE-NEXT: bne 0, .LBB106_1 1840 ; PPC64LE-NEXT: # %bb.3: 1841 ; PPC64LE-NEXT: lwsync 1842 ; PPC64LE-NEXT: blr 1843 ; PPC64LE-NEXT: .LBB106_4: 1844 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1845 ; PPC64LE-NEXT: lwsync 1846 ; PPC64LE-NEXT: blr 1847 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel acquire 1848 ret void 1849 } 1850 1851 define void @test107(i32* %ptr, i32 %cmp, i32 %val) { 1852 ; PPC64LE-LABEL: test107: 1853 ; PPC64LE: # %bb.0: 1854 ; PPC64LE-NEXT: sync 1855 ; PPC64LE-NEXT: .LBB107_1: 1856 ; PPC64LE-NEXT: lwarx 6, 0, 3 1857 ; PPC64LE-NEXT: cmpw 4, 6 1858 ; PPC64LE-NEXT: bne 0, .LBB107_4 1859 ; PPC64LE-NEXT: # %bb.2: 1860 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1861 ; PPC64LE-NEXT: bne 0, .LBB107_1 1862 ; PPC64LE-NEXT: # %bb.3: 1863 ; PPC64LE-NEXT: lwsync 1864 ; PPC64LE-NEXT: blr 1865 ; PPC64LE-NEXT: .LBB107_4: 1866 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1867 ; PPC64LE-NEXT: lwsync 1868 ; PPC64LE-NEXT: blr 1869 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst monotonic 1870 ret void 1871 } 1872 1873 define void @test108(i32* %ptr, i32 %cmp, i32 %val) { 1874 ; PPC64LE-LABEL: test108: 1875 ; PPC64LE: # %bb.0: 1876 ; PPC64LE-NEXT: sync 1877 ; PPC64LE-NEXT: .LBB108_1: 1878 ; PPC64LE-NEXT: lwarx 6, 0, 3 1879 ; PPC64LE-NEXT: cmpw 4, 6 1880 ; PPC64LE-NEXT: bne 0, .LBB108_4 1881 ; PPC64LE-NEXT: # %bb.2: 1882 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1883 ; PPC64LE-NEXT: bne 0, .LBB108_1 1884 ; PPC64LE-NEXT: # %bb.3: 1885 ; PPC64LE-NEXT: lwsync 1886 ; PPC64LE-NEXT: blr 1887 ; PPC64LE-NEXT: .LBB108_4: 1888 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1889 ; PPC64LE-NEXT: lwsync 1890 ; PPC64LE-NEXT: blr 1891 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst acquire 1892 ret void 1893 } 1894 1895 define void @test109(i32* %ptr, i32 %cmp, i32 %val) { 1896 ; PPC64LE-LABEL: test109: 1897 ; PPC64LE: # %bb.0: 1898 ; PPC64LE-NEXT: sync 1899 ; PPC64LE-NEXT: .LBB109_1: 1900 ; PPC64LE-NEXT: lwarx 6, 0, 3 1901 ; PPC64LE-NEXT: cmpw 4, 6 1902 ; PPC64LE-NEXT: bne 0, .LBB109_4 1903 ; PPC64LE-NEXT: # %bb.2: 1904 ; PPC64LE-NEXT: stwcx. 5, 0, 3 1905 ; PPC64LE-NEXT: bne 0, .LBB109_1 1906 ; PPC64LE-NEXT: # %bb.3: 1907 ; PPC64LE-NEXT: lwsync 1908 ; PPC64LE-NEXT: blr 1909 ; PPC64LE-NEXT: .LBB109_4: 1910 ; PPC64LE-NEXT: stwcx. 6, 0, 3 1911 ; PPC64LE-NEXT: lwsync 1912 ; PPC64LE-NEXT: blr 1913 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst seq_cst 1914 ret void 1915 } 1916 1917 define void @test110(i64* %ptr, i64 %cmp, i64 %val) { 1918 ; PPC64LE-LABEL: test110: 1919 ; PPC64LE: # %bb.0: 1920 ; PPC64LE-NEXT: b .LBB110_2 1921 ; PPC64LE-NEXT: .p2align 5 1922 ; PPC64LE-NEXT: .LBB110_1: 1923 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1924 ; PPC64LE-NEXT: beqlr 0 1925 ; PPC64LE-NEXT: .LBB110_2: 1926 ; PPC64LE-NEXT: ldarx 6, 0, 3 1927 ; PPC64LE-NEXT: cmpd 4, 6 1928 ; PPC64LE-NEXT: beq 0, .LBB110_1 1929 ; PPC64LE-NEXT: # %bb.3: 1930 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1931 ; PPC64LE-NEXT: blr 1932 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic 1933 ret void 1934 } 1935 1936 define void @test111(i64* %ptr, i64 %cmp, i64 %val) { 1937 ; PPC64LE-LABEL: test111: 1938 ; PPC64LE: # %bb.0: 1939 ; PPC64LE-NEXT: .LBB111_1: 1940 ; PPC64LE-NEXT: ldarx 6, 0, 3 1941 ; PPC64LE-NEXT: cmpd 4, 6 1942 ; PPC64LE-NEXT: bne 0, .LBB111_4 1943 ; PPC64LE-NEXT: # %bb.2: 1944 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1945 ; PPC64LE-NEXT: bne 0, .LBB111_1 1946 ; PPC64LE-NEXT: # %bb.3: 1947 ; PPC64LE-NEXT: lwsync 1948 ; PPC64LE-NEXT: blr 1949 ; PPC64LE-NEXT: .LBB111_4: 1950 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1951 ; PPC64LE-NEXT: lwsync 1952 ; PPC64LE-NEXT: blr 1953 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire monotonic 1954 ret void 1955 } 1956 1957 define void @test112(i64* %ptr, i64 %cmp, i64 %val) { 1958 ; PPC64LE-LABEL: test112: 1959 ; PPC64LE: # %bb.0: 1960 ; PPC64LE-NEXT: .LBB112_1: 1961 ; PPC64LE-NEXT: ldarx 6, 0, 3 1962 ; PPC64LE-NEXT: cmpd 4, 6 1963 ; PPC64LE-NEXT: bne 0, .LBB112_4 1964 ; PPC64LE-NEXT: # %bb.2: 1965 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1966 ; PPC64LE-NEXT: bne 0, .LBB112_1 1967 ; PPC64LE-NEXT: # %bb.3: 1968 ; PPC64LE-NEXT: lwsync 1969 ; PPC64LE-NEXT: blr 1970 ; PPC64LE-NEXT: .LBB112_4: 1971 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1972 ; PPC64LE-NEXT: lwsync 1973 ; PPC64LE-NEXT: blr 1974 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire acquire 1975 ret void 1976 } 1977 1978 define void @test113(i64* %ptr, i64 %cmp, i64 %val) { 1979 ; PPC64LE-LABEL: test113: 1980 ; PPC64LE: # %bb.0: 1981 ; PPC64LE-NEXT: lwsync 1982 ; PPC64LE-NEXT: b .LBB113_2 1983 ; PPC64LE-NEXT: .p2align 5 1984 ; PPC64LE-NEXT: .LBB113_1: 1985 ; PPC64LE-NEXT: stdcx. 5, 0, 3 1986 ; PPC64LE-NEXT: beqlr 0 1987 ; PPC64LE-NEXT: .LBB113_2: 1988 ; PPC64LE-NEXT: ldarx 6, 0, 3 1989 ; PPC64LE-NEXT: cmpd 4, 6 1990 ; PPC64LE-NEXT: beq 0, .LBB113_1 1991 ; PPC64LE-NEXT: # %bb.3: 1992 ; PPC64LE-NEXT: stdcx. 6, 0, 3 1993 ; PPC64LE-NEXT: blr 1994 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic 1995 ret void 1996 } 1997 1998 define void @test114(i64* %ptr, i64 %cmp, i64 %val) { 1999 ; PPC64LE-LABEL: test114: 2000 ; PPC64LE: # %bb.0: 2001 ; PPC64LE-NEXT: lwsync 2002 ; PPC64LE-NEXT: b .LBB114_2 2003 ; PPC64LE-NEXT: .p2align 5 2004 ; PPC64LE-NEXT: .LBB114_1: 2005 ; PPC64LE-NEXT: stdcx. 5, 0, 3 2006 ; PPC64LE-NEXT: beqlr 0 2007 ; PPC64LE-NEXT: .LBB114_2: 2008 ; PPC64LE-NEXT: ldarx 6, 0, 3 2009 ; PPC64LE-NEXT: cmpd 4, 6 2010 ; PPC64LE-NEXT: beq 0, .LBB114_1 2011 ; PPC64LE-NEXT: # %bb.3: 2012 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2013 ; PPC64LE-NEXT: blr 2014 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire 2015 ret void 2016 } 2017 2018 define void @test115(i64* %ptr, i64 %cmp, i64 %val) { 2019 ; PPC64LE-LABEL: test115: 2020 ; PPC64LE: # %bb.0: 2021 ; PPC64LE-NEXT: lwsync 2022 ; PPC64LE-NEXT: .LBB115_1: 2023 ; PPC64LE-NEXT: ldarx 6, 0, 3 2024 ; PPC64LE-NEXT: cmpd 4, 6 2025 ; PPC64LE-NEXT: bne 0, .LBB115_4 2026 ; PPC64LE-NEXT: # %bb.2: 2027 ; PPC64LE-NEXT: stdcx. 5, 0, 3 2028 ; PPC64LE-NEXT: bne 0, .LBB115_1 2029 ; PPC64LE-NEXT: # %bb.3: 2030 ; PPC64LE-NEXT: lwsync 2031 ; PPC64LE-NEXT: blr 2032 ; PPC64LE-NEXT: .LBB115_4: 2033 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2034 ; PPC64LE-NEXT: lwsync 2035 ; PPC64LE-NEXT: blr 2036 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel monotonic 2037 ret void 2038 } 2039 2040 define void @test116(i64* %ptr, i64 %cmp, i64 %val) { 2041 ; PPC64LE-LABEL: test116: 2042 ; PPC64LE: # %bb.0: 2043 ; PPC64LE-NEXT: lwsync 2044 ; PPC64LE-NEXT: .LBB116_1: 2045 ; PPC64LE-NEXT: ldarx 6, 0, 3 2046 ; PPC64LE-NEXT: cmpd 4, 6 2047 ; PPC64LE-NEXT: bne 0, .LBB116_4 2048 ; PPC64LE-NEXT: # %bb.2: 2049 ; PPC64LE-NEXT: stdcx. 5, 0, 3 2050 ; PPC64LE-NEXT: bne 0, .LBB116_1 2051 ; PPC64LE-NEXT: # %bb.3: 2052 ; PPC64LE-NEXT: lwsync 2053 ; PPC64LE-NEXT: blr 2054 ; PPC64LE-NEXT: .LBB116_4: 2055 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2056 ; PPC64LE-NEXT: lwsync 2057 ; PPC64LE-NEXT: blr 2058 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel acquire 2059 ret void 2060 } 2061 2062 define void @test117(i64* %ptr, i64 %cmp, i64 %val) { 2063 ; PPC64LE-LABEL: test117: 2064 ; PPC64LE: # %bb.0: 2065 ; PPC64LE-NEXT: sync 2066 ; PPC64LE-NEXT: .LBB117_1: 2067 ; PPC64LE-NEXT: ldarx 6, 0, 3 2068 ; PPC64LE-NEXT: cmpd 4, 6 2069 ; PPC64LE-NEXT: bne 0, .LBB117_4 2070 ; PPC64LE-NEXT: # %bb.2: 2071 ; PPC64LE-NEXT: stdcx. 5, 0, 3 2072 ; PPC64LE-NEXT: bne 0, .LBB117_1 2073 ; PPC64LE-NEXT: # %bb.3: 2074 ; PPC64LE-NEXT: lwsync 2075 ; PPC64LE-NEXT: blr 2076 ; PPC64LE-NEXT: .LBB117_4: 2077 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2078 ; PPC64LE-NEXT: lwsync 2079 ; PPC64LE-NEXT: blr 2080 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst monotonic 2081 ret void 2082 } 2083 2084 define void @test118(i64* %ptr, i64 %cmp, i64 %val) { 2085 ; PPC64LE-LABEL: test118: 2086 ; PPC64LE: # %bb.0: 2087 ; PPC64LE-NEXT: sync 2088 ; PPC64LE-NEXT: .LBB118_1: 2089 ; PPC64LE-NEXT: ldarx 6, 0, 3 2090 ; PPC64LE-NEXT: cmpd 4, 6 2091 ; PPC64LE-NEXT: bne 0, .LBB118_4 2092 ; PPC64LE-NEXT: # %bb.2: 2093 ; PPC64LE-NEXT: stdcx. 5, 0, 3 2094 ; PPC64LE-NEXT: bne 0, .LBB118_1 2095 ; PPC64LE-NEXT: # %bb.3: 2096 ; PPC64LE-NEXT: lwsync 2097 ; PPC64LE-NEXT: blr 2098 ; PPC64LE-NEXT: .LBB118_4: 2099 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2100 ; PPC64LE-NEXT: lwsync 2101 ; PPC64LE-NEXT: blr 2102 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst acquire 2103 ret void 2104 } 2105 2106 define void @test119(i64* %ptr, i64 %cmp, i64 %val) { 2107 ; PPC64LE-LABEL: test119: 2108 ; PPC64LE: # %bb.0: 2109 ; PPC64LE-NEXT: sync 2110 ; PPC64LE-NEXT: .LBB119_1: 2111 ; PPC64LE-NEXT: ldarx 6, 0, 3 2112 ; PPC64LE-NEXT: cmpd 4, 6 2113 ; PPC64LE-NEXT: bne 0, .LBB119_4 2114 ; PPC64LE-NEXT: # %bb.2: 2115 ; PPC64LE-NEXT: stdcx. 5, 0, 3 2116 ; PPC64LE-NEXT: bne 0, .LBB119_1 2117 ; PPC64LE-NEXT: # %bb.3: 2118 ; PPC64LE-NEXT: lwsync 2119 ; PPC64LE-NEXT: blr 2120 ; PPC64LE-NEXT: .LBB119_4: 2121 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2122 ; PPC64LE-NEXT: lwsync 2123 ; PPC64LE-NEXT: blr 2124 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst seq_cst 2125 ret void 2126 } 2127 2128 define i8 @test120(i8* %ptr, i8 %val) { 2129 ; PPC64LE-LABEL: test120: 2130 ; PPC64LE: # %bb.0: 2131 ; PPC64LE-NEXT: .LBB120_1: 2132 ; PPC64LE-NEXT: lbarx 5, 0, 3 2133 ; PPC64LE-NEXT: stbcx. 4, 0, 3 2134 ; PPC64LE-NEXT: bne 0, .LBB120_1 2135 ; PPC64LE-NEXT: # %bb.2: 2136 ; PPC64LE-NEXT: mr 3, 5 2137 ; PPC64LE-NEXT: blr 2138 %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic 2139 ret i8 %ret 2140 } 2141 2142 define i8 @test121(i8* %ptr, i8 %val) { 2143 ; PPC64LE-LABEL: test121: 2144 ; PPC64LE: # %bb.0: 2145 ; PPC64LE-NEXT: mr 5, 3 2146 ; PPC64LE-NEXT: .LBB121_1: 2147 ; PPC64LE-NEXT: lbarx 3, 0, 5 2148 ; PPC64LE-NEXT: stbcx. 4, 0, 5 2149 ; PPC64LE-NEXT: bne 0, .LBB121_1 2150 ; PPC64LE-NEXT: # %bb.2: 2151 ; PPC64LE-NEXT: lwsync 2152 ; PPC64LE-NEXT: blr 2153 %ret = atomicrmw xchg i8* %ptr, i8 %val acquire 2154 ret i8 %ret 2155 } 2156 2157 define i8 @test122(i8* %ptr, i8 %val) { 2158 ; PPC64LE-LABEL: test122: 2159 ; PPC64LE: # %bb.0: 2160 ; PPC64LE-NEXT: lwsync 2161 ; PPC64LE-NEXT: .LBB122_1: 2162 ; PPC64LE-NEXT: lbarx 5, 0, 3 2163 ; PPC64LE-NEXT: stbcx. 4, 0, 3 2164 ; PPC64LE-NEXT: bne 0, .LBB122_1 2165 ; PPC64LE-NEXT: # %bb.2: 2166 ; PPC64LE-NEXT: mr 3, 5 2167 ; PPC64LE-NEXT: blr 2168 %ret = atomicrmw xchg i8* %ptr, i8 %val release 2169 ret i8 %ret 2170 } 2171 2172 define i8 @test123(i8* %ptr, i8 %val) { 2173 ; PPC64LE-LABEL: test123: 2174 ; PPC64LE: # %bb.0: 2175 ; PPC64LE-NEXT: lwsync 2176 ; PPC64LE-NEXT: .LBB123_1: 2177 ; PPC64LE-NEXT: lbarx 5, 0, 3 2178 ; PPC64LE-NEXT: stbcx. 4, 0, 3 2179 ; PPC64LE-NEXT: bne 0, .LBB123_1 2180 ; PPC64LE-NEXT: # %bb.2: 2181 ; PPC64LE-NEXT: mr 3, 5 2182 ; PPC64LE-NEXT: lwsync 2183 ; PPC64LE-NEXT: blr 2184 %ret = atomicrmw xchg i8* %ptr, i8 %val acq_rel 2185 ret i8 %ret 2186 } 2187 2188 define i8 @test124(i8* %ptr, i8 %val) { 2189 ; PPC64LE-LABEL: test124: 2190 ; PPC64LE: # %bb.0: 2191 ; PPC64LE-NEXT: sync 2192 ; PPC64LE-NEXT: .LBB124_1: 2193 ; PPC64LE-NEXT: lbarx 5, 0, 3 2194 ; PPC64LE-NEXT: stbcx. 4, 0, 3 2195 ; PPC64LE-NEXT: bne 0, .LBB124_1 2196 ; PPC64LE-NEXT: # %bb.2: 2197 ; PPC64LE-NEXT: mr 3, 5 2198 ; PPC64LE-NEXT: lwsync 2199 ; PPC64LE-NEXT: blr 2200 %ret = atomicrmw xchg i8* %ptr, i8 %val seq_cst 2201 ret i8 %ret 2202 } 2203 2204 define i16 @test125(i16* %ptr, i16 %val) { 2205 ; PPC64LE-LABEL: test125: 2206 ; PPC64LE: # %bb.0: 2207 ; PPC64LE-NEXT: .LBB125_1: 2208 ; PPC64LE-NEXT: lharx 5, 0, 3 2209 ; PPC64LE-NEXT: sthcx. 4, 0, 3 2210 ; PPC64LE-NEXT: bne 0, .LBB125_1 2211 ; PPC64LE-NEXT: # %bb.2: 2212 ; PPC64LE-NEXT: mr 3, 5 2213 ; PPC64LE-NEXT: blr 2214 %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic 2215 ret i16 %ret 2216 } 2217 2218 define i16 @test126(i16* %ptr, i16 %val) { 2219 ; PPC64LE-LABEL: test126: 2220 ; PPC64LE: # %bb.0: 2221 ; PPC64LE-NEXT: mr 5, 3 2222 ; PPC64LE-NEXT: .LBB126_1: 2223 ; PPC64LE-NEXT: lharx 3, 0, 5 2224 ; PPC64LE-NEXT: sthcx. 4, 0, 5 2225 ; PPC64LE-NEXT: bne 0, .LBB126_1 2226 ; PPC64LE-NEXT: # %bb.2: 2227 ; PPC64LE-NEXT: lwsync 2228 ; PPC64LE-NEXT: blr 2229 %ret = atomicrmw xchg i16* %ptr, i16 %val acquire 2230 ret i16 %ret 2231 } 2232 2233 define i16 @test127(i16* %ptr, i16 %val) { 2234 ; PPC64LE-LABEL: test127: 2235 ; PPC64LE: # %bb.0: 2236 ; PPC64LE-NEXT: lwsync 2237 ; PPC64LE-NEXT: .LBB127_1: 2238 ; PPC64LE-NEXT: lharx 5, 0, 3 2239 ; PPC64LE-NEXT: sthcx. 4, 0, 3 2240 ; PPC64LE-NEXT: bne 0, .LBB127_1 2241 ; PPC64LE-NEXT: # %bb.2: 2242 ; PPC64LE-NEXT: mr 3, 5 2243 ; PPC64LE-NEXT: blr 2244 %ret = atomicrmw xchg i16* %ptr, i16 %val release 2245 ret i16 %ret 2246 } 2247 2248 define i16 @test128(i16* %ptr, i16 %val) { 2249 ; PPC64LE-LABEL: test128: 2250 ; PPC64LE: # %bb.0: 2251 ; PPC64LE-NEXT: lwsync 2252 ; PPC64LE-NEXT: .LBB128_1: 2253 ; PPC64LE-NEXT: lharx 5, 0, 3 2254 ; PPC64LE-NEXT: sthcx. 4, 0, 3 2255 ; PPC64LE-NEXT: bne 0, .LBB128_1 2256 ; PPC64LE-NEXT: # %bb.2: 2257 ; PPC64LE-NEXT: mr 3, 5 2258 ; PPC64LE-NEXT: lwsync 2259 ; PPC64LE-NEXT: blr 2260 %ret = atomicrmw xchg i16* %ptr, i16 %val acq_rel 2261 ret i16 %ret 2262 } 2263 2264 define i16 @test129(i16* %ptr, i16 %val) { 2265 ; PPC64LE-LABEL: test129: 2266 ; PPC64LE: # %bb.0: 2267 ; PPC64LE-NEXT: sync 2268 ; PPC64LE-NEXT: .LBB129_1: 2269 ; PPC64LE-NEXT: lharx 5, 0, 3 2270 ; PPC64LE-NEXT: sthcx. 4, 0, 3 2271 ; PPC64LE-NEXT: bne 0, .LBB129_1 2272 ; PPC64LE-NEXT: # %bb.2: 2273 ; PPC64LE-NEXT: mr 3, 5 2274 ; PPC64LE-NEXT: lwsync 2275 ; PPC64LE-NEXT: blr 2276 %ret = atomicrmw xchg i16* %ptr, i16 %val seq_cst 2277 ret i16 %ret 2278 } 2279 2280 define i32 @test130(i32* %ptr, i32 %val) { 2281 ; PPC64LE-LABEL: test130: 2282 ; PPC64LE: # %bb.0: 2283 ; PPC64LE-NEXT: .LBB130_1: 2284 ; PPC64LE-NEXT: lwarx 5, 0, 3 2285 ; PPC64LE-NEXT: stwcx. 4, 0, 3 2286 ; PPC64LE-NEXT: bne 0, .LBB130_1 2287 ; PPC64LE-NEXT: # %bb.2: 2288 ; PPC64LE-NEXT: mr 3, 5 2289 ; PPC64LE-NEXT: blr 2290 %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic 2291 ret i32 %ret 2292 } 2293 2294 define i32 @test131(i32* %ptr, i32 %val) { 2295 ; PPC64LE-LABEL: test131: 2296 ; PPC64LE: # %bb.0: 2297 ; PPC64LE-NEXT: mr 5, 3 2298 ; PPC64LE-NEXT: .LBB131_1: 2299 ; PPC64LE-NEXT: lwarx 3, 0, 5 2300 ; PPC64LE-NEXT: stwcx. 4, 0, 5 2301 ; PPC64LE-NEXT: bne 0, .LBB131_1 2302 ; PPC64LE-NEXT: # %bb.2: 2303 ; PPC64LE-NEXT: lwsync 2304 ; PPC64LE-NEXT: blr 2305 %ret = atomicrmw xchg i32* %ptr, i32 %val acquire 2306 ret i32 %ret 2307 } 2308 2309 define i32 @test132(i32* %ptr, i32 %val) { 2310 ; PPC64LE-LABEL: test132: 2311 ; PPC64LE: # %bb.0: 2312 ; PPC64LE-NEXT: lwsync 2313 ; PPC64LE-NEXT: .LBB132_1: 2314 ; PPC64LE-NEXT: lwarx 5, 0, 3 2315 ; PPC64LE-NEXT: stwcx. 4, 0, 3 2316 ; PPC64LE-NEXT: bne 0, .LBB132_1 2317 ; PPC64LE-NEXT: # %bb.2: 2318 ; PPC64LE-NEXT: mr 3, 5 2319 ; PPC64LE-NEXT: blr 2320 %ret = atomicrmw xchg i32* %ptr, i32 %val release 2321 ret i32 %ret 2322 } 2323 2324 define i32 @test133(i32* %ptr, i32 %val) { 2325 ; PPC64LE-LABEL: test133: 2326 ; PPC64LE: # %bb.0: 2327 ; PPC64LE-NEXT: lwsync 2328 ; PPC64LE-NEXT: .LBB133_1: 2329 ; PPC64LE-NEXT: lwarx 5, 0, 3 2330 ; PPC64LE-NEXT: stwcx. 4, 0, 3 2331 ; PPC64LE-NEXT: bne 0, .LBB133_1 2332 ; PPC64LE-NEXT: # %bb.2: 2333 ; PPC64LE-NEXT: mr 3, 5 2334 ; PPC64LE-NEXT: lwsync 2335 ; PPC64LE-NEXT: blr 2336 %ret = atomicrmw xchg i32* %ptr, i32 %val acq_rel 2337 ret i32 %ret 2338 } 2339 2340 define i32 @test134(i32* %ptr, i32 %val) { 2341 ; PPC64LE-LABEL: test134: 2342 ; PPC64LE: # %bb.0: 2343 ; PPC64LE-NEXT: sync 2344 ; PPC64LE-NEXT: .LBB134_1: 2345 ; PPC64LE-NEXT: lwarx 5, 0, 3 2346 ; PPC64LE-NEXT: stwcx. 4, 0, 3 2347 ; PPC64LE-NEXT: bne 0, .LBB134_1 2348 ; PPC64LE-NEXT: # %bb.2: 2349 ; PPC64LE-NEXT: mr 3, 5 2350 ; PPC64LE-NEXT: lwsync 2351 ; PPC64LE-NEXT: blr 2352 %ret = atomicrmw xchg i32* %ptr, i32 %val seq_cst 2353 ret i32 %ret 2354 } 2355 2356 define i64 @test135(i64* %ptr, i64 %val) { 2357 ; PPC64LE-LABEL: test135: 2358 ; PPC64LE: # %bb.0: 2359 ; PPC64LE-NEXT: .LBB135_1: 2360 ; PPC64LE-NEXT: ldarx 5, 0, 3 2361 ; PPC64LE-NEXT: stdcx. 4, 0, 3 2362 ; PPC64LE-NEXT: bne 0, .LBB135_1 2363 ; PPC64LE-NEXT: # %bb.2: 2364 ; PPC64LE-NEXT: mr 3, 5 2365 ; PPC64LE-NEXT: blr 2366 %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic 2367 ret i64 %ret 2368 } 2369 2370 define i64 @test136(i64* %ptr, i64 %val) { 2371 ; PPC64LE-LABEL: test136: 2372 ; PPC64LE: # %bb.0: 2373 ; PPC64LE-NEXT: mr 5, 3 2374 ; PPC64LE-NEXT: .LBB136_1: 2375 ; PPC64LE-NEXT: ldarx 3, 0, 5 2376 ; PPC64LE-NEXT: stdcx. 4, 0, 5 2377 ; PPC64LE-NEXT: bne 0, .LBB136_1 2378 ; PPC64LE-NEXT: # %bb.2: 2379 ; PPC64LE-NEXT: lwsync 2380 ; PPC64LE-NEXT: blr 2381 %ret = atomicrmw xchg i64* %ptr, i64 %val acquire 2382 ret i64 %ret 2383 } 2384 2385 define i64 @test137(i64* %ptr, i64 %val) { 2386 ; PPC64LE-LABEL: test137: 2387 ; PPC64LE: # %bb.0: 2388 ; PPC64LE-NEXT: lwsync 2389 ; PPC64LE-NEXT: .LBB137_1: 2390 ; PPC64LE-NEXT: ldarx 5, 0, 3 2391 ; PPC64LE-NEXT: stdcx. 4, 0, 3 2392 ; PPC64LE-NEXT: bne 0, .LBB137_1 2393 ; PPC64LE-NEXT: # %bb.2: 2394 ; PPC64LE-NEXT: mr 3, 5 2395 ; PPC64LE-NEXT: blr 2396 %ret = atomicrmw xchg i64* %ptr, i64 %val release 2397 ret i64 %ret 2398 } 2399 2400 define i64 @test138(i64* %ptr, i64 %val) { 2401 ; PPC64LE-LABEL: test138: 2402 ; PPC64LE: # %bb.0: 2403 ; PPC64LE-NEXT: lwsync 2404 ; PPC64LE-NEXT: .LBB138_1: 2405 ; PPC64LE-NEXT: ldarx 5, 0, 3 2406 ; PPC64LE-NEXT: stdcx. 4, 0, 3 2407 ; PPC64LE-NEXT: bne 0, .LBB138_1 2408 ; PPC64LE-NEXT: # %bb.2: 2409 ; PPC64LE-NEXT: mr 3, 5 2410 ; PPC64LE-NEXT: lwsync 2411 ; PPC64LE-NEXT: blr 2412 %ret = atomicrmw xchg i64* %ptr, i64 %val acq_rel 2413 ret i64 %ret 2414 } 2415 2416 define i64 @test139(i64* %ptr, i64 %val) { 2417 ; PPC64LE-LABEL: test139: 2418 ; PPC64LE: # %bb.0: 2419 ; PPC64LE-NEXT: sync 2420 ; PPC64LE-NEXT: .LBB139_1: 2421 ; PPC64LE-NEXT: ldarx 5, 0, 3 2422 ; PPC64LE-NEXT: stdcx. 4, 0, 3 2423 ; PPC64LE-NEXT: bne 0, .LBB139_1 2424 ; PPC64LE-NEXT: # %bb.2: 2425 ; PPC64LE-NEXT: mr 3, 5 2426 ; PPC64LE-NEXT: lwsync 2427 ; PPC64LE-NEXT: blr 2428 %ret = atomicrmw xchg i64* %ptr, i64 %val seq_cst 2429 ret i64 %ret 2430 } 2431 2432 define i8 @test140(i8* %ptr, i8 %val) { 2433 ; PPC64LE-LABEL: test140: 2434 ; PPC64LE: # %bb.0: 2435 ; PPC64LE-NEXT: .LBB140_1: 2436 ; PPC64LE-NEXT: lbarx 5, 0, 3 2437 ; PPC64LE-NEXT: add 6, 4, 5 2438 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2439 ; PPC64LE-NEXT: bne 0, .LBB140_1 2440 ; PPC64LE-NEXT: # %bb.2: 2441 ; PPC64LE-NEXT: mr 3, 5 2442 ; PPC64LE-NEXT: blr 2443 %ret = atomicrmw add i8* %ptr, i8 %val monotonic 2444 ret i8 %ret 2445 } 2446 2447 define i8 @test141(i8* %ptr, i8 %val) { 2448 ; PPC64LE-LABEL: test141: 2449 ; PPC64LE: # %bb.0: 2450 ; PPC64LE-NEXT: mr 5, 3 2451 ; PPC64LE-NEXT: .LBB141_1: 2452 ; PPC64LE-NEXT: lbarx 3, 0, 5 2453 ; PPC64LE-NEXT: add 6, 4, 3 2454 ; PPC64LE-NEXT: stbcx. 6, 0, 5 2455 ; PPC64LE-NEXT: bne 0, .LBB141_1 2456 ; PPC64LE-NEXT: # %bb.2: 2457 ; PPC64LE-NEXT: lwsync 2458 ; PPC64LE-NEXT: blr 2459 %ret = atomicrmw add i8* %ptr, i8 %val acquire 2460 ret i8 %ret 2461 } 2462 2463 define i8 @test142(i8* %ptr, i8 %val) { 2464 ; PPC64LE-LABEL: test142: 2465 ; PPC64LE: # %bb.0: 2466 ; PPC64LE-NEXT: lwsync 2467 ; PPC64LE-NEXT: .LBB142_1: 2468 ; PPC64LE-NEXT: lbarx 5, 0, 3 2469 ; PPC64LE-NEXT: add 6, 4, 5 2470 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2471 ; PPC64LE-NEXT: bne 0, .LBB142_1 2472 ; PPC64LE-NEXT: # %bb.2: 2473 ; PPC64LE-NEXT: mr 3, 5 2474 ; PPC64LE-NEXT: blr 2475 %ret = atomicrmw add i8* %ptr, i8 %val release 2476 ret i8 %ret 2477 } 2478 2479 define i8 @test143(i8* %ptr, i8 %val) { 2480 ; PPC64LE-LABEL: test143: 2481 ; PPC64LE: # %bb.0: 2482 ; PPC64LE-NEXT: lwsync 2483 ; PPC64LE-NEXT: .LBB143_1: 2484 ; PPC64LE-NEXT: lbarx 5, 0, 3 2485 ; PPC64LE-NEXT: add 6, 4, 5 2486 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2487 ; PPC64LE-NEXT: bne 0, .LBB143_1 2488 ; PPC64LE-NEXT: # %bb.2: 2489 ; PPC64LE-NEXT: mr 3, 5 2490 ; PPC64LE-NEXT: lwsync 2491 ; PPC64LE-NEXT: blr 2492 %ret = atomicrmw add i8* %ptr, i8 %val acq_rel 2493 ret i8 %ret 2494 } 2495 2496 define i8 @test144(i8* %ptr, i8 %val) { 2497 ; PPC64LE-LABEL: test144: 2498 ; PPC64LE: # %bb.0: 2499 ; PPC64LE-NEXT: sync 2500 ; PPC64LE-NEXT: .LBB144_1: 2501 ; PPC64LE-NEXT: lbarx 5, 0, 3 2502 ; PPC64LE-NEXT: add 6, 4, 5 2503 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2504 ; PPC64LE-NEXT: bne 0, .LBB144_1 2505 ; PPC64LE-NEXT: # %bb.2: 2506 ; PPC64LE-NEXT: mr 3, 5 2507 ; PPC64LE-NEXT: lwsync 2508 ; PPC64LE-NEXT: blr 2509 %ret = atomicrmw add i8* %ptr, i8 %val seq_cst 2510 ret i8 %ret 2511 } 2512 2513 define i16 @test145(i16* %ptr, i16 %val) { 2514 ; PPC64LE-LABEL: test145: 2515 ; PPC64LE: # %bb.0: 2516 ; PPC64LE-NEXT: .LBB145_1: 2517 ; PPC64LE-NEXT: lharx 5, 0, 3 2518 ; PPC64LE-NEXT: add 6, 4, 5 2519 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2520 ; PPC64LE-NEXT: bne 0, .LBB145_1 2521 ; PPC64LE-NEXT: # %bb.2: 2522 ; PPC64LE-NEXT: mr 3, 5 2523 ; PPC64LE-NEXT: blr 2524 %ret = atomicrmw add i16* %ptr, i16 %val monotonic 2525 ret i16 %ret 2526 } 2527 2528 define i16 @test146(i16* %ptr, i16 %val) { 2529 ; PPC64LE-LABEL: test146: 2530 ; PPC64LE: # %bb.0: 2531 ; PPC64LE-NEXT: mr 5, 3 2532 ; PPC64LE-NEXT: .LBB146_1: 2533 ; PPC64LE-NEXT: lharx 3, 0, 5 2534 ; PPC64LE-NEXT: add 6, 4, 3 2535 ; PPC64LE-NEXT: sthcx. 6, 0, 5 2536 ; PPC64LE-NEXT: bne 0, .LBB146_1 2537 ; PPC64LE-NEXT: # %bb.2: 2538 ; PPC64LE-NEXT: lwsync 2539 ; PPC64LE-NEXT: blr 2540 %ret = atomicrmw add i16* %ptr, i16 %val acquire 2541 ret i16 %ret 2542 } 2543 2544 define i16 @test147(i16* %ptr, i16 %val) { 2545 ; PPC64LE-LABEL: test147: 2546 ; PPC64LE: # %bb.0: 2547 ; PPC64LE-NEXT: lwsync 2548 ; PPC64LE-NEXT: .LBB147_1: 2549 ; PPC64LE-NEXT: lharx 5, 0, 3 2550 ; PPC64LE-NEXT: add 6, 4, 5 2551 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2552 ; PPC64LE-NEXT: bne 0, .LBB147_1 2553 ; PPC64LE-NEXT: # %bb.2: 2554 ; PPC64LE-NEXT: mr 3, 5 2555 ; PPC64LE-NEXT: blr 2556 %ret = atomicrmw add i16* %ptr, i16 %val release 2557 ret i16 %ret 2558 } 2559 2560 define i16 @test148(i16* %ptr, i16 %val) { 2561 ; PPC64LE-LABEL: test148: 2562 ; PPC64LE: # %bb.0: 2563 ; PPC64LE-NEXT: lwsync 2564 ; PPC64LE-NEXT: .LBB148_1: 2565 ; PPC64LE-NEXT: lharx 5, 0, 3 2566 ; PPC64LE-NEXT: add 6, 4, 5 2567 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2568 ; PPC64LE-NEXT: bne 0, .LBB148_1 2569 ; PPC64LE-NEXT: # %bb.2: 2570 ; PPC64LE-NEXT: mr 3, 5 2571 ; PPC64LE-NEXT: lwsync 2572 ; PPC64LE-NEXT: blr 2573 %ret = atomicrmw add i16* %ptr, i16 %val acq_rel 2574 ret i16 %ret 2575 } 2576 2577 define i16 @test149(i16* %ptr, i16 %val) { 2578 ; PPC64LE-LABEL: test149: 2579 ; PPC64LE: # %bb.0: 2580 ; PPC64LE-NEXT: sync 2581 ; PPC64LE-NEXT: .LBB149_1: 2582 ; PPC64LE-NEXT: lharx 5, 0, 3 2583 ; PPC64LE-NEXT: add 6, 4, 5 2584 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2585 ; PPC64LE-NEXT: bne 0, .LBB149_1 2586 ; PPC64LE-NEXT: # %bb.2: 2587 ; PPC64LE-NEXT: mr 3, 5 2588 ; PPC64LE-NEXT: lwsync 2589 ; PPC64LE-NEXT: blr 2590 %ret = atomicrmw add i16* %ptr, i16 %val seq_cst 2591 ret i16 %ret 2592 } 2593 2594 define i32 @test150(i32* %ptr, i32 %val) { 2595 ; PPC64LE-LABEL: test150: 2596 ; PPC64LE: # %bb.0: 2597 ; PPC64LE-NEXT: .LBB150_1: 2598 ; PPC64LE-NEXT: lwarx 5, 0, 3 2599 ; PPC64LE-NEXT: add 6, 4, 5 2600 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2601 ; PPC64LE-NEXT: bne 0, .LBB150_1 2602 ; PPC64LE-NEXT: # %bb.2: 2603 ; PPC64LE-NEXT: mr 3, 5 2604 ; PPC64LE-NEXT: blr 2605 %ret = atomicrmw add i32* %ptr, i32 %val monotonic 2606 ret i32 %ret 2607 } 2608 2609 define i32 @test151(i32* %ptr, i32 %val) { 2610 ; PPC64LE-LABEL: test151: 2611 ; PPC64LE: # %bb.0: 2612 ; PPC64LE-NEXT: mr 5, 3 2613 ; PPC64LE-NEXT: .LBB151_1: 2614 ; PPC64LE-NEXT: lwarx 3, 0, 5 2615 ; PPC64LE-NEXT: add 6, 4, 3 2616 ; PPC64LE-NEXT: stwcx. 6, 0, 5 2617 ; PPC64LE-NEXT: bne 0, .LBB151_1 2618 ; PPC64LE-NEXT: # %bb.2: 2619 ; PPC64LE-NEXT: lwsync 2620 ; PPC64LE-NEXT: blr 2621 %ret = atomicrmw add i32* %ptr, i32 %val acquire 2622 ret i32 %ret 2623 } 2624 2625 define i32 @test152(i32* %ptr, i32 %val) { 2626 ; PPC64LE-LABEL: test152: 2627 ; PPC64LE: # %bb.0: 2628 ; PPC64LE-NEXT: lwsync 2629 ; PPC64LE-NEXT: .LBB152_1: 2630 ; PPC64LE-NEXT: lwarx 5, 0, 3 2631 ; PPC64LE-NEXT: add 6, 4, 5 2632 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2633 ; PPC64LE-NEXT: bne 0, .LBB152_1 2634 ; PPC64LE-NEXT: # %bb.2: 2635 ; PPC64LE-NEXT: mr 3, 5 2636 ; PPC64LE-NEXT: blr 2637 %ret = atomicrmw add i32* %ptr, i32 %val release 2638 ret i32 %ret 2639 } 2640 2641 define i32 @test153(i32* %ptr, i32 %val) { 2642 ; PPC64LE-LABEL: test153: 2643 ; PPC64LE: # %bb.0: 2644 ; PPC64LE-NEXT: lwsync 2645 ; PPC64LE-NEXT: .LBB153_1: 2646 ; PPC64LE-NEXT: lwarx 5, 0, 3 2647 ; PPC64LE-NEXT: add 6, 4, 5 2648 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2649 ; PPC64LE-NEXT: bne 0, .LBB153_1 2650 ; PPC64LE-NEXT: # %bb.2: 2651 ; PPC64LE-NEXT: mr 3, 5 2652 ; PPC64LE-NEXT: lwsync 2653 ; PPC64LE-NEXT: blr 2654 %ret = atomicrmw add i32* %ptr, i32 %val acq_rel 2655 ret i32 %ret 2656 } 2657 2658 define i32 @test154(i32* %ptr, i32 %val) { 2659 ; PPC64LE-LABEL: test154: 2660 ; PPC64LE: # %bb.0: 2661 ; PPC64LE-NEXT: sync 2662 ; PPC64LE-NEXT: .LBB154_1: 2663 ; PPC64LE-NEXT: lwarx 5, 0, 3 2664 ; PPC64LE-NEXT: add 6, 4, 5 2665 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2666 ; PPC64LE-NEXT: bne 0, .LBB154_1 2667 ; PPC64LE-NEXT: # %bb.2: 2668 ; PPC64LE-NEXT: mr 3, 5 2669 ; PPC64LE-NEXT: lwsync 2670 ; PPC64LE-NEXT: blr 2671 %ret = atomicrmw add i32* %ptr, i32 %val seq_cst 2672 ret i32 %ret 2673 } 2674 2675 define i64 @test155(i64* %ptr, i64 %val) { 2676 ; PPC64LE-LABEL: test155: 2677 ; PPC64LE: # %bb.0: 2678 ; PPC64LE-NEXT: .LBB155_1: 2679 ; PPC64LE-NEXT: ldarx 5, 0, 3 2680 ; PPC64LE-NEXT: add 6, 4, 5 2681 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2682 ; PPC64LE-NEXT: bne 0, .LBB155_1 2683 ; PPC64LE-NEXT: # %bb.2: 2684 ; PPC64LE-NEXT: mr 3, 5 2685 ; PPC64LE-NEXT: blr 2686 %ret = atomicrmw add i64* %ptr, i64 %val monotonic 2687 ret i64 %ret 2688 } 2689 2690 define i64 @test156(i64* %ptr, i64 %val) { 2691 ; PPC64LE-LABEL: test156: 2692 ; PPC64LE: # %bb.0: 2693 ; PPC64LE-NEXT: mr 5, 3 2694 ; PPC64LE-NEXT: .LBB156_1: 2695 ; PPC64LE-NEXT: ldarx 3, 0, 5 2696 ; PPC64LE-NEXT: add 6, 4, 3 2697 ; PPC64LE-NEXT: stdcx. 6, 0, 5 2698 ; PPC64LE-NEXT: bne 0, .LBB156_1 2699 ; PPC64LE-NEXT: # %bb.2: 2700 ; PPC64LE-NEXT: lwsync 2701 ; PPC64LE-NEXT: blr 2702 %ret = atomicrmw add i64* %ptr, i64 %val acquire 2703 ret i64 %ret 2704 } 2705 2706 define i64 @test157(i64* %ptr, i64 %val) { 2707 ; PPC64LE-LABEL: test157: 2708 ; PPC64LE: # %bb.0: 2709 ; PPC64LE-NEXT: lwsync 2710 ; PPC64LE-NEXT: .LBB157_1: 2711 ; PPC64LE-NEXT: ldarx 5, 0, 3 2712 ; PPC64LE-NEXT: add 6, 4, 5 2713 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2714 ; PPC64LE-NEXT: bne 0, .LBB157_1 2715 ; PPC64LE-NEXT: # %bb.2: 2716 ; PPC64LE-NEXT: mr 3, 5 2717 ; PPC64LE-NEXT: blr 2718 %ret = atomicrmw add i64* %ptr, i64 %val release 2719 ret i64 %ret 2720 } 2721 2722 define i64 @test158(i64* %ptr, i64 %val) { 2723 ; PPC64LE-LABEL: test158: 2724 ; PPC64LE: # %bb.0: 2725 ; PPC64LE-NEXT: lwsync 2726 ; PPC64LE-NEXT: .LBB158_1: 2727 ; PPC64LE-NEXT: ldarx 5, 0, 3 2728 ; PPC64LE-NEXT: add 6, 4, 5 2729 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2730 ; PPC64LE-NEXT: bne 0, .LBB158_1 2731 ; PPC64LE-NEXT: # %bb.2: 2732 ; PPC64LE-NEXT: mr 3, 5 2733 ; PPC64LE-NEXT: lwsync 2734 ; PPC64LE-NEXT: blr 2735 %ret = atomicrmw add i64* %ptr, i64 %val acq_rel 2736 ret i64 %ret 2737 } 2738 2739 define i64 @test159(i64* %ptr, i64 %val) { 2740 ; PPC64LE-LABEL: test159: 2741 ; PPC64LE: # %bb.0: 2742 ; PPC64LE-NEXT: sync 2743 ; PPC64LE-NEXT: .LBB159_1: 2744 ; PPC64LE-NEXT: ldarx 5, 0, 3 2745 ; PPC64LE-NEXT: add 6, 4, 5 2746 ; PPC64LE-NEXT: stdcx. 6, 0, 3 2747 ; PPC64LE-NEXT: bne 0, .LBB159_1 2748 ; PPC64LE-NEXT: # %bb.2: 2749 ; PPC64LE-NEXT: mr 3, 5 2750 ; PPC64LE-NEXT: lwsync 2751 ; PPC64LE-NEXT: blr 2752 %ret = atomicrmw add i64* %ptr, i64 %val seq_cst 2753 ret i64 %ret 2754 } 2755 2756 define i8 @test160(i8* %ptr, i8 %val) { 2757 ; PPC64LE-LABEL: test160: 2758 ; PPC64LE: # %bb.0: 2759 ; PPC64LE-NEXT: .LBB160_1: 2760 ; PPC64LE-NEXT: lbarx 5, 0, 3 2761 ; PPC64LE-NEXT: subf 6, 4, 5 2762 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2763 ; PPC64LE-NEXT: bne 0, .LBB160_1 2764 ; PPC64LE-NEXT: # %bb.2: 2765 ; PPC64LE-NEXT: mr 3, 5 2766 ; PPC64LE-NEXT: blr 2767 %ret = atomicrmw sub i8* %ptr, i8 %val monotonic 2768 ret i8 %ret 2769 } 2770 2771 define i8 @test161(i8* %ptr, i8 %val) { 2772 ; PPC64LE-LABEL: test161: 2773 ; PPC64LE: # %bb.0: 2774 ; PPC64LE-NEXT: mr 5, 3 2775 ; PPC64LE-NEXT: .LBB161_1: 2776 ; PPC64LE-NEXT: lbarx 3, 0, 5 2777 ; PPC64LE-NEXT: subf 6, 4, 3 2778 ; PPC64LE-NEXT: stbcx. 6, 0, 5 2779 ; PPC64LE-NEXT: bne 0, .LBB161_1 2780 ; PPC64LE-NEXT: # %bb.2: 2781 ; PPC64LE-NEXT: lwsync 2782 ; PPC64LE-NEXT: blr 2783 %ret = atomicrmw sub i8* %ptr, i8 %val acquire 2784 ret i8 %ret 2785 } 2786 2787 define i8 @test162(i8* %ptr, i8 %val) { 2788 ; PPC64LE-LABEL: test162: 2789 ; PPC64LE: # %bb.0: 2790 ; PPC64LE-NEXT: lwsync 2791 ; PPC64LE-NEXT: .LBB162_1: 2792 ; PPC64LE-NEXT: lbarx 5, 0, 3 2793 ; PPC64LE-NEXT: subf 6, 4, 5 2794 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2795 ; PPC64LE-NEXT: bne 0, .LBB162_1 2796 ; PPC64LE-NEXT: # %bb.2: 2797 ; PPC64LE-NEXT: mr 3, 5 2798 ; PPC64LE-NEXT: blr 2799 %ret = atomicrmw sub i8* %ptr, i8 %val release 2800 ret i8 %ret 2801 } 2802 2803 define i8 @test163(i8* %ptr, i8 %val) { 2804 ; PPC64LE-LABEL: test163: 2805 ; PPC64LE: # %bb.0: 2806 ; PPC64LE-NEXT: lwsync 2807 ; PPC64LE-NEXT: .LBB163_1: 2808 ; PPC64LE-NEXT: lbarx 5, 0, 3 2809 ; PPC64LE-NEXT: subf 6, 4, 5 2810 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2811 ; PPC64LE-NEXT: bne 0, .LBB163_1 2812 ; PPC64LE-NEXT: # %bb.2: 2813 ; PPC64LE-NEXT: mr 3, 5 2814 ; PPC64LE-NEXT: lwsync 2815 ; PPC64LE-NEXT: blr 2816 %ret = atomicrmw sub i8* %ptr, i8 %val acq_rel 2817 ret i8 %ret 2818 } 2819 2820 define i8 @test164(i8* %ptr, i8 %val) { 2821 ; PPC64LE-LABEL: test164: 2822 ; PPC64LE: # %bb.0: 2823 ; PPC64LE-NEXT: sync 2824 ; PPC64LE-NEXT: .LBB164_1: 2825 ; PPC64LE-NEXT: lbarx 5, 0, 3 2826 ; PPC64LE-NEXT: subf 6, 4, 5 2827 ; PPC64LE-NEXT: stbcx. 6, 0, 3 2828 ; PPC64LE-NEXT: bne 0, .LBB164_1 2829 ; PPC64LE-NEXT: # %bb.2: 2830 ; PPC64LE-NEXT: mr 3, 5 2831 ; PPC64LE-NEXT: lwsync 2832 ; PPC64LE-NEXT: blr 2833 %ret = atomicrmw sub i8* %ptr, i8 %val seq_cst 2834 ret i8 %ret 2835 } 2836 2837 define i16 @test165(i16* %ptr, i16 %val) { 2838 ; PPC64LE-LABEL: test165: 2839 ; PPC64LE: # %bb.0: 2840 ; PPC64LE-NEXT: .LBB165_1: 2841 ; PPC64LE-NEXT: lharx 5, 0, 3 2842 ; PPC64LE-NEXT: subf 6, 4, 5 2843 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2844 ; PPC64LE-NEXT: bne 0, .LBB165_1 2845 ; PPC64LE-NEXT: # %bb.2: 2846 ; PPC64LE-NEXT: mr 3, 5 2847 ; PPC64LE-NEXT: blr 2848 %ret = atomicrmw sub i16* %ptr, i16 %val monotonic 2849 ret i16 %ret 2850 } 2851 2852 define i16 @test166(i16* %ptr, i16 %val) { 2853 ; PPC64LE-LABEL: test166: 2854 ; PPC64LE: # %bb.0: 2855 ; PPC64LE-NEXT: mr 5, 3 2856 ; PPC64LE-NEXT: .LBB166_1: 2857 ; PPC64LE-NEXT: lharx 3, 0, 5 2858 ; PPC64LE-NEXT: subf 6, 4, 3 2859 ; PPC64LE-NEXT: sthcx. 6, 0, 5 2860 ; PPC64LE-NEXT: bne 0, .LBB166_1 2861 ; PPC64LE-NEXT: # %bb.2: 2862 ; PPC64LE-NEXT: lwsync 2863 ; PPC64LE-NEXT: blr 2864 %ret = atomicrmw sub i16* %ptr, i16 %val acquire 2865 ret i16 %ret 2866 } 2867 2868 define i16 @test167(i16* %ptr, i16 %val) { 2869 ; PPC64LE-LABEL: test167: 2870 ; PPC64LE: # %bb.0: 2871 ; PPC64LE-NEXT: lwsync 2872 ; PPC64LE-NEXT: .LBB167_1: 2873 ; PPC64LE-NEXT: lharx 5, 0, 3 2874 ; PPC64LE-NEXT: subf 6, 4, 5 2875 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2876 ; PPC64LE-NEXT: bne 0, .LBB167_1 2877 ; PPC64LE-NEXT: # %bb.2: 2878 ; PPC64LE-NEXT: mr 3, 5 2879 ; PPC64LE-NEXT: blr 2880 %ret = atomicrmw sub i16* %ptr, i16 %val release 2881 ret i16 %ret 2882 } 2883 2884 define i16 @test168(i16* %ptr, i16 %val) { 2885 ; PPC64LE-LABEL: test168: 2886 ; PPC64LE: # %bb.0: 2887 ; PPC64LE-NEXT: lwsync 2888 ; PPC64LE-NEXT: .LBB168_1: 2889 ; PPC64LE-NEXT: lharx 5, 0, 3 2890 ; PPC64LE-NEXT: subf 6, 4, 5 2891 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2892 ; PPC64LE-NEXT: bne 0, .LBB168_1 2893 ; PPC64LE-NEXT: # %bb.2: 2894 ; PPC64LE-NEXT: mr 3, 5 2895 ; PPC64LE-NEXT: lwsync 2896 ; PPC64LE-NEXT: blr 2897 %ret = atomicrmw sub i16* %ptr, i16 %val acq_rel 2898 ret i16 %ret 2899 } 2900 2901 define i16 @test169(i16* %ptr, i16 %val) { 2902 ; PPC64LE-LABEL: test169: 2903 ; PPC64LE: # %bb.0: 2904 ; PPC64LE-NEXT: sync 2905 ; PPC64LE-NEXT: .LBB169_1: 2906 ; PPC64LE-NEXT: lharx 5, 0, 3 2907 ; PPC64LE-NEXT: subf 6, 4, 5 2908 ; PPC64LE-NEXT: sthcx. 6, 0, 3 2909 ; PPC64LE-NEXT: bne 0, .LBB169_1 2910 ; PPC64LE-NEXT: # %bb.2: 2911 ; PPC64LE-NEXT: mr 3, 5 2912 ; PPC64LE-NEXT: lwsync 2913 ; PPC64LE-NEXT: blr 2914 %ret = atomicrmw sub i16* %ptr, i16 %val seq_cst 2915 ret i16 %ret 2916 } 2917 2918 define i32 @test170(i32* %ptr, i32 %val) { 2919 ; PPC64LE-LABEL: test170: 2920 ; PPC64LE: # %bb.0: 2921 ; PPC64LE-NEXT: .LBB170_1: 2922 ; PPC64LE-NEXT: lwarx 5, 0, 3 2923 ; PPC64LE-NEXT: subf 6, 4, 5 2924 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2925 ; PPC64LE-NEXT: bne 0, .LBB170_1 2926 ; PPC64LE-NEXT: # %bb.2: 2927 ; PPC64LE-NEXT: mr 3, 5 2928 ; PPC64LE-NEXT: blr 2929 %ret = atomicrmw sub i32* %ptr, i32 %val monotonic 2930 ret i32 %ret 2931 } 2932 2933 define i32 @test171(i32* %ptr, i32 %val) { 2934 ; PPC64LE-LABEL: test171: 2935 ; PPC64LE: # %bb.0: 2936 ; PPC64LE-NEXT: mr 5, 3 2937 ; PPC64LE-NEXT: .LBB171_1: 2938 ; PPC64LE-NEXT: lwarx 3, 0, 5 2939 ; PPC64LE-NEXT: subf 6, 4, 3 2940 ; PPC64LE-NEXT: stwcx. 6, 0, 5 2941 ; PPC64LE-NEXT: bne 0, .LBB171_1 2942 ; PPC64LE-NEXT: # %bb.2: 2943 ; PPC64LE-NEXT: lwsync 2944 ; PPC64LE-NEXT: blr 2945 %ret = atomicrmw sub i32* %ptr, i32 %val acquire 2946 ret i32 %ret 2947 } 2948 2949 define i32 @test172(i32* %ptr, i32 %val) { 2950 ; PPC64LE-LABEL: test172: 2951 ; PPC64LE: # %bb.0: 2952 ; PPC64LE-NEXT: lwsync 2953 ; PPC64LE-NEXT: .LBB172_1: 2954 ; PPC64LE-NEXT: lwarx 5, 0, 3 2955 ; PPC64LE-NEXT: subf 6, 4, 5 2956 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2957 ; PPC64LE-NEXT: bne 0, .LBB172_1 2958 ; PPC64LE-NEXT: # %bb.2: 2959 ; PPC64LE-NEXT: mr 3, 5 2960 ; PPC64LE-NEXT: blr 2961 %ret = atomicrmw sub i32* %ptr, i32 %val release 2962 ret i32 %ret 2963 } 2964 2965 define i32 @test173(i32* %ptr, i32 %val) { 2966 ; PPC64LE-LABEL: test173: 2967 ; PPC64LE: # %bb.0: 2968 ; PPC64LE-NEXT: lwsync 2969 ; PPC64LE-NEXT: .LBB173_1: 2970 ; PPC64LE-NEXT: lwarx 5, 0, 3 2971 ; PPC64LE-NEXT: subf 6, 4, 5 2972 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2973 ; PPC64LE-NEXT: bne 0, .LBB173_1 2974 ; PPC64LE-NEXT: # %bb.2: 2975 ; PPC64LE-NEXT: mr 3, 5 2976 ; PPC64LE-NEXT: lwsync 2977 ; PPC64LE-NEXT: blr 2978 %ret = atomicrmw sub i32* %ptr, i32 %val acq_rel 2979 ret i32 %ret 2980 } 2981 2982 define i32 @test174(i32* %ptr, i32 %val) { 2983 ; PPC64LE-LABEL: test174: 2984 ; PPC64LE: # %bb.0: 2985 ; PPC64LE-NEXT: sync 2986 ; PPC64LE-NEXT: .LBB174_1: 2987 ; PPC64LE-NEXT: lwarx 5, 0, 3 2988 ; PPC64LE-NEXT: subf 6, 4, 5 2989 ; PPC64LE-NEXT: stwcx. 6, 0, 3 2990 ; PPC64LE-NEXT: bne 0, .LBB174_1 2991 ; PPC64LE-NEXT: # %bb.2: 2992 ; PPC64LE-NEXT: mr 3, 5 2993 ; PPC64LE-NEXT: lwsync 2994 ; PPC64LE-NEXT: blr 2995 %ret = atomicrmw sub i32* %ptr, i32 %val seq_cst 2996 ret i32 %ret 2997 } 2998 2999 define i64 @test175(i64* %ptr, i64 %val) { 3000 ; PPC64LE-LABEL: test175: 3001 ; PPC64LE: # %bb.0: 3002 ; PPC64LE-NEXT: .LBB175_1: 3003 ; PPC64LE-NEXT: ldarx 5, 0, 3 3004 ; PPC64LE-NEXT: sub 6, 5, 4 3005 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3006 ; PPC64LE-NEXT: bne 0, .LBB175_1 3007 ; PPC64LE-NEXT: # %bb.2: 3008 ; PPC64LE-NEXT: mr 3, 5 3009 ; PPC64LE-NEXT: blr 3010 %ret = atomicrmw sub i64* %ptr, i64 %val monotonic 3011 ret i64 %ret 3012 } 3013 3014 define i64 @test176(i64* %ptr, i64 %val) { 3015 ; PPC64LE-LABEL: test176: 3016 ; PPC64LE: # %bb.0: 3017 ; PPC64LE-NEXT: mr 5, 3 3018 ; PPC64LE-NEXT: .LBB176_1: 3019 ; PPC64LE-NEXT: ldarx 3, 0, 5 3020 ; PPC64LE-NEXT: sub 6, 3, 4 3021 ; PPC64LE-NEXT: stdcx. 6, 0, 5 3022 ; PPC64LE-NEXT: bne 0, .LBB176_1 3023 ; PPC64LE-NEXT: # %bb.2: 3024 ; PPC64LE-NEXT: lwsync 3025 ; PPC64LE-NEXT: blr 3026 %ret = atomicrmw sub i64* %ptr, i64 %val acquire 3027 ret i64 %ret 3028 } 3029 3030 define i64 @test177(i64* %ptr, i64 %val) { 3031 ; PPC64LE-LABEL: test177: 3032 ; PPC64LE: # %bb.0: 3033 ; PPC64LE-NEXT: lwsync 3034 ; PPC64LE-NEXT: .LBB177_1: 3035 ; PPC64LE-NEXT: ldarx 5, 0, 3 3036 ; PPC64LE-NEXT: sub 6, 5, 4 3037 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3038 ; PPC64LE-NEXT: bne 0, .LBB177_1 3039 ; PPC64LE-NEXT: # %bb.2: 3040 ; PPC64LE-NEXT: mr 3, 5 3041 ; PPC64LE-NEXT: blr 3042 %ret = atomicrmw sub i64* %ptr, i64 %val release 3043 ret i64 %ret 3044 } 3045 3046 define i64 @test178(i64* %ptr, i64 %val) { 3047 ; PPC64LE-LABEL: test178: 3048 ; PPC64LE: # %bb.0: 3049 ; PPC64LE-NEXT: lwsync 3050 ; PPC64LE-NEXT: .LBB178_1: 3051 ; PPC64LE-NEXT: ldarx 5, 0, 3 3052 ; PPC64LE-NEXT: sub 6, 5, 4 3053 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3054 ; PPC64LE-NEXT: bne 0, .LBB178_1 3055 ; PPC64LE-NEXT: # %bb.2: 3056 ; PPC64LE-NEXT: mr 3, 5 3057 ; PPC64LE-NEXT: lwsync 3058 ; PPC64LE-NEXT: blr 3059 %ret = atomicrmw sub i64* %ptr, i64 %val acq_rel 3060 ret i64 %ret 3061 } 3062 3063 define i64 @test179(i64* %ptr, i64 %val) { 3064 ; PPC64LE-LABEL: test179: 3065 ; PPC64LE: # %bb.0: 3066 ; PPC64LE-NEXT: sync 3067 ; PPC64LE-NEXT: .LBB179_1: 3068 ; PPC64LE-NEXT: ldarx 5, 0, 3 3069 ; PPC64LE-NEXT: sub 6, 5, 4 3070 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3071 ; PPC64LE-NEXT: bne 0, .LBB179_1 3072 ; PPC64LE-NEXT: # %bb.2: 3073 ; PPC64LE-NEXT: mr 3, 5 3074 ; PPC64LE-NEXT: lwsync 3075 ; PPC64LE-NEXT: blr 3076 %ret = atomicrmw sub i64* %ptr, i64 %val seq_cst 3077 ret i64 %ret 3078 } 3079 3080 define i8 @test180(i8* %ptr, i8 %val) { 3081 ; PPC64LE-LABEL: test180: 3082 ; PPC64LE: # %bb.0: 3083 ; PPC64LE-NEXT: .LBB180_1: 3084 ; PPC64LE-NEXT: lbarx 5, 0, 3 3085 ; PPC64LE-NEXT: and 6, 4, 5 3086 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3087 ; PPC64LE-NEXT: bne 0, .LBB180_1 3088 ; PPC64LE-NEXT: # %bb.2: 3089 ; PPC64LE-NEXT: mr 3, 5 3090 ; PPC64LE-NEXT: blr 3091 %ret = atomicrmw and i8* %ptr, i8 %val monotonic 3092 ret i8 %ret 3093 } 3094 3095 define i8 @test181(i8* %ptr, i8 %val) { 3096 ; PPC64LE-LABEL: test181: 3097 ; PPC64LE: # %bb.0: 3098 ; PPC64LE-NEXT: mr 5, 3 3099 ; PPC64LE-NEXT: .LBB181_1: 3100 ; PPC64LE-NEXT: lbarx 3, 0, 5 3101 ; PPC64LE-NEXT: and 6, 4, 3 3102 ; PPC64LE-NEXT: stbcx. 6, 0, 5 3103 ; PPC64LE-NEXT: bne 0, .LBB181_1 3104 ; PPC64LE-NEXT: # %bb.2: 3105 ; PPC64LE-NEXT: lwsync 3106 ; PPC64LE-NEXT: blr 3107 %ret = atomicrmw and i8* %ptr, i8 %val acquire 3108 ret i8 %ret 3109 } 3110 3111 define i8 @test182(i8* %ptr, i8 %val) { 3112 ; PPC64LE-LABEL: test182: 3113 ; PPC64LE: # %bb.0: 3114 ; PPC64LE-NEXT: lwsync 3115 ; PPC64LE-NEXT: .LBB182_1: 3116 ; PPC64LE-NEXT: lbarx 5, 0, 3 3117 ; PPC64LE-NEXT: and 6, 4, 5 3118 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3119 ; PPC64LE-NEXT: bne 0, .LBB182_1 3120 ; PPC64LE-NEXT: # %bb.2: 3121 ; PPC64LE-NEXT: mr 3, 5 3122 ; PPC64LE-NEXT: blr 3123 %ret = atomicrmw and i8* %ptr, i8 %val release 3124 ret i8 %ret 3125 } 3126 3127 define i8 @test183(i8* %ptr, i8 %val) { 3128 ; PPC64LE-LABEL: test183: 3129 ; PPC64LE: # %bb.0: 3130 ; PPC64LE-NEXT: lwsync 3131 ; PPC64LE-NEXT: .LBB183_1: 3132 ; PPC64LE-NEXT: lbarx 5, 0, 3 3133 ; PPC64LE-NEXT: and 6, 4, 5 3134 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3135 ; PPC64LE-NEXT: bne 0, .LBB183_1 3136 ; PPC64LE-NEXT: # %bb.2: 3137 ; PPC64LE-NEXT: mr 3, 5 3138 ; PPC64LE-NEXT: lwsync 3139 ; PPC64LE-NEXT: blr 3140 %ret = atomicrmw and i8* %ptr, i8 %val acq_rel 3141 ret i8 %ret 3142 } 3143 3144 define i8 @test184(i8* %ptr, i8 %val) { 3145 ; PPC64LE-LABEL: test184: 3146 ; PPC64LE: # %bb.0: 3147 ; PPC64LE-NEXT: sync 3148 ; PPC64LE-NEXT: .LBB184_1: 3149 ; PPC64LE-NEXT: lbarx 5, 0, 3 3150 ; PPC64LE-NEXT: and 6, 4, 5 3151 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3152 ; PPC64LE-NEXT: bne 0, .LBB184_1 3153 ; PPC64LE-NEXT: # %bb.2: 3154 ; PPC64LE-NEXT: mr 3, 5 3155 ; PPC64LE-NEXT: lwsync 3156 ; PPC64LE-NEXT: blr 3157 %ret = atomicrmw and i8* %ptr, i8 %val seq_cst 3158 ret i8 %ret 3159 } 3160 3161 define i16 @test185(i16* %ptr, i16 %val) { 3162 ; PPC64LE-LABEL: test185: 3163 ; PPC64LE: # %bb.0: 3164 ; PPC64LE-NEXT: .LBB185_1: 3165 ; PPC64LE-NEXT: lharx 5, 0, 3 3166 ; PPC64LE-NEXT: and 6, 4, 5 3167 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3168 ; PPC64LE-NEXT: bne 0, .LBB185_1 3169 ; PPC64LE-NEXT: # %bb.2: 3170 ; PPC64LE-NEXT: mr 3, 5 3171 ; PPC64LE-NEXT: blr 3172 %ret = atomicrmw and i16* %ptr, i16 %val monotonic 3173 ret i16 %ret 3174 } 3175 3176 define i16 @test186(i16* %ptr, i16 %val) { 3177 ; PPC64LE-LABEL: test186: 3178 ; PPC64LE: # %bb.0: 3179 ; PPC64LE-NEXT: mr 5, 3 3180 ; PPC64LE-NEXT: .LBB186_1: 3181 ; PPC64LE-NEXT: lharx 3, 0, 5 3182 ; PPC64LE-NEXT: and 6, 4, 3 3183 ; PPC64LE-NEXT: sthcx. 6, 0, 5 3184 ; PPC64LE-NEXT: bne 0, .LBB186_1 3185 ; PPC64LE-NEXT: # %bb.2: 3186 ; PPC64LE-NEXT: lwsync 3187 ; PPC64LE-NEXT: blr 3188 %ret = atomicrmw and i16* %ptr, i16 %val acquire 3189 ret i16 %ret 3190 } 3191 3192 define i16 @test187(i16* %ptr, i16 %val) { 3193 ; PPC64LE-LABEL: test187: 3194 ; PPC64LE: # %bb.0: 3195 ; PPC64LE-NEXT: lwsync 3196 ; PPC64LE-NEXT: .LBB187_1: 3197 ; PPC64LE-NEXT: lharx 5, 0, 3 3198 ; PPC64LE-NEXT: and 6, 4, 5 3199 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3200 ; PPC64LE-NEXT: bne 0, .LBB187_1 3201 ; PPC64LE-NEXT: # %bb.2: 3202 ; PPC64LE-NEXT: mr 3, 5 3203 ; PPC64LE-NEXT: blr 3204 %ret = atomicrmw and i16* %ptr, i16 %val release 3205 ret i16 %ret 3206 } 3207 3208 define i16 @test188(i16* %ptr, i16 %val) { 3209 ; PPC64LE-LABEL: test188: 3210 ; PPC64LE: # %bb.0: 3211 ; PPC64LE-NEXT: lwsync 3212 ; PPC64LE-NEXT: .LBB188_1: 3213 ; PPC64LE-NEXT: lharx 5, 0, 3 3214 ; PPC64LE-NEXT: and 6, 4, 5 3215 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3216 ; PPC64LE-NEXT: bne 0, .LBB188_1 3217 ; PPC64LE-NEXT: # %bb.2: 3218 ; PPC64LE-NEXT: mr 3, 5 3219 ; PPC64LE-NEXT: lwsync 3220 ; PPC64LE-NEXT: blr 3221 %ret = atomicrmw and i16* %ptr, i16 %val acq_rel 3222 ret i16 %ret 3223 } 3224 3225 define i16 @test189(i16* %ptr, i16 %val) { 3226 ; PPC64LE-LABEL: test189: 3227 ; PPC64LE: # %bb.0: 3228 ; PPC64LE-NEXT: sync 3229 ; PPC64LE-NEXT: .LBB189_1: 3230 ; PPC64LE-NEXT: lharx 5, 0, 3 3231 ; PPC64LE-NEXT: and 6, 4, 5 3232 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3233 ; PPC64LE-NEXT: bne 0, .LBB189_1 3234 ; PPC64LE-NEXT: # %bb.2: 3235 ; PPC64LE-NEXT: mr 3, 5 3236 ; PPC64LE-NEXT: lwsync 3237 ; PPC64LE-NEXT: blr 3238 %ret = atomicrmw and i16* %ptr, i16 %val seq_cst 3239 ret i16 %ret 3240 } 3241 3242 define i32 @test190(i32* %ptr, i32 %val) { 3243 ; PPC64LE-LABEL: test190: 3244 ; PPC64LE: # %bb.0: 3245 ; PPC64LE-NEXT: .LBB190_1: 3246 ; PPC64LE-NEXT: lwarx 5, 0, 3 3247 ; PPC64LE-NEXT: and 6, 4, 5 3248 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3249 ; PPC64LE-NEXT: bne 0, .LBB190_1 3250 ; PPC64LE-NEXT: # %bb.2: 3251 ; PPC64LE-NEXT: mr 3, 5 3252 ; PPC64LE-NEXT: blr 3253 %ret = atomicrmw and i32* %ptr, i32 %val monotonic 3254 ret i32 %ret 3255 } 3256 3257 define i32 @test191(i32* %ptr, i32 %val) { 3258 ; PPC64LE-LABEL: test191: 3259 ; PPC64LE: # %bb.0: 3260 ; PPC64LE-NEXT: mr 5, 3 3261 ; PPC64LE-NEXT: .LBB191_1: 3262 ; PPC64LE-NEXT: lwarx 3, 0, 5 3263 ; PPC64LE-NEXT: and 6, 4, 3 3264 ; PPC64LE-NEXT: stwcx. 6, 0, 5 3265 ; PPC64LE-NEXT: bne 0, .LBB191_1 3266 ; PPC64LE-NEXT: # %bb.2: 3267 ; PPC64LE-NEXT: lwsync 3268 ; PPC64LE-NEXT: blr 3269 %ret = atomicrmw and i32* %ptr, i32 %val acquire 3270 ret i32 %ret 3271 } 3272 3273 define i32 @test192(i32* %ptr, i32 %val) { 3274 ; PPC64LE-LABEL: test192: 3275 ; PPC64LE: # %bb.0: 3276 ; PPC64LE-NEXT: lwsync 3277 ; PPC64LE-NEXT: .LBB192_1: 3278 ; PPC64LE-NEXT: lwarx 5, 0, 3 3279 ; PPC64LE-NEXT: and 6, 4, 5 3280 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3281 ; PPC64LE-NEXT: bne 0, .LBB192_1 3282 ; PPC64LE-NEXT: # %bb.2: 3283 ; PPC64LE-NEXT: mr 3, 5 3284 ; PPC64LE-NEXT: blr 3285 %ret = atomicrmw and i32* %ptr, i32 %val release 3286 ret i32 %ret 3287 } 3288 3289 define i32 @test193(i32* %ptr, i32 %val) { 3290 ; PPC64LE-LABEL: test193: 3291 ; PPC64LE: # %bb.0: 3292 ; PPC64LE-NEXT: lwsync 3293 ; PPC64LE-NEXT: .LBB193_1: 3294 ; PPC64LE-NEXT: lwarx 5, 0, 3 3295 ; PPC64LE-NEXT: and 6, 4, 5 3296 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3297 ; PPC64LE-NEXT: bne 0, .LBB193_1 3298 ; PPC64LE-NEXT: # %bb.2: 3299 ; PPC64LE-NEXT: mr 3, 5 3300 ; PPC64LE-NEXT: lwsync 3301 ; PPC64LE-NEXT: blr 3302 %ret = atomicrmw and i32* %ptr, i32 %val acq_rel 3303 ret i32 %ret 3304 } 3305 3306 define i32 @test194(i32* %ptr, i32 %val) { 3307 ; PPC64LE-LABEL: test194: 3308 ; PPC64LE: # %bb.0: 3309 ; PPC64LE-NEXT: sync 3310 ; PPC64LE-NEXT: .LBB194_1: 3311 ; PPC64LE-NEXT: lwarx 5, 0, 3 3312 ; PPC64LE-NEXT: and 6, 4, 5 3313 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3314 ; PPC64LE-NEXT: bne 0, .LBB194_1 3315 ; PPC64LE-NEXT: # %bb.2: 3316 ; PPC64LE-NEXT: mr 3, 5 3317 ; PPC64LE-NEXT: lwsync 3318 ; PPC64LE-NEXT: blr 3319 %ret = atomicrmw and i32* %ptr, i32 %val seq_cst 3320 ret i32 %ret 3321 } 3322 3323 define i64 @test195(i64* %ptr, i64 %val) { 3324 ; PPC64LE-LABEL: test195: 3325 ; PPC64LE: # %bb.0: 3326 ; PPC64LE-NEXT: .LBB195_1: 3327 ; PPC64LE-NEXT: ldarx 5, 0, 3 3328 ; PPC64LE-NEXT: and 6, 4, 5 3329 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3330 ; PPC64LE-NEXT: bne 0, .LBB195_1 3331 ; PPC64LE-NEXT: # %bb.2: 3332 ; PPC64LE-NEXT: mr 3, 5 3333 ; PPC64LE-NEXT: blr 3334 %ret = atomicrmw and i64* %ptr, i64 %val monotonic 3335 ret i64 %ret 3336 } 3337 3338 define i64 @test196(i64* %ptr, i64 %val) { 3339 ; PPC64LE-LABEL: test196: 3340 ; PPC64LE: # %bb.0: 3341 ; PPC64LE-NEXT: mr 5, 3 3342 ; PPC64LE-NEXT: .LBB196_1: 3343 ; PPC64LE-NEXT: ldarx 3, 0, 5 3344 ; PPC64LE-NEXT: and 6, 4, 3 3345 ; PPC64LE-NEXT: stdcx. 6, 0, 5 3346 ; PPC64LE-NEXT: bne 0, .LBB196_1 3347 ; PPC64LE-NEXT: # %bb.2: 3348 ; PPC64LE-NEXT: lwsync 3349 ; PPC64LE-NEXT: blr 3350 %ret = atomicrmw and i64* %ptr, i64 %val acquire 3351 ret i64 %ret 3352 } 3353 3354 define i64 @test197(i64* %ptr, i64 %val) { 3355 ; PPC64LE-LABEL: test197: 3356 ; PPC64LE: # %bb.0: 3357 ; PPC64LE-NEXT: lwsync 3358 ; PPC64LE-NEXT: .LBB197_1: 3359 ; PPC64LE-NEXT: ldarx 5, 0, 3 3360 ; PPC64LE-NEXT: and 6, 4, 5 3361 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3362 ; PPC64LE-NEXT: bne 0, .LBB197_1 3363 ; PPC64LE-NEXT: # %bb.2: 3364 ; PPC64LE-NEXT: mr 3, 5 3365 ; PPC64LE-NEXT: blr 3366 %ret = atomicrmw and i64* %ptr, i64 %val release 3367 ret i64 %ret 3368 } 3369 3370 define i64 @test198(i64* %ptr, i64 %val) { 3371 ; PPC64LE-LABEL: test198: 3372 ; PPC64LE: # %bb.0: 3373 ; PPC64LE-NEXT: lwsync 3374 ; PPC64LE-NEXT: .LBB198_1: 3375 ; PPC64LE-NEXT: ldarx 5, 0, 3 3376 ; PPC64LE-NEXT: and 6, 4, 5 3377 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3378 ; PPC64LE-NEXT: bne 0, .LBB198_1 3379 ; PPC64LE-NEXT: # %bb.2: 3380 ; PPC64LE-NEXT: mr 3, 5 3381 ; PPC64LE-NEXT: lwsync 3382 ; PPC64LE-NEXT: blr 3383 %ret = atomicrmw and i64* %ptr, i64 %val acq_rel 3384 ret i64 %ret 3385 } 3386 3387 define i64 @test199(i64* %ptr, i64 %val) { 3388 ; PPC64LE-LABEL: test199: 3389 ; PPC64LE: # %bb.0: 3390 ; PPC64LE-NEXT: sync 3391 ; PPC64LE-NEXT: .LBB199_1: 3392 ; PPC64LE-NEXT: ldarx 5, 0, 3 3393 ; PPC64LE-NEXT: and 6, 4, 5 3394 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3395 ; PPC64LE-NEXT: bne 0, .LBB199_1 3396 ; PPC64LE-NEXT: # %bb.2: 3397 ; PPC64LE-NEXT: mr 3, 5 3398 ; PPC64LE-NEXT: lwsync 3399 ; PPC64LE-NEXT: blr 3400 %ret = atomicrmw and i64* %ptr, i64 %val seq_cst 3401 ret i64 %ret 3402 } 3403 3404 define i8 @test200(i8* %ptr, i8 %val) { 3405 ; PPC64LE-LABEL: test200: 3406 ; PPC64LE: # %bb.0: 3407 ; PPC64LE-NEXT: .LBB200_1: 3408 ; PPC64LE-NEXT: lbarx 5, 0, 3 3409 ; PPC64LE-NEXT: nand 6, 4, 5 3410 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3411 ; PPC64LE-NEXT: bne 0, .LBB200_1 3412 ; PPC64LE-NEXT: # %bb.2: 3413 ; PPC64LE-NEXT: mr 3, 5 3414 ; PPC64LE-NEXT: blr 3415 %ret = atomicrmw nand i8* %ptr, i8 %val monotonic 3416 ret i8 %ret 3417 } 3418 3419 define i8 @test201(i8* %ptr, i8 %val) { 3420 ; PPC64LE-LABEL: test201: 3421 ; PPC64LE: # %bb.0: 3422 ; PPC64LE-NEXT: mr 5, 3 3423 ; PPC64LE-NEXT: .LBB201_1: 3424 ; PPC64LE-NEXT: lbarx 3, 0, 5 3425 ; PPC64LE-NEXT: nand 6, 4, 3 3426 ; PPC64LE-NEXT: stbcx. 6, 0, 5 3427 ; PPC64LE-NEXT: bne 0, .LBB201_1 3428 ; PPC64LE-NEXT: # %bb.2: 3429 ; PPC64LE-NEXT: lwsync 3430 ; PPC64LE-NEXT: blr 3431 %ret = atomicrmw nand i8* %ptr, i8 %val acquire 3432 ret i8 %ret 3433 } 3434 3435 define i8 @test202(i8* %ptr, i8 %val) { 3436 ; PPC64LE-LABEL: test202: 3437 ; PPC64LE: # %bb.0: 3438 ; PPC64LE-NEXT: lwsync 3439 ; PPC64LE-NEXT: .LBB202_1: 3440 ; PPC64LE-NEXT: lbarx 5, 0, 3 3441 ; PPC64LE-NEXT: nand 6, 4, 5 3442 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3443 ; PPC64LE-NEXT: bne 0, .LBB202_1 3444 ; PPC64LE-NEXT: # %bb.2: 3445 ; PPC64LE-NEXT: mr 3, 5 3446 ; PPC64LE-NEXT: blr 3447 %ret = atomicrmw nand i8* %ptr, i8 %val release 3448 ret i8 %ret 3449 } 3450 3451 define i8 @test203(i8* %ptr, i8 %val) { 3452 ; PPC64LE-LABEL: test203: 3453 ; PPC64LE: # %bb.0: 3454 ; PPC64LE-NEXT: lwsync 3455 ; PPC64LE-NEXT: .LBB203_1: 3456 ; PPC64LE-NEXT: lbarx 5, 0, 3 3457 ; PPC64LE-NEXT: nand 6, 4, 5 3458 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3459 ; PPC64LE-NEXT: bne 0, .LBB203_1 3460 ; PPC64LE-NEXT: # %bb.2: 3461 ; PPC64LE-NEXT: mr 3, 5 3462 ; PPC64LE-NEXT: lwsync 3463 ; PPC64LE-NEXT: blr 3464 %ret = atomicrmw nand i8* %ptr, i8 %val acq_rel 3465 ret i8 %ret 3466 } 3467 3468 define i8 @test204(i8* %ptr, i8 %val) { 3469 ; PPC64LE-LABEL: test204: 3470 ; PPC64LE: # %bb.0: 3471 ; PPC64LE-NEXT: sync 3472 ; PPC64LE-NEXT: .LBB204_1: 3473 ; PPC64LE-NEXT: lbarx 5, 0, 3 3474 ; PPC64LE-NEXT: nand 6, 4, 5 3475 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3476 ; PPC64LE-NEXT: bne 0, .LBB204_1 3477 ; PPC64LE-NEXT: # %bb.2: 3478 ; PPC64LE-NEXT: mr 3, 5 3479 ; PPC64LE-NEXT: lwsync 3480 ; PPC64LE-NEXT: blr 3481 %ret = atomicrmw nand i8* %ptr, i8 %val seq_cst 3482 ret i8 %ret 3483 } 3484 3485 define i16 @test205(i16* %ptr, i16 %val) { 3486 ; PPC64LE-LABEL: test205: 3487 ; PPC64LE: # %bb.0: 3488 ; PPC64LE-NEXT: .LBB205_1: 3489 ; PPC64LE-NEXT: lharx 5, 0, 3 3490 ; PPC64LE-NEXT: nand 6, 4, 5 3491 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3492 ; PPC64LE-NEXT: bne 0, .LBB205_1 3493 ; PPC64LE-NEXT: # %bb.2: 3494 ; PPC64LE-NEXT: mr 3, 5 3495 ; PPC64LE-NEXT: blr 3496 %ret = atomicrmw nand i16* %ptr, i16 %val monotonic 3497 ret i16 %ret 3498 } 3499 3500 define i16 @test206(i16* %ptr, i16 %val) { 3501 ; PPC64LE-LABEL: test206: 3502 ; PPC64LE: # %bb.0: 3503 ; PPC64LE-NEXT: mr 5, 3 3504 ; PPC64LE-NEXT: .LBB206_1: 3505 ; PPC64LE-NEXT: lharx 3, 0, 5 3506 ; PPC64LE-NEXT: nand 6, 4, 3 3507 ; PPC64LE-NEXT: sthcx. 6, 0, 5 3508 ; PPC64LE-NEXT: bne 0, .LBB206_1 3509 ; PPC64LE-NEXT: # %bb.2: 3510 ; PPC64LE-NEXT: lwsync 3511 ; PPC64LE-NEXT: blr 3512 %ret = atomicrmw nand i16* %ptr, i16 %val acquire 3513 ret i16 %ret 3514 } 3515 3516 define i16 @test207(i16* %ptr, i16 %val) { 3517 ; PPC64LE-LABEL: test207: 3518 ; PPC64LE: # %bb.0: 3519 ; PPC64LE-NEXT: lwsync 3520 ; PPC64LE-NEXT: .LBB207_1: 3521 ; PPC64LE-NEXT: lharx 5, 0, 3 3522 ; PPC64LE-NEXT: nand 6, 4, 5 3523 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3524 ; PPC64LE-NEXT: bne 0, .LBB207_1 3525 ; PPC64LE-NEXT: # %bb.2: 3526 ; PPC64LE-NEXT: mr 3, 5 3527 ; PPC64LE-NEXT: blr 3528 %ret = atomicrmw nand i16* %ptr, i16 %val release 3529 ret i16 %ret 3530 } 3531 3532 define i16 @test208(i16* %ptr, i16 %val) { 3533 ; PPC64LE-LABEL: test208: 3534 ; PPC64LE: # %bb.0: 3535 ; PPC64LE-NEXT: lwsync 3536 ; PPC64LE-NEXT: .LBB208_1: 3537 ; PPC64LE-NEXT: lharx 5, 0, 3 3538 ; PPC64LE-NEXT: nand 6, 4, 5 3539 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3540 ; PPC64LE-NEXT: bne 0, .LBB208_1 3541 ; PPC64LE-NEXT: # %bb.2: 3542 ; PPC64LE-NEXT: mr 3, 5 3543 ; PPC64LE-NEXT: lwsync 3544 ; PPC64LE-NEXT: blr 3545 %ret = atomicrmw nand i16* %ptr, i16 %val acq_rel 3546 ret i16 %ret 3547 } 3548 3549 define i16 @test209(i16* %ptr, i16 %val) { 3550 ; PPC64LE-LABEL: test209: 3551 ; PPC64LE: # %bb.0: 3552 ; PPC64LE-NEXT: sync 3553 ; PPC64LE-NEXT: .LBB209_1: 3554 ; PPC64LE-NEXT: lharx 5, 0, 3 3555 ; PPC64LE-NEXT: nand 6, 4, 5 3556 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3557 ; PPC64LE-NEXT: bne 0, .LBB209_1 3558 ; PPC64LE-NEXT: # %bb.2: 3559 ; PPC64LE-NEXT: mr 3, 5 3560 ; PPC64LE-NEXT: lwsync 3561 ; PPC64LE-NEXT: blr 3562 %ret = atomicrmw nand i16* %ptr, i16 %val seq_cst 3563 ret i16 %ret 3564 } 3565 3566 define i32 @test210(i32* %ptr, i32 %val) { 3567 ; PPC64LE-LABEL: test210: 3568 ; PPC64LE: # %bb.0: 3569 ; PPC64LE-NEXT: .LBB210_1: 3570 ; PPC64LE-NEXT: lwarx 5, 0, 3 3571 ; PPC64LE-NEXT: nand 6, 4, 5 3572 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3573 ; PPC64LE-NEXT: bne 0, .LBB210_1 3574 ; PPC64LE-NEXT: # %bb.2: 3575 ; PPC64LE-NEXT: mr 3, 5 3576 ; PPC64LE-NEXT: blr 3577 %ret = atomicrmw nand i32* %ptr, i32 %val monotonic 3578 ret i32 %ret 3579 } 3580 3581 define i32 @test211(i32* %ptr, i32 %val) { 3582 ; PPC64LE-LABEL: test211: 3583 ; PPC64LE: # %bb.0: 3584 ; PPC64LE-NEXT: mr 5, 3 3585 ; PPC64LE-NEXT: .LBB211_1: 3586 ; PPC64LE-NEXT: lwarx 3, 0, 5 3587 ; PPC64LE-NEXT: nand 6, 4, 3 3588 ; PPC64LE-NEXT: stwcx. 6, 0, 5 3589 ; PPC64LE-NEXT: bne 0, .LBB211_1 3590 ; PPC64LE-NEXT: # %bb.2: 3591 ; PPC64LE-NEXT: lwsync 3592 ; PPC64LE-NEXT: blr 3593 %ret = atomicrmw nand i32* %ptr, i32 %val acquire 3594 ret i32 %ret 3595 } 3596 3597 define i32 @test212(i32* %ptr, i32 %val) { 3598 ; PPC64LE-LABEL: test212: 3599 ; PPC64LE: # %bb.0: 3600 ; PPC64LE-NEXT: lwsync 3601 ; PPC64LE-NEXT: .LBB212_1: 3602 ; PPC64LE-NEXT: lwarx 5, 0, 3 3603 ; PPC64LE-NEXT: nand 6, 4, 5 3604 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3605 ; PPC64LE-NEXT: bne 0, .LBB212_1 3606 ; PPC64LE-NEXT: # %bb.2: 3607 ; PPC64LE-NEXT: mr 3, 5 3608 ; PPC64LE-NEXT: blr 3609 %ret = atomicrmw nand i32* %ptr, i32 %val release 3610 ret i32 %ret 3611 } 3612 3613 define i32 @test213(i32* %ptr, i32 %val) { 3614 ; PPC64LE-LABEL: test213: 3615 ; PPC64LE: # %bb.0: 3616 ; PPC64LE-NEXT: lwsync 3617 ; PPC64LE-NEXT: .LBB213_1: 3618 ; PPC64LE-NEXT: lwarx 5, 0, 3 3619 ; PPC64LE-NEXT: nand 6, 4, 5 3620 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3621 ; PPC64LE-NEXT: bne 0, .LBB213_1 3622 ; PPC64LE-NEXT: # %bb.2: 3623 ; PPC64LE-NEXT: mr 3, 5 3624 ; PPC64LE-NEXT: lwsync 3625 ; PPC64LE-NEXT: blr 3626 %ret = atomicrmw nand i32* %ptr, i32 %val acq_rel 3627 ret i32 %ret 3628 } 3629 3630 define i32 @test214(i32* %ptr, i32 %val) { 3631 ; PPC64LE-LABEL: test214: 3632 ; PPC64LE: # %bb.0: 3633 ; PPC64LE-NEXT: sync 3634 ; PPC64LE-NEXT: .LBB214_1: 3635 ; PPC64LE-NEXT: lwarx 5, 0, 3 3636 ; PPC64LE-NEXT: nand 6, 4, 5 3637 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3638 ; PPC64LE-NEXT: bne 0, .LBB214_1 3639 ; PPC64LE-NEXT: # %bb.2: 3640 ; PPC64LE-NEXT: mr 3, 5 3641 ; PPC64LE-NEXT: lwsync 3642 ; PPC64LE-NEXT: blr 3643 %ret = atomicrmw nand i32* %ptr, i32 %val seq_cst 3644 ret i32 %ret 3645 } 3646 3647 define i64 @test215(i64* %ptr, i64 %val) { 3648 ; PPC64LE-LABEL: test215: 3649 ; PPC64LE: # %bb.0: 3650 ; PPC64LE-NEXT: .LBB215_1: 3651 ; PPC64LE-NEXT: ldarx 5, 0, 3 3652 ; PPC64LE-NEXT: nand 6, 4, 5 3653 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3654 ; PPC64LE-NEXT: bne 0, .LBB215_1 3655 ; PPC64LE-NEXT: # %bb.2: 3656 ; PPC64LE-NEXT: mr 3, 5 3657 ; PPC64LE-NEXT: blr 3658 %ret = atomicrmw nand i64* %ptr, i64 %val monotonic 3659 ret i64 %ret 3660 } 3661 3662 define i64 @test216(i64* %ptr, i64 %val) { 3663 ; PPC64LE-LABEL: test216: 3664 ; PPC64LE: # %bb.0: 3665 ; PPC64LE-NEXT: mr 5, 3 3666 ; PPC64LE-NEXT: .LBB216_1: 3667 ; PPC64LE-NEXT: ldarx 3, 0, 5 3668 ; PPC64LE-NEXT: nand 6, 4, 3 3669 ; PPC64LE-NEXT: stdcx. 6, 0, 5 3670 ; PPC64LE-NEXT: bne 0, .LBB216_1 3671 ; PPC64LE-NEXT: # %bb.2: 3672 ; PPC64LE-NEXT: lwsync 3673 ; PPC64LE-NEXT: blr 3674 %ret = atomicrmw nand i64* %ptr, i64 %val acquire 3675 ret i64 %ret 3676 } 3677 3678 define i64 @test217(i64* %ptr, i64 %val) { 3679 ; PPC64LE-LABEL: test217: 3680 ; PPC64LE: # %bb.0: 3681 ; PPC64LE-NEXT: lwsync 3682 ; PPC64LE-NEXT: .LBB217_1: 3683 ; PPC64LE-NEXT: ldarx 5, 0, 3 3684 ; PPC64LE-NEXT: nand 6, 4, 5 3685 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3686 ; PPC64LE-NEXT: bne 0, .LBB217_1 3687 ; PPC64LE-NEXT: # %bb.2: 3688 ; PPC64LE-NEXT: mr 3, 5 3689 ; PPC64LE-NEXT: blr 3690 %ret = atomicrmw nand i64* %ptr, i64 %val release 3691 ret i64 %ret 3692 } 3693 3694 define i64 @test218(i64* %ptr, i64 %val) { 3695 ; PPC64LE-LABEL: test218: 3696 ; PPC64LE: # %bb.0: 3697 ; PPC64LE-NEXT: lwsync 3698 ; PPC64LE-NEXT: .LBB218_1: 3699 ; PPC64LE-NEXT: ldarx 5, 0, 3 3700 ; PPC64LE-NEXT: nand 6, 4, 5 3701 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3702 ; PPC64LE-NEXT: bne 0, .LBB218_1 3703 ; PPC64LE-NEXT: # %bb.2: 3704 ; PPC64LE-NEXT: mr 3, 5 3705 ; PPC64LE-NEXT: lwsync 3706 ; PPC64LE-NEXT: blr 3707 %ret = atomicrmw nand i64* %ptr, i64 %val acq_rel 3708 ret i64 %ret 3709 } 3710 3711 define i64 @test219(i64* %ptr, i64 %val) { 3712 ; PPC64LE-LABEL: test219: 3713 ; PPC64LE: # %bb.0: 3714 ; PPC64LE-NEXT: sync 3715 ; PPC64LE-NEXT: .LBB219_1: 3716 ; PPC64LE-NEXT: ldarx 5, 0, 3 3717 ; PPC64LE-NEXT: nand 6, 4, 5 3718 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3719 ; PPC64LE-NEXT: bne 0, .LBB219_1 3720 ; PPC64LE-NEXT: # %bb.2: 3721 ; PPC64LE-NEXT: mr 3, 5 3722 ; PPC64LE-NEXT: lwsync 3723 ; PPC64LE-NEXT: blr 3724 %ret = atomicrmw nand i64* %ptr, i64 %val seq_cst 3725 ret i64 %ret 3726 } 3727 3728 define i8 @test220(i8* %ptr, i8 %val) { 3729 ; PPC64LE-LABEL: test220: 3730 ; PPC64LE: # %bb.0: 3731 ; PPC64LE-NEXT: .LBB220_1: 3732 ; PPC64LE-NEXT: lbarx 5, 0, 3 3733 ; PPC64LE-NEXT: or 6, 4, 5 3734 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3735 ; PPC64LE-NEXT: bne 0, .LBB220_1 3736 ; PPC64LE-NEXT: # %bb.2: 3737 ; PPC64LE-NEXT: mr 3, 5 3738 ; PPC64LE-NEXT: blr 3739 %ret = atomicrmw or i8* %ptr, i8 %val monotonic 3740 ret i8 %ret 3741 } 3742 3743 define i8 @test221(i8* %ptr, i8 %val) { 3744 ; PPC64LE-LABEL: test221: 3745 ; PPC64LE: # %bb.0: 3746 ; PPC64LE-NEXT: mr 5, 3 3747 ; PPC64LE-NEXT: .LBB221_1: 3748 ; PPC64LE-NEXT: lbarx 3, 0, 5 3749 ; PPC64LE-NEXT: or 6, 4, 3 3750 ; PPC64LE-NEXT: stbcx. 6, 0, 5 3751 ; PPC64LE-NEXT: bne 0, .LBB221_1 3752 ; PPC64LE-NEXT: # %bb.2: 3753 ; PPC64LE-NEXT: lwsync 3754 ; PPC64LE-NEXT: blr 3755 %ret = atomicrmw or i8* %ptr, i8 %val acquire 3756 ret i8 %ret 3757 } 3758 3759 define i8 @test222(i8* %ptr, i8 %val) { 3760 ; PPC64LE-LABEL: test222: 3761 ; PPC64LE: # %bb.0: 3762 ; PPC64LE-NEXT: lwsync 3763 ; PPC64LE-NEXT: .LBB222_1: 3764 ; PPC64LE-NEXT: lbarx 5, 0, 3 3765 ; PPC64LE-NEXT: or 6, 4, 5 3766 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3767 ; PPC64LE-NEXT: bne 0, .LBB222_1 3768 ; PPC64LE-NEXT: # %bb.2: 3769 ; PPC64LE-NEXT: mr 3, 5 3770 ; PPC64LE-NEXT: blr 3771 %ret = atomicrmw or i8* %ptr, i8 %val release 3772 ret i8 %ret 3773 } 3774 3775 define i8 @test223(i8* %ptr, i8 %val) { 3776 ; PPC64LE-LABEL: test223: 3777 ; PPC64LE: # %bb.0: 3778 ; PPC64LE-NEXT: lwsync 3779 ; PPC64LE-NEXT: .LBB223_1: 3780 ; PPC64LE-NEXT: lbarx 5, 0, 3 3781 ; PPC64LE-NEXT: or 6, 4, 5 3782 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3783 ; PPC64LE-NEXT: bne 0, .LBB223_1 3784 ; PPC64LE-NEXT: # %bb.2: 3785 ; PPC64LE-NEXT: mr 3, 5 3786 ; PPC64LE-NEXT: lwsync 3787 ; PPC64LE-NEXT: blr 3788 %ret = atomicrmw or i8* %ptr, i8 %val acq_rel 3789 ret i8 %ret 3790 } 3791 3792 define i8 @test224(i8* %ptr, i8 %val) { 3793 ; PPC64LE-LABEL: test224: 3794 ; PPC64LE: # %bb.0: 3795 ; PPC64LE-NEXT: sync 3796 ; PPC64LE-NEXT: .LBB224_1: 3797 ; PPC64LE-NEXT: lbarx 5, 0, 3 3798 ; PPC64LE-NEXT: or 6, 4, 5 3799 ; PPC64LE-NEXT: stbcx. 6, 0, 3 3800 ; PPC64LE-NEXT: bne 0, .LBB224_1 3801 ; PPC64LE-NEXT: # %bb.2: 3802 ; PPC64LE-NEXT: mr 3, 5 3803 ; PPC64LE-NEXT: lwsync 3804 ; PPC64LE-NEXT: blr 3805 %ret = atomicrmw or i8* %ptr, i8 %val seq_cst 3806 ret i8 %ret 3807 } 3808 3809 define i16 @test225(i16* %ptr, i16 %val) { 3810 ; PPC64LE-LABEL: test225: 3811 ; PPC64LE: # %bb.0: 3812 ; PPC64LE-NEXT: .LBB225_1: 3813 ; PPC64LE-NEXT: lharx 5, 0, 3 3814 ; PPC64LE-NEXT: or 6, 4, 5 3815 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3816 ; PPC64LE-NEXT: bne 0, .LBB225_1 3817 ; PPC64LE-NEXT: # %bb.2: 3818 ; PPC64LE-NEXT: mr 3, 5 3819 ; PPC64LE-NEXT: blr 3820 %ret = atomicrmw or i16* %ptr, i16 %val monotonic 3821 ret i16 %ret 3822 } 3823 3824 define i16 @test226(i16* %ptr, i16 %val) { 3825 ; PPC64LE-LABEL: test226: 3826 ; PPC64LE: # %bb.0: 3827 ; PPC64LE-NEXT: mr 5, 3 3828 ; PPC64LE-NEXT: .LBB226_1: 3829 ; PPC64LE-NEXT: lharx 3, 0, 5 3830 ; PPC64LE-NEXT: or 6, 4, 3 3831 ; PPC64LE-NEXT: sthcx. 6, 0, 5 3832 ; PPC64LE-NEXT: bne 0, .LBB226_1 3833 ; PPC64LE-NEXT: # %bb.2: 3834 ; PPC64LE-NEXT: lwsync 3835 ; PPC64LE-NEXT: blr 3836 %ret = atomicrmw or i16* %ptr, i16 %val acquire 3837 ret i16 %ret 3838 } 3839 3840 define i16 @test227(i16* %ptr, i16 %val) { 3841 ; PPC64LE-LABEL: test227: 3842 ; PPC64LE: # %bb.0: 3843 ; PPC64LE-NEXT: lwsync 3844 ; PPC64LE-NEXT: .LBB227_1: 3845 ; PPC64LE-NEXT: lharx 5, 0, 3 3846 ; PPC64LE-NEXT: or 6, 4, 5 3847 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3848 ; PPC64LE-NEXT: bne 0, .LBB227_1 3849 ; PPC64LE-NEXT: # %bb.2: 3850 ; PPC64LE-NEXT: mr 3, 5 3851 ; PPC64LE-NEXT: blr 3852 %ret = atomicrmw or i16* %ptr, i16 %val release 3853 ret i16 %ret 3854 } 3855 3856 define i16 @test228(i16* %ptr, i16 %val) { 3857 ; PPC64LE-LABEL: test228: 3858 ; PPC64LE: # %bb.0: 3859 ; PPC64LE-NEXT: lwsync 3860 ; PPC64LE-NEXT: .LBB228_1: 3861 ; PPC64LE-NEXT: lharx 5, 0, 3 3862 ; PPC64LE-NEXT: or 6, 4, 5 3863 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3864 ; PPC64LE-NEXT: bne 0, .LBB228_1 3865 ; PPC64LE-NEXT: # %bb.2: 3866 ; PPC64LE-NEXT: mr 3, 5 3867 ; PPC64LE-NEXT: lwsync 3868 ; PPC64LE-NEXT: blr 3869 %ret = atomicrmw or i16* %ptr, i16 %val acq_rel 3870 ret i16 %ret 3871 } 3872 3873 define i16 @test229(i16* %ptr, i16 %val) { 3874 ; PPC64LE-LABEL: test229: 3875 ; PPC64LE: # %bb.0: 3876 ; PPC64LE-NEXT: sync 3877 ; PPC64LE-NEXT: .LBB229_1: 3878 ; PPC64LE-NEXT: lharx 5, 0, 3 3879 ; PPC64LE-NEXT: or 6, 4, 5 3880 ; PPC64LE-NEXT: sthcx. 6, 0, 3 3881 ; PPC64LE-NEXT: bne 0, .LBB229_1 3882 ; PPC64LE-NEXT: # %bb.2: 3883 ; PPC64LE-NEXT: mr 3, 5 3884 ; PPC64LE-NEXT: lwsync 3885 ; PPC64LE-NEXT: blr 3886 %ret = atomicrmw or i16* %ptr, i16 %val seq_cst 3887 ret i16 %ret 3888 } 3889 3890 define i32 @test230(i32* %ptr, i32 %val) { 3891 ; PPC64LE-LABEL: test230: 3892 ; PPC64LE: # %bb.0: 3893 ; PPC64LE-NEXT: .LBB230_1: 3894 ; PPC64LE-NEXT: lwarx 5, 0, 3 3895 ; PPC64LE-NEXT: or 6, 4, 5 3896 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3897 ; PPC64LE-NEXT: bne 0, .LBB230_1 3898 ; PPC64LE-NEXT: # %bb.2: 3899 ; PPC64LE-NEXT: mr 3, 5 3900 ; PPC64LE-NEXT: blr 3901 %ret = atomicrmw or i32* %ptr, i32 %val monotonic 3902 ret i32 %ret 3903 } 3904 3905 define i32 @test231(i32* %ptr, i32 %val) { 3906 ; PPC64LE-LABEL: test231: 3907 ; PPC64LE: # %bb.0: 3908 ; PPC64LE-NEXT: mr 5, 3 3909 ; PPC64LE-NEXT: .LBB231_1: 3910 ; PPC64LE-NEXT: lwarx 3, 0, 5 3911 ; PPC64LE-NEXT: or 6, 4, 3 3912 ; PPC64LE-NEXT: stwcx. 6, 0, 5 3913 ; PPC64LE-NEXT: bne 0, .LBB231_1 3914 ; PPC64LE-NEXT: # %bb.2: 3915 ; PPC64LE-NEXT: lwsync 3916 ; PPC64LE-NEXT: blr 3917 %ret = atomicrmw or i32* %ptr, i32 %val acquire 3918 ret i32 %ret 3919 } 3920 3921 define i32 @test232(i32* %ptr, i32 %val) { 3922 ; PPC64LE-LABEL: test232: 3923 ; PPC64LE: # %bb.0: 3924 ; PPC64LE-NEXT: lwsync 3925 ; PPC64LE-NEXT: .LBB232_1: 3926 ; PPC64LE-NEXT: lwarx 5, 0, 3 3927 ; PPC64LE-NEXT: or 6, 4, 5 3928 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3929 ; PPC64LE-NEXT: bne 0, .LBB232_1 3930 ; PPC64LE-NEXT: # %bb.2: 3931 ; PPC64LE-NEXT: mr 3, 5 3932 ; PPC64LE-NEXT: blr 3933 %ret = atomicrmw or i32* %ptr, i32 %val release 3934 ret i32 %ret 3935 } 3936 3937 define i32 @test233(i32* %ptr, i32 %val) { 3938 ; PPC64LE-LABEL: test233: 3939 ; PPC64LE: # %bb.0: 3940 ; PPC64LE-NEXT: lwsync 3941 ; PPC64LE-NEXT: .LBB233_1: 3942 ; PPC64LE-NEXT: lwarx 5, 0, 3 3943 ; PPC64LE-NEXT: or 6, 4, 5 3944 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3945 ; PPC64LE-NEXT: bne 0, .LBB233_1 3946 ; PPC64LE-NEXT: # %bb.2: 3947 ; PPC64LE-NEXT: mr 3, 5 3948 ; PPC64LE-NEXT: lwsync 3949 ; PPC64LE-NEXT: blr 3950 %ret = atomicrmw or i32* %ptr, i32 %val acq_rel 3951 ret i32 %ret 3952 } 3953 3954 define i32 @test234(i32* %ptr, i32 %val) { 3955 ; PPC64LE-LABEL: test234: 3956 ; PPC64LE: # %bb.0: 3957 ; PPC64LE-NEXT: sync 3958 ; PPC64LE-NEXT: .LBB234_1: 3959 ; PPC64LE-NEXT: lwarx 5, 0, 3 3960 ; PPC64LE-NEXT: or 6, 4, 5 3961 ; PPC64LE-NEXT: stwcx. 6, 0, 3 3962 ; PPC64LE-NEXT: bne 0, .LBB234_1 3963 ; PPC64LE-NEXT: # %bb.2: 3964 ; PPC64LE-NEXT: mr 3, 5 3965 ; PPC64LE-NEXT: lwsync 3966 ; PPC64LE-NEXT: blr 3967 %ret = atomicrmw or i32* %ptr, i32 %val seq_cst 3968 ret i32 %ret 3969 } 3970 3971 define i64 @test235(i64* %ptr, i64 %val) { 3972 ; PPC64LE-LABEL: test235: 3973 ; PPC64LE: # %bb.0: 3974 ; PPC64LE-NEXT: .LBB235_1: 3975 ; PPC64LE-NEXT: ldarx 5, 0, 3 3976 ; PPC64LE-NEXT: or 6, 4, 5 3977 ; PPC64LE-NEXT: stdcx. 6, 0, 3 3978 ; PPC64LE-NEXT: bne 0, .LBB235_1 3979 ; PPC64LE-NEXT: # %bb.2: 3980 ; PPC64LE-NEXT: mr 3, 5 3981 ; PPC64LE-NEXT: blr 3982 %ret = atomicrmw or i64* %ptr, i64 %val monotonic 3983 ret i64 %ret 3984 } 3985 3986 define i64 @test236(i64* %ptr, i64 %val) { 3987 ; PPC64LE-LABEL: test236: 3988 ; PPC64LE: # %bb.0: 3989 ; PPC64LE-NEXT: mr 5, 3 3990 ; PPC64LE-NEXT: .LBB236_1: 3991 ; PPC64LE-NEXT: ldarx 3, 0, 5 3992 ; PPC64LE-NEXT: or 6, 4, 3 3993 ; PPC64LE-NEXT: stdcx. 6, 0, 5 3994 ; PPC64LE-NEXT: bne 0, .LBB236_1 3995 ; PPC64LE-NEXT: # %bb.2: 3996 ; PPC64LE-NEXT: lwsync 3997 ; PPC64LE-NEXT: blr 3998 %ret = atomicrmw or i64* %ptr, i64 %val acquire 3999 ret i64 %ret 4000 } 4001 4002 define i64 @test237(i64* %ptr, i64 %val) { 4003 ; PPC64LE-LABEL: test237: 4004 ; PPC64LE: # %bb.0: 4005 ; PPC64LE-NEXT: lwsync 4006 ; PPC64LE-NEXT: .LBB237_1: 4007 ; PPC64LE-NEXT: ldarx 5, 0, 3 4008 ; PPC64LE-NEXT: or 6, 4, 5 4009 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4010 ; PPC64LE-NEXT: bne 0, .LBB237_1 4011 ; PPC64LE-NEXT: # %bb.2: 4012 ; PPC64LE-NEXT: mr 3, 5 4013 ; PPC64LE-NEXT: blr 4014 %ret = atomicrmw or i64* %ptr, i64 %val release 4015 ret i64 %ret 4016 } 4017 4018 define i64 @test238(i64* %ptr, i64 %val) { 4019 ; PPC64LE-LABEL: test238: 4020 ; PPC64LE: # %bb.0: 4021 ; PPC64LE-NEXT: lwsync 4022 ; PPC64LE-NEXT: .LBB238_1: 4023 ; PPC64LE-NEXT: ldarx 5, 0, 3 4024 ; PPC64LE-NEXT: or 6, 4, 5 4025 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4026 ; PPC64LE-NEXT: bne 0, .LBB238_1 4027 ; PPC64LE-NEXT: # %bb.2: 4028 ; PPC64LE-NEXT: mr 3, 5 4029 ; PPC64LE-NEXT: lwsync 4030 ; PPC64LE-NEXT: blr 4031 %ret = atomicrmw or i64* %ptr, i64 %val acq_rel 4032 ret i64 %ret 4033 } 4034 4035 define i64 @test239(i64* %ptr, i64 %val) { 4036 ; PPC64LE-LABEL: test239: 4037 ; PPC64LE: # %bb.0: 4038 ; PPC64LE-NEXT: sync 4039 ; PPC64LE-NEXT: .LBB239_1: 4040 ; PPC64LE-NEXT: ldarx 5, 0, 3 4041 ; PPC64LE-NEXT: or 6, 4, 5 4042 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4043 ; PPC64LE-NEXT: bne 0, .LBB239_1 4044 ; PPC64LE-NEXT: # %bb.2: 4045 ; PPC64LE-NEXT: mr 3, 5 4046 ; PPC64LE-NEXT: lwsync 4047 ; PPC64LE-NEXT: blr 4048 %ret = atomicrmw or i64* %ptr, i64 %val seq_cst 4049 ret i64 %ret 4050 } 4051 4052 define i8 @test240(i8* %ptr, i8 %val) { 4053 ; PPC64LE-LABEL: test240: 4054 ; PPC64LE: # %bb.0: 4055 ; PPC64LE-NEXT: .LBB240_1: 4056 ; PPC64LE-NEXT: lbarx 5, 0, 3 4057 ; PPC64LE-NEXT: xor 6, 4, 5 4058 ; PPC64LE-NEXT: stbcx. 6, 0, 3 4059 ; PPC64LE-NEXT: bne 0, .LBB240_1 4060 ; PPC64LE-NEXT: # %bb.2: 4061 ; PPC64LE-NEXT: mr 3, 5 4062 ; PPC64LE-NEXT: blr 4063 %ret = atomicrmw xor i8* %ptr, i8 %val monotonic 4064 ret i8 %ret 4065 } 4066 4067 define i8 @test241(i8* %ptr, i8 %val) { 4068 ; PPC64LE-LABEL: test241: 4069 ; PPC64LE: # %bb.0: 4070 ; PPC64LE-NEXT: mr 5, 3 4071 ; PPC64LE-NEXT: .LBB241_1: 4072 ; PPC64LE-NEXT: lbarx 3, 0, 5 4073 ; PPC64LE-NEXT: xor 6, 4, 3 4074 ; PPC64LE-NEXT: stbcx. 6, 0, 5 4075 ; PPC64LE-NEXT: bne 0, .LBB241_1 4076 ; PPC64LE-NEXT: # %bb.2: 4077 ; PPC64LE-NEXT: lwsync 4078 ; PPC64LE-NEXT: blr 4079 %ret = atomicrmw xor i8* %ptr, i8 %val acquire 4080 ret i8 %ret 4081 } 4082 4083 define i8 @test242(i8* %ptr, i8 %val) { 4084 ; PPC64LE-LABEL: test242: 4085 ; PPC64LE: # %bb.0: 4086 ; PPC64LE-NEXT: lwsync 4087 ; PPC64LE-NEXT: .LBB242_1: 4088 ; PPC64LE-NEXT: lbarx 5, 0, 3 4089 ; PPC64LE-NEXT: xor 6, 4, 5 4090 ; PPC64LE-NEXT: stbcx. 6, 0, 3 4091 ; PPC64LE-NEXT: bne 0, .LBB242_1 4092 ; PPC64LE-NEXT: # %bb.2: 4093 ; PPC64LE-NEXT: mr 3, 5 4094 ; PPC64LE-NEXT: blr 4095 %ret = atomicrmw xor i8* %ptr, i8 %val release 4096 ret i8 %ret 4097 } 4098 4099 define i8 @test243(i8* %ptr, i8 %val) { 4100 ; PPC64LE-LABEL: test243: 4101 ; PPC64LE: # %bb.0: 4102 ; PPC64LE-NEXT: lwsync 4103 ; PPC64LE-NEXT: .LBB243_1: 4104 ; PPC64LE-NEXT: lbarx 5, 0, 3 4105 ; PPC64LE-NEXT: xor 6, 4, 5 4106 ; PPC64LE-NEXT: stbcx. 6, 0, 3 4107 ; PPC64LE-NEXT: bne 0, .LBB243_1 4108 ; PPC64LE-NEXT: # %bb.2: 4109 ; PPC64LE-NEXT: mr 3, 5 4110 ; PPC64LE-NEXT: lwsync 4111 ; PPC64LE-NEXT: blr 4112 %ret = atomicrmw xor i8* %ptr, i8 %val acq_rel 4113 ret i8 %ret 4114 } 4115 4116 define i8 @test244(i8* %ptr, i8 %val) { 4117 ; PPC64LE-LABEL: test244: 4118 ; PPC64LE: # %bb.0: 4119 ; PPC64LE-NEXT: sync 4120 ; PPC64LE-NEXT: .LBB244_1: 4121 ; PPC64LE-NEXT: lbarx 5, 0, 3 4122 ; PPC64LE-NEXT: xor 6, 4, 5 4123 ; PPC64LE-NEXT: stbcx. 6, 0, 3 4124 ; PPC64LE-NEXT: bne 0, .LBB244_1 4125 ; PPC64LE-NEXT: # %bb.2: 4126 ; PPC64LE-NEXT: mr 3, 5 4127 ; PPC64LE-NEXT: lwsync 4128 ; PPC64LE-NEXT: blr 4129 %ret = atomicrmw xor i8* %ptr, i8 %val seq_cst 4130 ret i8 %ret 4131 } 4132 4133 define i16 @test245(i16* %ptr, i16 %val) { 4134 ; PPC64LE-LABEL: test245: 4135 ; PPC64LE: # %bb.0: 4136 ; PPC64LE-NEXT: .LBB245_1: 4137 ; PPC64LE-NEXT: lharx 5, 0, 3 4138 ; PPC64LE-NEXT: xor 6, 4, 5 4139 ; PPC64LE-NEXT: sthcx. 6, 0, 3 4140 ; PPC64LE-NEXT: bne 0, .LBB245_1 4141 ; PPC64LE-NEXT: # %bb.2: 4142 ; PPC64LE-NEXT: mr 3, 5 4143 ; PPC64LE-NEXT: blr 4144 %ret = atomicrmw xor i16* %ptr, i16 %val monotonic 4145 ret i16 %ret 4146 } 4147 4148 define i16 @test246(i16* %ptr, i16 %val) { 4149 ; PPC64LE-LABEL: test246: 4150 ; PPC64LE: # %bb.0: 4151 ; PPC64LE-NEXT: mr 5, 3 4152 ; PPC64LE-NEXT: .LBB246_1: 4153 ; PPC64LE-NEXT: lharx 3, 0, 5 4154 ; PPC64LE-NEXT: xor 6, 4, 3 4155 ; PPC64LE-NEXT: sthcx. 6, 0, 5 4156 ; PPC64LE-NEXT: bne 0, .LBB246_1 4157 ; PPC64LE-NEXT: # %bb.2: 4158 ; PPC64LE-NEXT: lwsync 4159 ; PPC64LE-NEXT: blr 4160 %ret = atomicrmw xor i16* %ptr, i16 %val acquire 4161 ret i16 %ret 4162 } 4163 4164 define i16 @test247(i16* %ptr, i16 %val) { 4165 ; PPC64LE-LABEL: test247: 4166 ; PPC64LE: # %bb.0: 4167 ; PPC64LE-NEXT: lwsync 4168 ; PPC64LE-NEXT: .LBB247_1: 4169 ; PPC64LE-NEXT: lharx 5, 0, 3 4170 ; PPC64LE-NEXT: xor 6, 4, 5 4171 ; PPC64LE-NEXT: sthcx. 6, 0, 3 4172 ; PPC64LE-NEXT: bne 0, .LBB247_1 4173 ; PPC64LE-NEXT: # %bb.2: 4174 ; PPC64LE-NEXT: mr 3, 5 4175 ; PPC64LE-NEXT: blr 4176 %ret = atomicrmw xor i16* %ptr, i16 %val release 4177 ret i16 %ret 4178 } 4179 4180 define i16 @test248(i16* %ptr, i16 %val) { 4181 ; PPC64LE-LABEL: test248: 4182 ; PPC64LE: # %bb.0: 4183 ; PPC64LE-NEXT: lwsync 4184 ; PPC64LE-NEXT: .LBB248_1: 4185 ; PPC64LE-NEXT: lharx 5, 0, 3 4186 ; PPC64LE-NEXT: xor 6, 4, 5 4187 ; PPC64LE-NEXT: sthcx. 6, 0, 3 4188 ; PPC64LE-NEXT: bne 0, .LBB248_1 4189 ; PPC64LE-NEXT: # %bb.2: 4190 ; PPC64LE-NEXT: mr 3, 5 4191 ; PPC64LE-NEXT: lwsync 4192 ; PPC64LE-NEXT: blr 4193 %ret = atomicrmw xor i16* %ptr, i16 %val acq_rel 4194 ret i16 %ret 4195 } 4196 4197 define i16 @test249(i16* %ptr, i16 %val) { 4198 ; PPC64LE-LABEL: test249: 4199 ; PPC64LE: # %bb.0: 4200 ; PPC64LE-NEXT: sync 4201 ; PPC64LE-NEXT: .LBB249_1: 4202 ; PPC64LE-NEXT: lharx 5, 0, 3 4203 ; PPC64LE-NEXT: xor 6, 4, 5 4204 ; PPC64LE-NEXT: sthcx. 6, 0, 3 4205 ; PPC64LE-NEXT: bne 0, .LBB249_1 4206 ; PPC64LE-NEXT: # %bb.2: 4207 ; PPC64LE-NEXT: mr 3, 5 4208 ; PPC64LE-NEXT: lwsync 4209 ; PPC64LE-NEXT: blr 4210 %ret = atomicrmw xor i16* %ptr, i16 %val seq_cst 4211 ret i16 %ret 4212 } 4213 4214 define i32 @test250(i32* %ptr, i32 %val) { 4215 ; PPC64LE-LABEL: test250: 4216 ; PPC64LE: # %bb.0: 4217 ; PPC64LE-NEXT: .LBB250_1: 4218 ; PPC64LE-NEXT: lwarx 5, 0, 3 4219 ; PPC64LE-NEXT: xor 6, 4, 5 4220 ; PPC64LE-NEXT: stwcx. 6, 0, 3 4221 ; PPC64LE-NEXT: bne 0, .LBB250_1 4222 ; PPC64LE-NEXT: # %bb.2: 4223 ; PPC64LE-NEXT: mr 3, 5 4224 ; PPC64LE-NEXT: blr 4225 %ret = atomicrmw xor i32* %ptr, i32 %val monotonic 4226 ret i32 %ret 4227 } 4228 4229 define i32 @test251(i32* %ptr, i32 %val) { 4230 ; PPC64LE-LABEL: test251: 4231 ; PPC64LE: # %bb.0: 4232 ; PPC64LE-NEXT: mr 5, 3 4233 ; PPC64LE-NEXT: .LBB251_1: 4234 ; PPC64LE-NEXT: lwarx 3, 0, 5 4235 ; PPC64LE-NEXT: xor 6, 4, 3 4236 ; PPC64LE-NEXT: stwcx. 6, 0, 5 4237 ; PPC64LE-NEXT: bne 0, .LBB251_1 4238 ; PPC64LE-NEXT: # %bb.2: 4239 ; PPC64LE-NEXT: lwsync 4240 ; PPC64LE-NEXT: blr 4241 %ret = atomicrmw xor i32* %ptr, i32 %val acquire 4242 ret i32 %ret 4243 } 4244 4245 define i32 @test252(i32* %ptr, i32 %val) { 4246 ; PPC64LE-LABEL: test252: 4247 ; PPC64LE: # %bb.0: 4248 ; PPC64LE-NEXT: lwsync 4249 ; PPC64LE-NEXT: .LBB252_1: 4250 ; PPC64LE-NEXT: lwarx 5, 0, 3 4251 ; PPC64LE-NEXT: xor 6, 4, 5 4252 ; PPC64LE-NEXT: stwcx. 6, 0, 3 4253 ; PPC64LE-NEXT: bne 0, .LBB252_1 4254 ; PPC64LE-NEXT: # %bb.2: 4255 ; PPC64LE-NEXT: mr 3, 5 4256 ; PPC64LE-NEXT: blr 4257 %ret = atomicrmw xor i32* %ptr, i32 %val release 4258 ret i32 %ret 4259 } 4260 4261 define i32 @test253(i32* %ptr, i32 %val) { 4262 ; PPC64LE-LABEL: test253: 4263 ; PPC64LE: # %bb.0: 4264 ; PPC64LE-NEXT: lwsync 4265 ; PPC64LE-NEXT: .LBB253_1: 4266 ; PPC64LE-NEXT: lwarx 5, 0, 3 4267 ; PPC64LE-NEXT: xor 6, 4, 5 4268 ; PPC64LE-NEXT: stwcx. 6, 0, 3 4269 ; PPC64LE-NEXT: bne 0, .LBB253_1 4270 ; PPC64LE-NEXT: # %bb.2: 4271 ; PPC64LE-NEXT: mr 3, 5 4272 ; PPC64LE-NEXT: lwsync 4273 ; PPC64LE-NEXT: blr 4274 %ret = atomicrmw xor i32* %ptr, i32 %val acq_rel 4275 ret i32 %ret 4276 } 4277 4278 define i32 @test254(i32* %ptr, i32 %val) { 4279 ; PPC64LE-LABEL: test254: 4280 ; PPC64LE: # %bb.0: 4281 ; PPC64LE-NEXT: sync 4282 ; PPC64LE-NEXT: .LBB254_1: 4283 ; PPC64LE-NEXT: lwarx 5, 0, 3 4284 ; PPC64LE-NEXT: xor 6, 4, 5 4285 ; PPC64LE-NEXT: stwcx. 6, 0, 3 4286 ; PPC64LE-NEXT: bne 0, .LBB254_1 4287 ; PPC64LE-NEXT: # %bb.2: 4288 ; PPC64LE-NEXT: mr 3, 5 4289 ; PPC64LE-NEXT: lwsync 4290 ; PPC64LE-NEXT: blr 4291 %ret = atomicrmw xor i32* %ptr, i32 %val seq_cst 4292 ret i32 %ret 4293 } 4294 4295 define i64 @test255(i64* %ptr, i64 %val) { 4296 ; PPC64LE-LABEL: test255: 4297 ; PPC64LE: # %bb.0: 4298 ; PPC64LE-NEXT: .LBB255_1: 4299 ; PPC64LE-NEXT: ldarx 5, 0, 3 4300 ; PPC64LE-NEXT: xor 6, 4, 5 4301 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4302 ; PPC64LE-NEXT: bne 0, .LBB255_1 4303 ; PPC64LE-NEXT: # %bb.2: 4304 ; PPC64LE-NEXT: mr 3, 5 4305 ; PPC64LE-NEXT: blr 4306 %ret = atomicrmw xor i64* %ptr, i64 %val monotonic 4307 ret i64 %ret 4308 } 4309 4310 define i64 @test256(i64* %ptr, i64 %val) { 4311 ; PPC64LE-LABEL: test256: 4312 ; PPC64LE: # %bb.0: 4313 ; PPC64LE-NEXT: mr 5, 3 4314 ; PPC64LE-NEXT: .LBB256_1: 4315 ; PPC64LE-NEXT: ldarx 3, 0, 5 4316 ; PPC64LE-NEXT: xor 6, 4, 3 4317 ; PPC64LE-NEXT: stdcx. 6, 0, 5 4318 ; PPC64LE-NEXT: bne 0, .LBB256_1 4319 ; PPC64LE-NEXT: # %bb.2: 4320 ; PPC64LE-NEXT: lwsync 4321 ; PPC64LE-NEXT: blr 4322 %ret = atomicrmw xor i64* %ptr, i64 %val acquire 4323 ret i64 %ret 4324 } 4325 4326 define i64 @test257(i64* %ptr, i64 %val) { 4327 ; PPC64LE-LABEL: test257: 4328 ; PPC64LE: # %bb.0: 4329 ; PPC64LE-NEXT: lwsync 4330 ; PPC64LE-NEXT: .LBB257_1: 4331 ; PPC64LE-NEXT: ldarx 5, 0, 3 4332 ; PPC64LE-NEXT: xor 6, 4, 5 4333 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4334 ; PPC64LE-NEXT: bne 0, .LBB257_1 4335 ; PPC64LE-NEXT: # %bb.2: 4336 ; PPC64LE-NEXT: mr 3, 5 4337 ; PPC64LE-NEXT: blr 4338 %ret = atomicrmw xor i64* %ptr, i64 %val release 4339 ret i64 %ret 4340 } 4341 4342 define i64 @test258(i64* %ptr, i64 %val) { 4343 ; PPC64LE-LABEL: test258: 4344 ; PPC64LE: # %bb.0: 4345 ; PPC64LE-NEXT: lwsync 4346 ; PPC64LE-NEXT: .LBB258_1: 4347 ; PPC64LE-NEXT: ldarx 5, 0, 3 4348 ; PPC64LE-NEXT: xor 6, 4, 5 4349 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4350 ; PPC64LE-NEXT: bne 0, .LBB258_1 4351 ; PPC64LE-NEXT: # %bb.2: 4352 ; PPC64LE-NEXT: mr 3, 5 4353 ; PPC64LE-NEXT: lwsync 4354 ; PPC64LE-NEXT: blr 4355 %ret = atomicrmw xor i64* %ptr, i64 %val acq_rel 4356 ret i64 %ret 4357 } 4358 4359 define i64 @test259(i64* %ptr, i64 %val) { 4360 ; PPC64LE-LABEL: test259: 4361 ; PPC64LE: # %bb.0: 4362 ; PPC64LE-NEXT: sync 4363 ; PPC64LE-NEXT: .LBB259_1: 4364 ; PPC64LE-NEXT: ldarx 5, 0, 3 4365 ; PPC64LE-NEXT: xor 6, 4, 5 4366 ; PPC64LE-NEXT: stdcx. 6, 0, 3 4367 ; PPC64LE-NEXT: bne 0, .LBB259_1 4368 ; PPC64LE-NEXT: # %bb.2: 4369 ; PPC64LE-NEXT: mr 3, 5 4370 ; PPC64LE-NEXT: lwsync 4371 ; PPC64LE-NEXT: blr 4372 %ret = atomicrmw xor i64* %ptr, i64 %val seq_cst 4373 ret i64 %ret 4374 } 4375 4376 define i8 @test260(i8* %ptr, i8 %val) { 4377 ; PPC64LE-LABEL: test260: 4378 ; PPC64LE: # %bb.0: 4379 ; PPC64LE-NEXT: .LBB260_1: 4380 ; PPC64LE-NEXT: lbarx 5, 0, 3 4381 ; PPC64LE-NEXT: extsb 6, 5 4382 ; PPC64LE-NEXT: cmpw 4, 6 4383 ; PPC64LE-NEXT: ble 0, .LBB260_3 4384 ; PPC64LE-NEXT: # %bb.2: 4385 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4386 ; PPC64LE-NEXT: bne 0, .LBB260_1 4387 ; PPC64LE-NEXT: .LBB260_3: 4388 ; PPC64LE-NEXT: mr 3, 5 4389 ; PPC64LE-NEXT: blr 4390 %ret = atomicrmw max i8* %ptr, i8 %val monotonic 4391 ret i8 %ret 4392 } 4393 4394 define i8 @test261(i8* %ptr, i8 %val) { 4395 ; PPC64LE-LABEL: test261: 4396 ; PPC64LE: # %bb.0: 4397 ; PPC64LE-NEXT: mr 5, 3 4398 ; PPC64LE-NEXT: .LBB261_1: 4399 ; PPC64LE-NEXT: lbarx 3, 0, 5 4400 ; PPC64LE-NEXT: extsb 6, 3 4401 ; PPC64LE-NEXT: cmpw 4, 6 4402 ; PPC64LE-NEXT: ble 0, .LBB261_3 4403 ; PPC64LE-NEXT: # %bb.2: 4404 ; PPC64LE-NEXT: stbcx. 4, 0, 5 4405 ; PPC64LE-NEXT: bne 0, .LBB261_1 4406 ; PPC64LE-NEXT: .LBB261_3: 4407 ; PPC64LE-NEXT: lwsync 4408 ; PPC64LE-NEXT: blr 4409 %ret = atomicrmw max i8* %ptr, i8 %val acquire 4410 ret i8 %ret 4411 } 4412 4413 define i8 @test262(i8* %ptr, i8 %val) { 4414 ; PPC64LE-LABEL: test262: 4415 ; PPC64LE: # %bb.0: 4416 ; PPC64LE-NEXT: lwsync 4417 ; PPC64LE-NEXT: .LBB262_1: 4418 ; PPC64LE-NEXT: lbarx 5, 0, 3 4419 ; PPC64LE-NEXT: extsb 6, 5 4420 ; PPC64LE-NEXT: cmpw 4, 6 4421 ; PPC64LE-NEXT: ble 0, .LBB262_3 4422 ; PPC64LE-NEXT: # %bb.2: 4423 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4424 ; PPC64LE-NEXT: bne 0, .LBB262_1 4425 ; PPC64LE-NEXT: .LBB262_3: 4426 ; PPC64LE-NEXT: mr 3, 5 4427 ; PPC64LE-NEXT: blr 4428 %ret = atomicrmw max i8* %ptr, i8 %val release 4429 ret i8 %ret 4430 } 4431 4432 define i8 @test263(i8* %ptr, i8 %val) { 4433 ; PPC64LE-LABEL: test263: 4434 ; PPC64LE: # %bb.0: 4435 ; PPC64LE-NEXT: lwsync 4436 ; PPC64LE-NEXT: .LBB263_1: 4437 ; PPC64LE-NEXT: lbarx 5, 0, 3 4438 ; PPC64LE-NEXT: extsb 6, 5 4439 ; PPC64LE-NEXT: cmpw 4, 6 4440 ; PPC64LE-NEXT: ble 0, .LBB263_3 4441 ; PPC64LE-NEXT: # %bb.2: 4442 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4443 ; PPC64LE-NEXT: bne 0, .LBB263_1 4444 ; PPC64LE-NEXT: .LBB263_3: 4445 ; PPC64LE-NEXT: mr 3, 5 4446 ; PPC64LE-NEXT: lwsync 4447 ; PPC64LE-NEXT: blr 4448 %ret = atomicrmw max i8* %ptr, i8 %val acq_rel 4449 ret i8 %ret 4450 } 4451 4452 define i8 @test264(i8* %ptr, i8 %val) { 4453 ; PPC64LE-LABEL: test264: 4454 ; PPC64LE: # %bb.0: 4455 ; PPC64LE-NEXT: sync 4456 ; PPC64LE-NEXT: .LBB264_1: 4457 ; PPC64LE-NEXT: lbarx 5, 0, 3 4458 ; PPC64LE-NEXT: extsb 6, 5 4459 ; PPC64LE-NEXT: cmpw 4, 6 4460 ; PPC64LE-NEXT: ble 0, .LBB264_3 4461 ; PPC64LE-NEXT: # %bb.2: 4462 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4463 ; PPC64LE-NEXT: bne 0, .LBB264_1 4464 ; PPC64LE-NEXT: .LBB264_3: 4465 ; PPC64LE-NEXT: mr 3, 5 4466 ; PPC64LE-NEXT: lwsync 4467 ; PPC64LE-NEXT: blr 4468 %ret = atomicrmw max i8* %ptr, i8 %val seq_cst 4469 ret i8 %ret 4470 } 4471 4472 define i16 @test265(i16* %ptr, i16 %val) { 4473 ; PPC64LE-LABEL: test265: 4474 ; PPC64LE: # %bb.0: 4475 ; PPC64LE-NEXT: .LBB265_1: 4476 ; PPC64LE-NEXT: lharx 5, 0, 3 4477 ; PPC64LE-NEXT: extsh 6, 5 4478 ; PPC64LE-NEXT: cmpw 4, 6 4479 ; PPC64LE-NEXT: ble 0, .LBB265_3 4480 ; PPC64LE-NEXT: # %bb.2: 4481 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4482 ; PPC64LE-NEXT: bne 0, .LBB265_1 4483 ; PPC64LE-NEXT: .LBB265_3: 4484 ; PPC64LE-NEXT: mr 3, 5 4485 ; PPC64LE-NEXT: blr 4486 %ret = atomicrmw max i16* %ptr, i16 %val monotonic 4487 ret i16 %ret 4488 } 4489 4490 define i16 @test266(i16* %ptr, i16 %val) { 4491 ; PPC64LE-LABEL: test266: 4492 ; PPC64LE: # %bb.0: 4493 ; PPC64LE-NEXT: mr 5, 3 4494 ; PPC64LE-NEXT: .LBB266_1: 4495 ; PPC64LE-NEXT: lharx 3, 0, 5 4496 ; PPC64LE-NEXT: extsh 6, 3 4497 ; PPC64LE-NEXT: cmpw 4, 6 4498 ; PPC64LE-NEXT: ble 0, .LBB266_3 4499 ; PPC64LE-NEXT: # %bb.2: 4500 ; PPC64LE-NEXT: sthcx. 4, 0, 5 4501 ; PPC64LE-NEXT: bne 0, .LBB266_1 4502 ; PPC64LE-NEXT: .LBB266_3: 4503 ; PPC64LE-NEXT: lwsync 4504 ; PPC64LE-NEXT: blr 4505 %ret = atomicrmw max i16* %ptr, i16 %val acquire 4506 ret i16 %ret 4507 } 4508 4509 define i16 @test267(i16* %ptr, i16 %val) { 4510 ; PPC64LE-LABEL: test267: 4511 ; PPC64LE: # %bb.0: 4512 ; PPC64LE-NEXT: lwsync 4513 ; PPC64LE-NEXT: .LBB267_1: 4514 ; PPC64LE-NEXT: lharx 5, 0, 3 4515 ; PPC64LE-NEXT: extsh 6, 5 4516 ; PPC64LE-NEXT: cmpw 4, 6 4517 ; PPC64LE-NEXT: ble 0, .LBB267_3 4518 ; PPC64LE-NEXT: # %bb.2: 4519 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4520 ; PPC64LE-NEXT: bne 0, .LBB267_1 4521 ; PPC64LE-NEXT: .LBB267_3: 4522 ; PPC64LE-NEXT: mr 3, 5 4523 ; PPC64LE-NEXT: blr 4524 %ret = atomicrmw max i16* %ptr, i16 %val release 4525 ret i16 %ret 4526 } 4527 4528 define i16 @test268(i16* %ptr, i16 %val) { 4529 ; PPC64LE-LABEL: test268: 4530 ; PPC64LE: # %bb.0: 4531 ; PPC64LE-NEXT: lwsync 4532 ; PPC64LE-NEXT: .LBB268_1: 4533 ; PPC64LE-NEXT: lharx 5, 0, 3 4534 ; PPC64LE-NEXT: extsh 6, 5 4535 ; PPC64LE-NEXT: cmpw 4, 6 4536 ; PPC64LE-NEXT: ble 0, .LBB268_3 4537 ; PPC64LE-NEXT: # %bb.2: 4538 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4539 ; PPC64LE-NEXT: bne 0, .LBB268_1 4540 ; PPC64LE-NEXT: .LBB268_3: 4541 ; PPC64LE-NEXT: mr 3, 5 4542 ; PPC64LE-NEXT: lwsync 4543 ; PPC64LE-NEXT: blr 4544 %ret = atomicrmw max i16* %ptr, i16 %val acq_rel 4545 ret i16 %ret 4546 } 4547 4548 define i16 @test269(i16* %ptr, i16 %val) { 4549 ; PPC64LE-LABEL: test269: 4550 ; PPC64LE: # %bb.0: 4551 ; PPC64LE-NEXT: sync 4552 ; PPC64LE-NEXT: .LBB269_1: 4553 ; PPC64LE-NEXT: lharx 5, 0, 3 4554 ; PPC64LE-NEXT: extsh 6, 5 4555 ; PPC64LE-NEXT: cmpw 4, 6 4556 ; PPC64LE-NEXT: ble 0, .LBB269_3 4557 ; PPC64LE-NEXT: # %bb.2: 4558 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4559 ; PPC64LE-NEXT: bne 0, .LBB269_1 4560 ; PPC64LE-NEXT: .LBB269_3: 4561 ; PPC64LE-NEXT: mr 3, 5 4562 ; PPC64LE-NEXT: lwsync 4563 ; PPC64LE-NEXT: blr 4564 %ret = atomicrmw max i16* %ptr, i16 %val seq_cst 4565 ret i16 %ret 4566 } 4567 4568 define i32 @test270(i32* %ptr, i32 %val) { 4569 ; PPC64LE-LABEL: test270: 4570 ; PPC64LE: # %bb.0: 4571 ; PPC64LE-NEXT: .LBB270_1: 4572 ; PPC64LE-NEXT: lwarx 5, 0, 3 4573 ; PPC64LE-NEXT: cmpw 4, 5 4574 ; PPC64LE-NEXT: ble 0, .LBB270_3 4575 ; PPC64LE-NEXT: # %bb.2: 4576 ; PPC64LE-NEXT: stwcx. 4, 0, 3 4577 ; PPC64LE-NEXT: bne 0, .LBB270_1 4578 ; PPC64LE-NEXT: .LBB270_3: 4579 ; PPC64LE-NEXT: mr 3, 5 4580 ; PPC64LE-NEXT: blr 4581 %ret = atomicrmw max i32* %ptr, i32 %val monotonic 4582 ret i32 %ret 4583 } 4584 4585 define i32 @test271(i32* %ptr, i32 %val) { 4586 ; PPC64LE-LABEL: test271: 4587 ; PPC64LE: # %bb.0: 4588 ; PPC64LE-NEXT: mr 5, 3 4589 ; PPC64LE-NEXT: .LBB271_1: 4590 ; PPC64LE-NEXT: lwarx 3, 0, 5 4591 ; PPC64LE-NEXT: cmpw 4, 3 4592 ; PPC64LE-NEXT: ble 0, .LBB271_3 4593 ; PPC64LE-NEXT: # %bb.2: 4594 ; PPC64LE-NEXT: stwcx. 4, 0, 5 4595 ; PPC64LE-NEXT: bne 0, .LBB271_1 4596 ; PPC64LE-NEXT: .LBB271_3: 4597 ; PPC64LE-NEXT: lwsync 4598 ; PPC64LE-NEXT: blr 4599 %ret = atomicrmw max i32* %ptr, i32 %val acquire 4600 ret i32 %ret 4601 } 4602 4603 define i32 @test272(i32* %ptr, i32 %val) { 4604 ; PPC64LE-LABEL: test272: 4605 ; PPC64LE: # %bb.0: 4606 ; PPC64LE-NEXT: lwsync 4607 ; PPC64LE-NEXT: .LBB272_1: 4608 ; PPC64LE-NEXT: lwarx 5, 0, 3 4609 ; PPC64LE-NEXT: cmpw 4, 5 4610 ; PPC64LE-NEXT: ble 0, .LBB272_3 4611 ; PPC64LE-NEXT: # %bb.2: 4612 ; PPC64LE-NEXT: stwcx. 4, 0, 3 4613 ; PPC64LE-NEXT: bne 0, .LBB272_1 4614 ; PPC64LE-NEXT: .LBB272_3: 4615 ; PPC64LE-NEXT: mr 3, 5 4616 ; PPC64LE-NEXT: blr 4617 %ret = atomicrmw max i32* %ptr, i32 %val release 4618 ret i32 %ret 4619 } 4620 4621 define i32 @test273(i32* %ptr, i32 %val) { 4622 ; PPC64LE-LABEL: test273: 4623 ; PPC64LE: # %bb.0: 4624 ; PPC64LE-NEXT: lwsync 4625 ; PPC64LE-NEXT: .LBB273_1: 4626 ; PPC64LE-NEXT: lwarx 5, 0, 3 4627 ; PPC64LE-NEXT: cmpw 4, 5 4628 ; PPC64LE-NEXT: ble 0, .LBB273_3 4629 ; PPC64LE-NEXT: # %bb.2: 4630 ; PPC64LE-NEXT: stwcx. 4, 0, 3 4631 ; PPC64LE-NEXT: bne 0, .LBB273_1 4632 ; PPC64LE-NEXT: .LBB273_3: 4633 ; PPC64LE-NEXT: mr 3, 5 4634 ; PPC64LE-NEXT: lwsync 4635 ; PPC64LE-NEXT: blr 4636 %ret = atomicrmw max i32* %ptr, i32 %val acq_rel 4637 ret i32 %ret 4638 } 4639 4640 define i32 @test274(i32* %ptr, i32 %val) { 4641 ; PPC64LE-LABEL: test274: 4642 ; PPC64LE: # %bb.0: 4643 ; PPC64LE-NEXT: sync 4644 ; PPC64LE-NEXT: .LBB274_1: 4645 ; PPC64LE-NEXT: lwarx 5, 0, 3 4646 ; PPC64LE-NEXT: cmpw 4, 5 4647 ; PPC64LE-NEXT: ble 0, .LBB274_3 4648 ; PPC64LE-NEXT: # %bb.2: 4649 ; PPC64LE-NEXT: stwcx. 4, 0, 3 4650 ; PPC64LE-NEXT: bne 0, .LBB274_1 4651 ; PPC64LE-NEXT: .LBB274_3: 4652 ; PPC64LE-NEXT: mr 3, 5 4653 ; PPC64LE-NEXT: lwsync 4654 ; PPC64LE-NEXT: blr 4655 %ret = atomicrmw max i32* %ptr, i32 %val seq_cst 4656 ret i32 %ret 4657 } 4658 4659 define i64 @test275(i64* %ptr, i64 %val) { 4660 ; PPC64LE-LABEL: test275: 4661 ; PPC64LE: # %bb.0: 4662 ; PPC64LE-NEXT: .LBB275_1: 4663 ; PPC64LE-NEXT: ldarx 5, 0, 3 4664 ; PPC64LE-NEXT: cmpd 4, 5 4665 ; PPC64LE-NEXT: ble 0, .LBB275_3 4666 ; PPC64LE-NEXT: # %bb.2: 4667 ; PPC64LE-NEXT: stdcx. 4, 0, 3 4668 ; PPC64LE-NEXT: bne 0, .LBB275_1 4669 ; PPC64LE-NEXT: .LBB275_3: 4670 ; PPC64LE-NEXT: mr 3, 5 4671 ; PPC64LE-NEXT: blr 4672 %ret = atomicrmw max i64* %ptr, i64 %val monotonic 4673 ret i64 %ret 4674 } 4675 4676 define i64 @test276(i64* %ptr, i64 %val) { 4677 ; PPC64LE-LABEL: test276: 4678 ; PPC64LE: # %bb.0: 4679 ; PPC64LE-NEXT: mr 5, 3 4680 ; PPC64LE-NEXT: .LBB276_1: 4681 ; PPC64LE-NEXT: ldarx 3, 0, 5 4682 ; PPC64LE-NEXT: cmpd 4, 3 4683 ; PPC64LE-NEXT: ble 0, .LBB276_3 4684 ; PPC64LE-NEXT: # %bb.2: 4685 ; PPC64LE-NEXT: stdcx. 4, 0, 5 4686 ; PPC64LE-NEXT: bne 0, .LBB276_1 4687 ; PPC64LE-NEXT: .LBB276_3: 4688 ; PPC64LE-NEXT: lwsync 4689 ; PPC64LE-NEXT: blr 4690 %ret = atomicrmw max i64* %ptr, i64 %val acquire 4691 ret i64 %ret 4692 } 4693 4694 define i64 @test277(i64* %ptr, i64 %val) { 4695 ; PPC64LE-LABEL: test277: 4696 ; PPC64LE: # %bb.0: 4697 ; PPC64LE-NEXT: lwsync 4698 ; PPC64LE-NEXT: .LBB277_1: 4699 ; PPC64LE-NEXT: ldarx 5, 0, 3 4700 ; PPC64LE-NEXT: cmpd 4, 5 4701 ; PPC64LE-NEXT: ble 0, .LBB277_3 4702 ; PPC64LE-NEXT: # %bb.2: 4703 ; PPC64LE-NEXT: stdcx. 4, 0, 3 4704 ; PPC64LE-NEXT: bne 0, .LBB277_1 4705 ; PPC64LE-NEXT: .LBB277_3: 4706 ; PPC64LE-NEXT: mr 3, 5 4707 ; PPC64LE-NEXT: blr 4708 %ret = atomicrmw max i64* %ptr, i64 %val release 4709 ret i64 %ret 4710 } 4711 4712 define i64 @test278(i64* %ptr, i64 %val) { 4713 ; PPC64LE-LABEL: test278: 4714 ; PPC64LE: # %bb.0: 4715 ; PPC64LE-NEXT: lwsync 4716 ; PPC64LE-NEXT: .LBB278_1: 4717 ; PPC64LE-NEXT: ldarx 5, 0, 3 4718 ; PPC64LE-NEXT: cmpd 4, 5 4719 ; PPC64LE-NEXT: ble 0, .LBB278_3 4720 ; PPC64LE-NEXT: # %bb.2: 4721 ; PPC64LE-NEXT: stdcx. 4, 0, 3 4722 ; PPC64LE-NEXT: bne 0, .LBB278_1 4723 ; PPC64LE-NEXT: .LBB278_3: 4724 ; PPC64LE-NEXT: mr 3, 5 4725 ; PPC64LE-NEXT: lwsync 4726 ; PPC64LE-NEXT: blr 4727 %ret = atomicrmw max i64* %ptr, i64 %val acq_rel 4728 ret i64 %ret 4729 } 4730 4731 define i64 @test279(i64* %ptr, i64 %val) { 4732 ; PPC64LE-LABEL: test279: 4733 ; PPC64LE: # %bb.0: 4734 ; PPC64LE-NEXT: sync 4735 ; PPC64LE-NEXT: .LBB279_1: 4736 ; PPC64LE-NEXT: ldarx 5, 0, 3 4737 ; PPC64LE-NEXT: cmpd 4, 5 4738 ; PPC64LE-NEXT: ble 0, .LBB279_3 4739 ; PPC64LE-NEXT: # %bb.2: 4740 ; PPC64LE-NEXT: stdcx. 4, 0, 3 4741 ; PPC64LE-NEXT: bne 0, .LBB279_1 4742 ; PPC64LE-NEXT: .LBB279_3: 4743 ; PPC64LE-NEXT: mr 3, 5 4744 ; PPC64LE-NEXT: lwsync 4745 ; PPC64LE-NEXT: blr 4746 %ret = atomicrmw max i64* %ptr, i64 %val seq_cst 4747 ret i64 %ret 4748 } 4749 4750 define i8 @test280(i8* %ptr, i8 %val) { 4751 ; PPC64LE-LABEL: test280: 4752 ; PPC64LE: # %bb.0: 4753 ; PPC64LE-NEXT: .LBB280_1: 4754 ; PPC64LE-NEXT: lbarx 5, 0, 3 4755 ; PPC64LE-NEXT: extsb 6, 5 4756 ; PPC64LE-NEXT: cmpw 4, 6 4757 ; PPC64LE-NEXT: bge 0, .LBB280_3 4758 ; PPC64LE-NEXT: # %bb.2: 4759 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4760 ; PPC64LE-NEXT: bne 0, .LBB280_1 4761 ; PPC64LE-NEXT: .LBB280_3: 4762 ; PPC64LE-NEXT: mr 3, 5 4763 ; PPC64LE-NEXT: blr 4764 %ret = atomicrmw min i8* %ptr, i8 %val monotonic 4765 ret i8 %ret 4766 } 4767 4768 define i8 @test281(i8* %ptr, i8 %val) { 4769 ; PPC64LE-LABEL: test281: 4770 ; PPC64LE: # %bb.0: 4771 ; PPC64LE-NEXT: mr 5, 3 4772 ; PPC64LE-NEXT: .LBB281_1: 4773 ; PPC64LE-NEXT: lbarx 3, 0, 5 4774 ; PPC64LE-NEXT: extsb 6, 3 4775 ; PPC64LE-NEXT: cmpw 4, 6 4776 ; PPC64LE-NEXT: bge 0, .LBB281_3 4777 ; PPC64LE-NEXT: # %bb.2: 4778 ; PPC64LE-NEXT: stbcx. 4, 0, 5 4779 ; PPC64LE-NEXT: bne 0, .LBB281_1 4780 ; PPC64LE-NEXT: .LBB281_3: 4781 ; PPC64LE-NEXT: lwsync 4782 ; PPC64LE-NEXT: blr 4783 %ret = atomicrmw min i8* %ptr, i8 %val acquire 4784 ret i8 %ret 4785 } 4786 4787 define i8 @test282(i8* %ptr, i8 %val) { 4788 ; PPC64LE-LABEL: test282: 4789 ; PPC64LE: # %bb.0: 4790 ; PPC64LE-NEXT: lwsync 4791 ; PPC64LE-NEXT: .LBB282_1: 4792 ; PPC64LE-NEXT: lbarx 5, 0, 3 4793 ; PPC64LE-NEXT: extsb 6, 5 4794 ; PPC64LE-NEXT: cmpw 4, 6 4795 ; PPC64LE-NEXT: bge 0, .LBB282_3 4796 ; PPC64LE-NEXT: # %bb.2: 4797 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4798 ; PPC64LE-NEXT: bne 0, .LBB282_1 4799 ; PPC64LE-NEXT: .LBB282_3: 4800 ; PPC64LE-NEXT: mr 3, 5 4801 ; PPC64LE-NEXT: blr 4802 %ret = atomicrmw min i8* %ptr, i8 %val release 4803 ret i8 %ret 4804 } 4805 4806 define i8 @test283(i8* %ptr, i8 %val) { 4807 ; PPC64LE-LABEL: test283: 4808 ; PPC64LE: # %bb.0: 4809 ; PPC64LE-NEXT: lwsync 4810 ; PPC64LE-NEXT: .LBB283_1: 4811 ; PPC64LE-NEXT: lbarx 5, 0, 3 4812 ; PPC64LE-NEXT: extsb 6, 5 4813 ; PPC64LE-NEXT: cmpw 4, 6 4814 ; PPC64LE-NEXT: bge 0, .LBB283_3 4815 ; PPC64LE-NEXT: # %bb.2: 4816 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4817 ; PPC64LE-NEXT: bne 0, .LBB283_1 4818 ; PPC64LE-NEXT: .LBB283_3: 4819 ; PPC64LE-NEXT: mr 3, 5 4820 ; PPC64LE-NEXT: lwsync 4821 ; PPC64LE-NEXT: blr 4822 %ret = atomicrmw min i8* %ptr, i8 %val acq_rel 4823 ret i8 %ret 4824 } 4825 4826 define i8 @test284(i8* %ptr, i8 %val) { 4827 ; PPC64LE-LABEL: test284: 4828 ; PPC64LE: # %bb.0: 4829 ; PPC64LE-NEXT: sync 4830 ; PPC64LE-NEXT: .LBB284_1: 4831 ; PPC64LE-NEXT: lbarx 5, 0, 3 4832 ; PPC64LE-NEXT: extsb 6, 5 4833 ; PPC64LE-NEXT: cmpw 4, 6 4834 ; PPC64LE-NEXT: bge 0, .LBB284_3 4835 ; PPC64LE-NEXT: # %bb.2: 4836 ; PPC64LE-NEXT: stbcx. 4, 0, 3 4837 ; PPC64LE-NEXT: bne 0, .LBB284_1 4838 ; PPC64LE-NEXT: .LBB284_3: 4839 ; PPC64LE-NEXT: mr 3, 5 4840 ; PPC64LE-NEXT: lwsync 4841 ; PPC64LE-NEXT: blr 4842 %ret = atomicrmw min i8* %ptr, i8 %val seq_cst 4843 ret i8 %ret 4844 } 4845 4846 define i16 @test285(i16* %ptr, i16 %val) { 4847 ; PPC64LE-LABEL: test285: 4848 ; PPC64LE: # %bb.0: 4849 ; PPC64LE-NEXT: .LBB285_1: 4850 ; PPC64LE-NEXT: lharx 5, 0, 3 4851 ; PPC64LE-NEXT: extsh 6, 5 4852 ; PPC64LE-NEXT: cmpw 4, 6 4853 ; PPC64LE-NEXT: bge 0, .LBB285_3 4854 ; PPC64LE-NEXT: # %bb.2: 4855 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4856 ; PPC64LE-NEXT: bne 0, .LBB285_1 4857 ; PPC64LE-NEXT: .LBB285_3: 4858 ; PPC64LE-NEXT: mr 3, 5 4859 ; PPC64LE-NEXT: blr 4860 %ret = atomicrmw min i16* %ptr, i16 %val monotonic 4861 ret i16 %ret 4862 } 4863 4864 define i16 @test286(i16* %ptr, i16 %val) { 4865 ; PPC64LE-LABEL: test286: 4866 ; PPC64LE: # %bb.0: 4867 ; PPC64LE-NEXT: mr 5, 3 4868 ; PPC64LE-NEXT: .LBB286_1: 4869 ; PPC64LE-NEXT: lharx 3, 0, 5 4870 ; PPC64LE-NEXT: extsh 6, 3 4871 ; PPC64LE-NEXT: cmpw 4, 6 4872 ; PPC64LE-NEXT: bge 0, .LBB286_3 4873 ; PPC64LE-NEXT: # %bb.2: 4874 ; PPC64LE-NEXT: sthcx. 4, 0, 5 4875 ; PPC64LE-NEXT: bne 0, .LBB286_1 4876 ; PPC64LE-NEXT: .LBB286_3: 4877 ; PPC64LE-NEXT: lwsync 4878 ; PPC64LE-NEXT: blr 4879 %ret = atomicrmw min i16* %ptr, i16 %val acquire 4880 ret i16 %ret 4881 } 4882 4883 define i16 @test287(i16* %ptr, i16 %val) { 4884 ; PPC64LE-LABEL: test287: 4885 ; PPC64LE: # %bb.0: 4886 ; PPC64LE-NEXT: lwsync 4887 ; PPC64LE-NEXT: .LBB287_1: 4888 ; PPC64LE-NEXT: lharx 5, 0, 3 4889 ; PPC64LE-NEXT: extsh 6, 5 4890 ; PPC64LE-NEXT: cmpw 4, 6 4891 ; PPC64LE-NEXT: bge 0, .LBB287_3 4892 ; PPC64LE-NEXT: # %bb.2: 4893 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4894 ; PPC64LE-NEXT: bne 0, .LBB287_1 4895 ; PPC64LE-NEXT: .LBB287_3: 4896 ; PPC64LE-NEXT: mr 3, 5 4897 ; PPC64LE-NEXT: blr 4898 %ret = atomicrmw min i16* %ptr, i16 %val release 4899 ret i16 %ret 4900 } 4901 4902 define i16 @test288(i16* %ptr, i16 %val) { 4903 ; PPC64LE-LABEL: test288: 4904 ; PPC64LE: # %bb.0: 4905 ; PPC64LE-NEXT: lwsync 4906 ; PPC64LE-NEXT: .LBB288_1: 4907 ; PPC64LE-NEXT: lharx 5, 0, 3 4908 ; PPC64LE-NEXT: extsh 6, 5 4909 ; PPC64LE-NEXT: cmpw 4, 6 4910 ; PPC64LE-NEXT: bge 0, .LBB288_3 4911 ; PPC64LE-NEXT: # %bb.2: 4912 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4913 ; PPC64LE-NEXT: bne 0, .LBB288_1 4914 ; PPC64LE-NEXT: .LBB288_3: 4915 ; PPC64LE-NEXT: mr 3, 5 4916 ; PPC64LE-NEXT: lwsync 4917 ; PPC64LE-NEXT: blr 4918 %ret = atomicrmw min i16* %ptr, i16 %val acq_rel 4919 ret i16 %ret 4920 } 4921 4922 define i16 @test289(i16* %ptr, i16 %val) { 4923 ; PPC64LE-LABEL: test289: 4924 ; PPC64LE: # %bb.0: 4925 ; PPC64LE-NEXT: sync 4926 ; PPC64LE-NEXT: .LBB289_1: 4927 ; PPC64LE-NEXT: lharx 5, 0, 3 4928 ; PPC64LE-NEXT: extsh 6, 5 4929 ; PPC64LE-NEXT: cmpw 4, 6 4930 ; PPC64LE-NEXT: bge 0, .LBB289_3 4931 ; PPC64LE-NEXT: # %bb.2: 4932 ; PPC64LE-NEXT: sthcx. 4, 0, 3 4933 ; PPC64LE-NEXT: bne 0, .LBB289_1 4934 ; PPC64LE-NEXT: .LBB289_3: 4935 ; PPC64LE-NEXT: mr 3, 5 4936 ; PPC64LE-NEXT: lwsync 4937 ; PPC64LE-NEXT: blr 4938 %ret = atomicrmw min i16* %ptr, i16 %val seq_cst 4939 ret i16 %ret 4940 } 4941 4942 define i32 @test290(i32* %ptr, i32 %val) { 4943 ; PPC64LE-LABEL: test290: 4944 ; PPC64LE: # %bb.0: 4945 ; PPC64LE-NEXT: .LBB290_1: 4946 ; PPC64LE-NEXT: lwarx 5, 0, 3 4947 ; PPC64LE-NEXT: cmpw 4, 5 4948 ; PPC64LE-NEXT: bge 0, .LBB290_3 4949 ; PPC64LE-NEXT: # %bb.2: 4950 ; PPC64LE-NEXT: stwcx. 4, 0, 3 4951 ; PPC64LE-NEXT: bne 0, .LBB290_1 4952 ; PPC64LE-NEXT: .LBB290_3: 4953 ; PPC64LE-NEXT: mr 3, 5 4954 ; PPC64LE-NEXT: blr 4955 %ret = atomicrmw min i32* %ptr, i32 %val monotonic 4956 ret i32 %ret 4957 } 4958 4959 define i32 @test291(i32* %ptr, i32 %val) { 4960 ; PPC64LE-LABEL: test291: 4961 ; PPC64LE: # %bb.0: 4962 ; PPC64LE-NEXT: mr 5, 3 4963 ; PPC64LE-NEXT: .LBB291_1: 4964 ; PPC64LE-NEXT: lwarx 3, 0, 5 4965 ; PPC64LE-NEXT: cmpw 4, 3 4966 ; PPC64LE-NEXT: bge 0, .LBB291_3 4967 ; PPC64LE-NEXT: # %bb.2: 4968 ; PPC64LE-NEXT: stwcx. 4, 0, 5 4969 ; PPC64LE-NEXT: bne 0, .LBB291_1 4970 ; PPC64LE-NEXT: .LBB291_3: 4971 ; PPC64LE-NEXT: lwsync 4972 ; PPC64LE-NEXT: blr 4973 %ret = atomicrmw min i32* %ptr, i32 %val acquire 4974 ret i32 %ret 4975 } 4976 4977 define i32 @test292(i32* %ptr, i32 %val) { 4978 ; PPC64LE-LABEL: test292: 4979 ; PPC64LE: # %bb.0: 4980 ; PPC64LE-NEXT: lwsync 4981 ; PPC64LE-NEXT: .LBB292_1: 4982 ; PPC64LE-NEXT: lwarx 5, 0, 3 4983 ; PPC64LE-NEXT: cmpw 4, 5 4984 ; PPC64LE-NEXT: bge 0, .LBB292_3 4985 ; PPC64LE-NEXT: # %bb.2: 4986 ; PPC64LE-NEXT: stwcx. 4, 0, 3 4987 ; PPC64LE-NEXT: bne 0, .LBB292_1 4988 ; PPC64LE-NEXT: .LBB292_3: 4989 ; PPC64LE-NEXT: mr 3, 5 4990 ; PPC64LE-NEXT: blr 4991 %ret = atomicrmw min i32* %ptr, i32 %val release 4992 ret i32 %ret 4993 } 4994 4995 define i32 @test293(i32* %ptr, i32 %val) { 4996 ; PPC64LE-LABEL: test293: 4997 ; PPC64LE: # %bb.0: 4998 ; PPC64LE-NEXT: lwsync 4999 ; PPC64LE-NEXT: .LBB293_1: 5000 ; PPC64LE-NEXT: lwarx 5, 0, 3 5001 ; PPC64LE-NEXT: cmpw 4, 5 5002 ; PPC64LE-NEXT: bge 0, .LBB293_3 5003 ; PPC64LE-NEXT: # %bb.2: 5004 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5005 ; PPC64LE-NEXT: bne 0, .LBB293_1 5006 ; PPC64LE-NEXT: .LBB293_3: 5007 ; PPC64LE-NEXT: mr 3, 5 5008 ; PPC64LE-NEXT: lwsync 5009 ; PPC64LE-NEXT: blr 5010 %ret = atomicrmw min i32* %ptr, i32 %val acq_rel 5011 ret i32 %ret 5012 } 5013 5014 define i32 @test294(i32* %ptr, i32 %val) { 5015 ; PPC64LE-LABEL: test294: 5016 ; PPC64LE: # %bb.0: 5017 ; PPC64LE-NEXT: sync 5018 ; PPC64LE-NEXT: .LBB294_1: 5019 ; PPC64LE-NEXT: lwarx 5, 0, 3 5020 ; PPC64LE-NEXT: cmpw 4, 5 5021 ; PPC64LE-NEXT: bge 0, .LBB294_3 5022 ; PPC64LE-NEXT: # %bb.2: 5023 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5024 ; PPC64LE-NEXT: bne 0, .LBB294_1 5025 ; PPC64LE-NEXT: .LBB294_3: 5026 ; PPC64LE-NEXT: mr 3, 5 5027 ; PPC64LE-NEXT: lwsync 5028 ; PPC64LE-NEXT: blr 5029 %ret = atomicrmw min i32* %ptr, i32 %val seq_cst 5030 ret i32 %ret 5031 } 5032 5033 define i64 @test295(i64* %ptr, i64 %val) { 5034 ; PPC64LE-LABEL: test295: 5035 ; PPC64LE: # %bb.0: 5036 ; PPC64LE-NEXT: .LBB295_1: 5037 ; PPC64LE-NEXT: ldarx 5, 0, 3 5038 ; PPC64LE-NEXT: cmpd 4, 5 5039 ; PPC64LE-NEXT: bge 0, .LBB295_3 5040 ; PPC64LE-NEXT: # %bb.2: 5041 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5042 ; PPC64LE-NEXT: bne 0, .LBB295_1 5043 ; PPC64LE-NEXT: .LBB295_3: 5044 ; PPC64LE-NEXT: mr 3, 5 5045 ; PPC64LE-NEXT: blr 5046 %ret = atomicrmw min i64* %ptr, i64 %val monotonic 5047 ret i64 %ret 5048 } 5049 5050 define i64 @test296(i64* %ptr, i64 %val) { 5051 ; PPC64LE-LABEL: test296: 5052 ; PPC64LE: # %bb.0: 5053 ; PPC64LE-NEXT: mr 5, 3 5054 ; PPC64LE-NEXT: .LBB296_1: 5055 ; PPC64LE-NEXT: ldarx 3, 0, 5 5056 ; PPC64LE-NEXT: cmpd 4, 3 5057 ; PPC64LE-NEXT: bge 0, .LBB296_3 5058 ; PPC64LE-NEXT: # %bb.2: 5059 ; PPC64LE-NEXT: stdcx. 4, 0, 5 5060 ; PPC64LE-NEXT: bne 0, .LBB296_1 5061 ; PPC64LE-NEXT: .LBB296_3: 5062 ; PPC64LE-NEXT: lwsync 5063 ; PPC64LE-NEXT: blr 5064 %ret = atomicrmw min i64* %ptr, i64 %val acquire 5065 ret i64 %ret 5066 } 5067 5068 define i64 @test297(i64* %ptr, i64 %val) { 5069 ; PPC64LE-LABEL: test297: 5070 ; PPC64LE: # %bb.0: 5071 ; PPC64LE-NEXT: lwsync 5072 ; PPC64LE-NEXT: .LBB297_1: 5073 ; PPC64LE-NEXT: ldarx 5, 0, 3 5074 ; PPC64LE-NEXT: cmpd 4, 5 5075 ; PPC64LE-NEXT: bge 0, .LBB297_3 5076 ; PPC64LE-NEXT: # %bb.2: 5077 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5078 ; PPC64LE-NEXT: bne 0, .LBB297_1 5079 ; PPC64LE-NEXT: .LBB297_3: 5080 ; PPC64LE-NEXT: mr 3, 5 5081 ; PPC64LE-NEXT: blr 5082 %ret = atomicrmw min i64* %ptr, i64 %val release 5083 ret i64 %ret 5084 } 5085 5086 define i64 @test298(i64* %ptr, i64 %val) { 5087 ; PPC64LE-LABEL: test298: 5088 ; PPC64LE: # %bb.0: 5089 ; PPC64LE-NEXT: lwsync 5090 ; PPC64LE-NEXT: .LBB298_1: 5091 ; PPC64LE-NEXT: ldarx 5, 0, 3 5092 ; PPC64LE-NEXT: cmpd 4, 5 5093 ; PPC64LE-NEXT: bge 0, .LBB298_3 5094 ; PPC64LE-NEXT: # %bb.2: 5095 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5096 ; PPC64LE-NEXT: bne 0, .LBB298_1 5097 ; PPC64LE-NEXT: .LBB298_3: 5098 ; PPC64LE-NEXT: mr 3, 5 5099 ; PPC64LE-NEXT: lwsync 5100 ; PPC64LE-NEXT: blr 5101 %ret = atomicrmw min i64* %ptr, i64 %val acq_rel 5102 ret i64 %ret 5103 } 5104 5105 define i64 @test299(i64* %ptr, i64 %val) { 5106 ; PPC64LE-LABEL: test299: 5107 ; PPC64LE: # %bb.0: 5108 ; PPC64LE-NEXT: sync 5109 ; PPC64LE-NEXT: .LBB299_1: 5110 ; PPC64LE-NEXT: ldarx 5, 0, 3 5111 ; PPC64LE-NEXT: cmpd 4, 5 5112 ; PPC64LE-NEXT: bge 0, .LBB299_3 5113 ; PPC64LE-NEXT: # %bb.2: 5114 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5115 ; PPC64LE-NEXT: bne 0, .LBB299_1 5116 ; PPC64LE-NEXT: .LBB299_3: 5117 ; PPC64LE-NEXT: mr 3, 5 5118 ; PPC64LE-NEXT: lwsync 5119 ; PPC64LE-NEXT: blr 5120 %ret = atomicrmw min i64* %ptr, i64 %val seq_cst 5121 ret i64 %ret 5122 } 5123 5124 define i8 @test300(i8* %ptr, i8 %val) { 5125 ; PPC64LE-LABEL: test300: 5126 ; PPC64LE: # %bb.0: 5127 ; PPC64LE-NEXT: .LBB300_1: 5128 ; PPC64LE-NEXT: lbarx 5, 0, 3 5129 ; PPC64LE-NEXT: cmplw 4, 5 5130 ; PPC64LE-NEXT: ble 0, .LBB300_3 5131 ; PPC64LE-NEXT: # %bb.2: 5132 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5133 ; PPC64LE-NEXT: bne 0, .LBB300_1 5134 ; PPC64LE-NEXT: .LBB300_3: 5135 ; PPC64LE-NEXT: mr 3, 5 5136 ; PPC64LE-NEXT: blr 5137 %ret = atomicrmw umax i8* %ptr, i8 %val monotonic 5138 ret i8 %ret 5139 } 5140 5141 define i8 @test301(i8* %ptr, i8 %val) { 5142 ; PPC64LE-LABEL: test301: 5143 ; PPC64LE: # %bb.0: 5144 ; PPC64LE-NEXT: mr 5, 3 5145 ; PPC64LE-NEXT: .LBB301_1: 5146 ; PPC64LE-NEXT: lbarx 3, 0, 5 5147 ; PPC64LE-NEXT: cmplw 4, 3 5148 ; PPC64LE-NEXT: ble 0, .LBB301_3 5149 ; PPC64LE-NEXT: # %bb.2: 5150 ; PPC64LE-NEXT: stbcx. 4, 0, 5 5151 ; PPC64LE-NEXT: bne 0, .LBB301_1 5152 ; PPC64LE-NEXT: .LBB301_3: 5153 ; PPC64LE-NEXT: lwsync 5154 ; PPC64LE-NEXT: blr 5155 %ret = atomicrmw umax i8* %ptr, i8 %val acquire 5156 ret i8 %ret 5157 } 5158 5159 define i8 @test302(i8* %ptr, i8 %val) { 5160 ; PPC64LE-LABEL: test302: 5161 ; PPC64LE: # %bb.0: 5162 ; PPC64LE-NEXT: lwsync 5163 ; PPC64LE-NEXT: .LBB302_1: 5164 ; PPC64LE-NEXT: lbarx 5, 0, 3 5165 ; PPC64LE-NEXT: cmplw 4, 5 5166 ; PPC64LE-NEXT: ble 0, .LBB302_3 5167 ; PPC64LE-NEXT: # %bb.2: 5168 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5169 ; PPC64LE-NEXT: bne 0, .LBB302_1 5170 ; PPC64LE-NEXT: .LBB302_3: 5171 ; PPC64LE-NEXT: mr 3, 5 5172 ; PPC64LE-NEXT: blr 5173 %ret = atomicrmw umax i8* %ptr, i8 %val release 5174 ret i8 %ret 5175 } 5176 5177 define i8 @test303(i8* %ptr, i8 %val) { 5178 ; PPC64LE-LABEL: test303: 5179 ; PPC64LE: # %bb.0: 5180 ; PPC64LE-NEXT: lwsync 5181 ; PPC64LE-NEXT: .LBB303_1: 5182 ; PPC64LE-NEXT: lbarx 5, 0, 3 5183 ; PPC64LE-NEXT: cmplw 4, 5 5184 ; PPC64LE-NEXT: ble 0, .LBB303_3 5185 ; PPC64LE-NEXT: # %bb.2: 5186 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5187 ; PPC64LE-NEXT: bne 0, .LBB303_1 5188 ; PPC64LE-NEXT: .LBB303_3: 5189 ; PPC64LE-NEXT: mr 3, 5 5190 ; PPC64LE-NEXT: lwsync 5191 ; PPC64LE-NEXT: blr 5192 %ret = atomicrmw umax i8* %ptr, i8 %val acq_rel 5193 ret i8 %ret 5194 } 5195 5196 define i8 @test304(i8* %ptr, i8 %val) { 5197 ; PPC64LE-LABEL: test304: 5198 ; PPC64LE: # %bb.0: 5199 ; PPC64LE-NEXT: sync 5200 ; PPC64LE-NEXT: .LBB304_1: 5201 ; PPC64LE-NEXT: lbarx 5, 0, 3 5202 ; PPC64LE-NEXT: cmplw 4, 5 5203 ; PPC64LE-NEXT: ble 0, .LBB304_3 5204 ; PPC64LE-NEXT: # %bb.2: 5205 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5206 ; PPC64LE-NEXT: bne 0, .LBB304_1 5207 ; PPC64LE-NEXT: .LBB304_3: 5208 ; PPC64LE-NEXT: mr 3, 5 5209 ; PPC64LE-NEXT: lwsync 5210 ; PPC64LE-NEXT: blr 5211 %ret = atomicrmw umax i8* %ptr, i8 %val seq_cst 5212 ret i8 %ret 5213 } 5214 5215 define i16 @test305(i16* %ptr, i16 %val) { 5216 ; PPC64LE-LABEL: test305: 5217 ; PPC64LE: # %bb.0: 5218 ; PPC64LE-NEXT: .LBB305_1: 5219 ; PPC64LE-NEXT: lharx 5, 0, 3 5220 ; PPC64LE-NEXT: cmplw 4, 5 5221 ; PPC64LE-NEXT: ble 0, .LBB305_3 5222 ; PPC64LE-NEXT: # %bb.2: 5223 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5224 ; PPC64LE-NEXT: bne 0, .LBB305_1 5225 ; PPC64LE-NEXT: .LBB305_3: 5226 ; PPC64LE-NEXT: mr 3, 5 5227 ; PPC64LE-NEXT: blr 5228 %ret = atomicrmw umax i16* %ptr, i16 %val monotonic 5229 ret i16 %ret 5230 } 5231 5232 define i16 @test306(i16* %ptr, i16 %val) { 5233 ; PPC64LE-LABEL: test306: 5234 ; PPC64LE: # %bb.0: 5235 ; PPC64LE-NEXT: mr 5, 3 5236 ; PPC64LE-NEXT: .LBB306_1: 5237 ; PPC64LE-NEXT: lharx 3, 0, 5 5238 ; PPC64LE-NEXT: cmplw 4, 3 5239 ; PPC64LE-NEXT: ble 0, .LBB306_3 5240 ; PPC64LE-NEXT: # %bb.2: 5241 ; PPC64LE-NEXT: sthcx. 4, 0, 5 5242 ; PPC64LE-NEXT: bne 0, .LBB306_1 5243 ; PPC64LE-NEXT: .LBB306_3: 5244 ; PPC64LE-NEXT: lwsync 5245 ; PPC64LE-NEXT: blr 5246 %ret = atomicrmw umax i16* %ptr, i16 %val acquire 5247 ret i16 %ret 5248 } 5249 5250 define i16 @test307(i16* %ptr, i16 %val) { 5251 ; PPC64LE-LABEL: test307: 5252 ; PPC64LE: # %bb.0: 5253 ; PPC64LE-NEXT: lwsync 5254 ; PPC64LE-NEXT: .LBB307_1: 5255 ; PPC64LE-NEXT: lharx 5, 0, 3 5256 ; PPC64LE-NEXT: cmplw 4, 5 5257 ; PPC64LE-NEXT: ble 0, .LBB307_3 5258 ; PPC64LE-NEXT: # %bb.2: 5259 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5260 ; PPC64LE-NEXT: bne 0, .LBB307_1 5261 ; PPC64LE-NEXT: .LBB307_3: 5262 ; PPC64LE-NEXT: mr 3, 5 5263 ; PPC64LE-NEXT: blr 5264 %ret = atomicrmw umax i16* %ptr, i16 %val release 5265 ret i16 %ret 5266 } 5267 5268 define i16 @test308(i16* %ptr, i16 %val) { 5269 ; PPC64LE-LABEL: test308: 5270 ; PPC64LE: # %bb.0: 5271 ; PPC64LE-NEXT: lwsync 5272 ; PPC64LE-NEXT: .LBB308_1: 5273 ; PPC64LE-NEXT: lharx 5, 0, 3 5274 ; PPC64LE-NEXT: cmplw 4, 5 5275 ; PPC64LE-NEXT: ble 0, .LBB308_3 5276 ; PPC64LE-NEXT: # %bb.2: 5277 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5278 ; PPC64LE-NEXT: bne 0, .LBB308_1 5279 ; PPC64LE-NEXT: .LBB308_3: 5280 ; PPC64LE-NEXT: mr 3, 5 5281 ; PPC64LE-NEXT: lwsync 5282 ; PPC64LE-NEXT: blr 5283 %ret = atomicrmw umax i16* %ptr, i16 %val acq_rel 5284 ret i16 %ret 5285 } 5286 5287 define i16 @test309(i16* %ptr, i16 %val) { 5288 ; PPC64LE-LABEL: test309: 5289 ; PPC64LE: # %bb.0: 5290 ; PPC64LE-NEXT: sync 5291 ; PPC64LE-NEXT: .LBB309_1: 5292 ; PPC64LE-NEXT: lharx 5, 0, 3 5293 ; PPC64LE-NEXT: cmplw 4, 5 5294 ; PPC64LE-NEXT: ble 0, .LBB309_3 5295 ; PPC64LE-NEXT: # %bb.2: 5296 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5297 ; PPC64LE-NEXT: bne 0, .LBB309_1 5298 ; PPC64LE-NEXT: .LBB309_3: 5299 ; PPC64LE-NEXT: mr 3, 5 5300 ; PPC64LE-NEXT: lwsync 5301 ; PPC64LE-NEXT: blr 5302 %ret = atomicrmw umax i16* %ptr, i16 %val seq_cst 5303 ret i16 %ret 5304 } 5305 5306 define i32 @test310(i32* %ptr, i32 %val) { 5307 ; PPC64LE-LABEL: test310: 5308 ; PPC64LE: # %bb.0: 5309 ; PPC64LE-NEXT: .LBB310_1: 5310 ; PPC64LE-NEXT: lwarx 5, 0, 3 5311 ; PPC64LE-NEXT: cmplw 4, 5 5312 ; PPC64LE-NEXT: ble 0, .LBB310_3 5313 ; PPC64LE-NEXT: # %bb.2: 5314 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5315 ; PPC64LE-NEXT: bne 0, .LBB310_1 5316 ; PPC64LE-NEXT: .LBB310_3: 5317 ; PPC64LE-NEXT: mr 3, 5 5318 ; PPC64LE-NEXT: blr 5319 %ret = atomicrmw umax i32* %ptr, i32 %val monotonic 5320 ret i32 %ret 5321 } 5322 5323 define i32 @test311(i32* %ptr, i32 %val) { 5324 ; PPC64LE-LABEL: test311: 5325 ; PPC64LE: # %bb.0: 5326 ; PPC64LE-NEXT: mr 5, 3 5327 ; PPC64LE-NEXT: .LBB311_1: 5328 ; PPC64LE-NEXT: lwarx 3, 0, 5 5329 ; PPC64LE-NEXT: cmplw 4, 3 5330 ; PPC64LE-NEXT: ble 0, .LBB311_3 5331 ; PPC64LE-NEXT: # %bb.2: 5332 ; PPC64LE-NEXT: stwcx. 4, 0, 5 5333 ; PPC64LE-NEXT: bne 0, .LBB311_1 5334 ; PPC64LE-NEXT: .LBB311_3: 5335 ; PPC64LE-NEXT: lwsync 5336 ; PPC64LE-NEXT: blr 5337 %ret = atomicrmw umax i32* %ptr, i32 %val acquire 5338 ret i32 %ret 5339 } 5340 5341 define i32 @test312(i32* %ptr, i32 %val) { 5342 ; PPC64LE-LABEL: test312: 5343 ; PPC64LE: # %bb.0: 5344 ; PPC64LE-NEXT: lwsync 5345 ; PPC64LE-NEXT: .LBB312_1: 5346 ; PPC64LE-NEXT: lwarx 5, 0, 3 5347 ; PPC64LE-NEXT: cmplw 4, 5 5348 ; PPC64LE-NEXT: ble 0, .LBB312_3 5349 ; PPC64LE-NEXT: # %bb.2: 5350 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5351 ; PPC64LE-NEXT: bne 0, .LBB312_1 5352 ; PPC64LE-NEXT: .LBB312_3: 5353 ; PPC64LE-NEXT: mr 3, 5 5354 ; PPC64LE-NEXT: blr 5355 %ret = atomicrmw umax i32* %ptr, i32 %val release 5356 ret i32 %ret 5357 } 5358 5359 define i32 @test313(i32* %ptr, i32 %val) { 5360 ; PPC64LE-LABEL: test313: 5361 ; PPC64LE: # %bb.0: 5362 ; PPC64LE-NEXT: lwsync 5363 ; PPC64LE-NEXT: .LBB313_1: 5364 ; PPC64LE-NEXT: lwarx 5, 0, 3 5365 ; PPC64LE-NEXT: cmplw 4, 5 5366 ; PPC64LE-NEXT: ble 0, .LBB313_3 5367 ; PPC64LE-NEXT: # %bb.2: 5368 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5369 ; PPC64LE-NEXT: bne 0, .LBB313_1 5370 ; PPC64LE-NEXT: .LBB313_3: 5371 ; PPC64LE-NEXT: mr 3, 5 5372 ; PPC64LE-NEXT: lwsync 5373 ; PPC64LE-NEXT: blr 5374 %ret = atomicrmw umax i32* %ptr, i32 %val acq_rel 5375 ret i32 %ret 5376 } 5377 5378 define i32 @test314(i32* %ptr, i32 %val) { 5379 ; PPC64LE-LABEL: test314: 5380 ; PPC64LE: # %bb.0: 5381 ; PPC64LE-NEXT: sync 5382 ; PPC64LE-NEXT: .LBB314_1: 5383 ; PPC64LE-NEXT: lwarx 5, 0, 3 5384 ; PPC64LE-NEXT: cmplw 4, 5 5385 ; PPC64LE-NEXT: ble 0, .LBB314_3 5386 ; PPC64LE-NEXT: # %bb.2: 5387 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5388 ; PPC64LE-NEXT: bne 0, .LBB314_1 5389 ; PPC64LE-NEXT: .LBB314_3: 5390 ; PPC64LE-NEXT: mr 3, 5 5391 ; PPC64LE-NEXT: lwsync 5392 ; PPC64LE-NEXT: blr 5393 %ret = atomicrmw umax i32* %ptr, i32 %val seq_cst 5394 ret i32 %ret 5395 } 5396 5397 define i64 @test315(i64* %ptr, i64 %val) { 5398 ; PPC64LE-LABEL: test315: 5399 ; PPC64LE: # %bb.0: 5400 ; PPC64LE-NEXT: .LBB315_1: 5401 ; PPC64LE-NEXT: ldarx 5, 0, 3 5402 ; PPC64LE-NEXT: cmpld 4, 5 5403 ; PPC64LE-NEXT: ble 0, .LBB315_3 5404 ; PPC64LE-NEXT: # %bb.2: 5405 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5406 ; PPC64LE-NEXT: bne 0, .LBB315_1 5407 ; PPC64LE-NEXT: .LBB315_3: 5408 ; PPC64LE-NEXT: mr 3, 5 5409 ; PPC64LE-NEXT: blr 5410 %ret = atomicrmw umax i64* %ptr, i64 %val monotonic 5411 ret i64 %ret 5412 } 5413 5414 define i64 @test316(i64* %ptr, i64 %val) { 5415 ; PPC64LE-LABEL: test316: 5416 ; PPC64LE: # %bb.0: 5417 ; PPC64LE-NEXT: mr 5, 3 5418 ; PPC64LE-NEXT: .LBB316_1: 5419 ; PPC64LE-NEXT: ldarx 3, 0, 5 5420 ; PPC64LE-NEXT: cmpld 4, 3 5421 ; PPC64LE-NEXT: ble 0, .LBB316_3 5422 ; PPC64LE-NEXT: # %bb.2: 5423 ; PPC64LE-NEXT: stdcx. 4, 0, 5 5424 ; PPC64LE-NEXT: bne 0, .LBB316_1 5425 ; PPC64LE-NEXT: .LBB316_3: 5426 ; PPC64LE-NEXT: lwsync 5427 ; PPC64LE-NEXT: blr 5428 %ret = atomicrmw umax i64* %ptr, i64 %val acquire 5429 ret i64 %ret 5430 } 5431 5432 define i64 @test317(i64* %ptr, i64 %val) { 5433 ; PPC64LE-LABEL: test317: 5434 ; PPC64LE: # %bb.0: 5435 ; PPC64LE-NEXT: lwsync 5436 ; PPC64LE-NEXT: .LBB317_1: 5437 ; PPC64LE-NEXT: ldarx 5, 0, 3 5438 ; PPC64LE-NEXT: cmpld 4, 5 5439 ; PPC64LE-NEXT: ble 0, .LBB317_3 5440 ; PPC64LE-NEXT: # %bb.2: 5441 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5442 ; PPC64LE-NEXT: bne 0, .LBB317_1 5443 ; PPC64LE-NEXT: .LBB317_3: 5444 ; PPC64LE-NEXT: mr 3, 5 5445 ; PPC64LE-NEXT: blr 5446 %ret = atomicrmw umax i64* %ptr, i64 %val release 5447 ret i64 %ret 5448 } 5449 5450 define i64 @test318(i64* %ptr, i64 %val) { 5451 ; PPC64LE-LABEL: test318: 5452 ; PPC64LE: # %bb.0: 5453 ; PPC64LE-NEXT: lwsync 5454 ; PPC64LE-NEXT: .LBB318_1: 5455 ; PPC64LE-NEXT: ldarx 5, 0, 3 5456 ; PPC64LE-NEXT: cmpld 4, 5 5457 ; PPC64LE-NEXT: ble 0, .LBB318_3 5458 ; PPC64LE-NEXT: # %bb.2: 5459 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5460 ; PPC64LE-NEXT: bne 0, .LBB318_1 5461 ; PPC64LE-NEXT: .LBB318_3: 5462 ; PPC64LE-NEXT: mr 3, 5 5463 ; PPC64LE-NEXT: lwsync 5464 ; PPC64LE-NEXT: blr 5465 %ret = atomicrmw umax i64* %ptr, i64 %val acq_rel 5466 ret i64 %ret 5467 } 5468 5469 define i64 @test319(i64* %ptr, i64 %val) { 5470 ; PPC64LE-LABEL: test319: 5471 ; PPC64LE: # %bb.0: 5472 ; PPC64LE-NEXT: sync 5473 ; PPC64LE-NEXT: .LBB319_1: 5474 ; PPC64LE-NEXT: ldarx 5, 0, 3 5475 ; PPC64LE-NEXT: cmpld 4, 5 5476 ; PPC64LE-NEXT: ble 0, .LBB319_3 5477 ; PPC64LE-NEXT: # %bb.2: 5478 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5479 ; PPC64LE-NEXT: bne 0, .LBB319_1 5480 ; PPC64LE-NEXT: .LBB319_3: 5481 ; PPC64LE-NEXT: mr 3, 5 5482 ; PPC64LE-NEXT: lwsync 5483 ; PPC64LE-NEXT: blr 5484 %ret = atomicrmw umax i64* %ptr, i64 %val seq_cst 5485 ret i64 %ret 5486 } 5487 5488 define i8 @test320(i8* %ptr, i8 %val) { 5489 ; PPC64LE-LABEL: test320: 5490 ; PPC64LE: # %bb.0: 5491 ; PPC64LE-NEXT: .LBB320_1: 5492 ; PPC64LE-NEXT: lbarx 5, 0, 3 5493 ; PPC64LE-NEXT: cmplw 4, 5 5494 ; PPC64LE-NEXT: bge 0, .LBB320_3 5495 ; PPC64LE-NEXT: # %bb.2: 5496 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5497 ; PPC64LE-NEXT: bne 0, .LBB320_1 5498 ; PPC64LE-NEXT: .LBB320_3: 5499 ; PPC64LE-NEXT: mr 3, 5 5500 ; PPC64LE-NEXT: blr 5501 %ret = atomicrmw umin i8* %ptr, i8 %val monotonic 5502 ret i8 %ret 5503 } 5504 5505 define i8 @test321(i8* %ptr, i8 %val) { 5506 ; PPC64LE-LABEL: test321: 5507 ; PPC64LE: # %bb.0: 5508 ; PPC64LE-NEXT: mr 5, 3 5509 ; PPC64LE-NEXT: .LBB321_1: 5510 ; PPC64LE-NEXT: lbarx 3, 0, 5 5511 ; PPC64LE-NEXT: cmplw 4, 3 5512 ; PPC64LE-NEXT: bge 0, .LBB321_3 5513 ; PPC64LE-NEXT: # %bb.2: 5514 ; PPC64LE-NEXT: stbcx. 4, 0, 5 5515 ; PPC64LE-NEXT: bne 0, .LBB321_1 5516 ; PPC64LE-NEXT: .LBB321_3: 5517 ; PPC64LE-NEXT: lwsync 5518 ; PPC64LE-NEXT: blr 5519 %ret = atomicrmw umin i8* %ptr, i8 %val acquire 5520 ret i8 %ret 5521 } 5522 5523 define i8 @test322(i8* %ptr, i8 %val) { 5524 ; PPC64LE-LABEL: test322: 5525 ; PPC64LE: # %bb.0: 5526 ; PPC64LE-NEXT: lwsync 5527 ; PPC64LE-NEXT: .LBB322_1: 5528 ; PPC64LE-NEXT: lbarx 5, 0, 3 5529 ; PPC64LE-NEXT: cmplw 4, 5 5530 ; PPC64LE-NEXT: bge 0, .LBB322_3 5531 ; PPC64LE-NEXT: # %bb.2: 5532 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5533 ; PPC64LE-NEXT: bne 0, .LBB322_1 5534 ; PPC64LE-NEXT: .LBB322_3: 5535 ; PPC64LE-NEXT: mr 3, 5 5536 ; PPC64LE-NEXT: blr 5537 %ret = atomicrmw umin i8* %ptr, i8 %val release 5538 ret i8 %ret 5539 } 5540 5541 define i8 @test323(i8* %ptr, i8 %val) { 5542 ; PPC64LE-LABEL: test323: 5543 ; PPC64LE: # %bb.0: 5544 ; PPC64LE-NEXT: lwsync 5545 ; PPC64LE-NEXT: .LBB323_1: 5546 ; PPC64LE-NEXT: lbarx 5, 0, 3 5547 ; PPC64LE-NEXT: cmplw 4, 5 5548 ; PPC64LE-NEXT: bge 0, .LBB323_3 5549 ; PPC64LE-NEXT: # %bb.2: 5550 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5551 ; PPC64LE-NEXT: bne 0, .LBB323_1 5552 ; PPC64LE-NEXT: .LBB323_3: 5553 ; PPC64LE-NEXT: mr 3, 5 5554 ; PPC64LE-NEXT: lwsync 5555 ; PPC64LE-NEXT: blr 5556 %ret = atomicrmw umin i8* %ptr, i8 %val acq_rel 5557 ret i8 %ret 5558 } 5559 5560 define i8 @test324(i8* %ptr, i8 %val) { 5561 ; PPC64LE-LABEL: test324: 5562 ; PPC64LE: # %bb.0: 5563 ; PPC64LE-NEXT: sync 5564 ; PPC64LE-NEXT: .LBB324_1: 5565 ; PPC64LE-NEXT: lbarx 5, 0, 3 5566 ; PPC64LE-NEXT: cmplw 4, 5 5567 ; PPC64LE-NEXT: bge 0, .LBB324_3 5568 ; PPC64LE-NEXT: # %bb.2: 5569 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5570 ; PPC64LE-NEXT: bne 0, .LBB324_1 5571 ; PPC64LE-NEXT: .LBB324_3: 5572 ; PPC64LE-NEXT: mr 3, 5 5573 ; PPC64LE-NEXT: lwsync 5574 ; PPC64LE-NEXT: blr 5575 %ret = atomicrmw umin i8* %ptr, i8 %val seq_cst 5576 ret i8 %ret 5577 } 5578 5579 define i16 @test325(i16* %ptr, i16 %val) { 5580 ; PPC64LE-LABEL: test325: 5581 ; PPC64LE: # %bb.0: 5582 ; PPC64LE-NEXT: .LBB325_1: 5583 ; PPC64LE-NEXT: lharx 5, 0, 3 5584 ; PPC64LE-NEXT: cmplw 4, 5 5585 ; PPC64LE-NEXT: bge 0, .LBB325_3 5586 ; PPC64LE-NEXT: # %bb.2: 5587 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5588 ; PPC64LE-NEXT: bne 0, .LBB325_1 5589 ; PPC64LE-NEXT: .LBB325_3: 5590 ; PPC64LE-NEXT: mr 3, 5 5591 ; PPC64LE-NEXT: blr 5592 %ret = atomicrmw umin i16* %ptr, i16 %val monotonic 5593 ret i16 %ret 5594 } 5595 5596 define i16 @test326(i16* %ptr, i16 %val) { 5597 ; PPC64LE-LABEL: test326: 5598 ; PPC64LE: # %bb.0: 5599 ; PPC64LE-NEXT: mr 5, 3 5600 ; PPC64LE-NEXT: .LBB326_1: 5601 ; PPC64LE-NEXT: lharx 3, 0, 5 5602 ; PPC64LE-NEXT: cmplw 4, 3 5603 ; PPC64LE-NEXT: bge 0, .LBB326_3 5604 ; PPC64LE-NEXT: # %bb.2: 5605 ; PPC64LE-NEXT: sthcx. 4, 0, 5 5606 ; PPC64LE-NEXT: bne 0, .LBB326_1 5607 ; PPC64LE-NEXT: .LBB326_3: 5608 ; PPC64LE-NEXT: lwsync 5609 ; PPC64LE-NEXT: blr 5610 %ret = atomicrmw umin i16* %ptr, i16 %val acquire 5611 ret i16 %ret 5612 } 5613 5614 define i16 @test327(i16* %ptr, i16 %val) { 5615 ; PPC64LE-LABEL: test327: 5616 ; PPC64LE: # %bb.0: 5617 ; PPC64LE-NEXT: lwsync 5618 ; PPC64LE-NEXT: .LBB327_1: 5619 ; PPC64LE-NEXT: lharx 5, 0, 3 5620 ; PPC64LE-NEXT: cmplw 4, 5 5621 ; PPC64LE-NEXT: bge 0, .LBB327_3 5622 ; PPC64LE-NEXT: # %bb.2: 5623 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5624 ; PPC64LE-NEXT: bne 0, .LBB327_1 5625 ; PPC64LE-NEXT: .LBB327_3: 5626 ; PPC64LE-NEXT: mr 3, 5 5627 ; PPC64LE-NEXT: blr 5628 %ret = atomicrmw umin i16* %ptr, i16 %val release 5629 ret i16 %ret 5630 } 5631 5632 define i16 @test328(i16* %ptr, i16 %val) { 5633 ; PPC64LE-LABEL: test328: 5634 ; PPC64LE: # %bb.0: 5635 ; PPC64LE-NEXT: lwsync 5636 ; PPC64LE-NEXT: .LBB328_1: 5637 ; PPC64LE-NEXT: lharx 5, 0, 3 5638 ; PPC64LE-NEXT: cmplw 4, 5 5639 ; PPC64LE-NEXT: bge 0, .LBB328_3 5640 ; PPC64LE-NEXT: # %bb.2: 5641 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5642 ; PPC64LE-NEXT: bne 0, .LBB328_1 5643 ; PPC64LE-NEXT: .LBB328_3: 5644 ; PPC64LE-NEXT: mr 3, 5 5645 ; PPC64LE-NEXT: lwsync 5646 ; PPC64LE-NEXT: blr 5647 %ret = atomicrmw umin i16* %ptr, i16 %val acq_rel 5648 ret i16 %ret 5649 } 5650 5651 define i16 @test329(i16* %ptr, i16 %val) { 5652 ; PPC64LE-LABEL: test329: 5653 ; PPC64LE: # %bb.0: 5654 ; PPC64LE-NEXT: sync 5655 ; PPC64LE-NEXT: .LBB329_1: 5656 ; PPC64LE-NEXT: lharx 5, 0, 3 5657 ; PPC64LE-NEXT: cmplw 4, 5 5658 ; PPC64LE-NEXT: bge 0, .LBB329_3 5659 ; PPC64LE-NEXT: # %bb.2: 5660 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5661 ; PPC64LE-NEXT: bne 0, .LBB329_1 5662 ; PPC64LE-NEXT: .LBB329_3: 5663 ; PPC64LE-NEXT: mr 3, 5 5664 ; PPC64LE-NEXT: lwsync 5665 ; PPC64LE-NEXT: blr 5666 %ret = atomicrmw umin i16* %ptr, i16 %val seq_cst 5667 ret i16 %ret 5668 } 5669 5670 define i32 @test330(i32* %ptr, i32 %val) { 5671 ; PPC64LE-LABEL: test330: 5672 ; PPC64LE: # %bb.0: 5673 ; PPC64LE-NEXT: .LBB330_1: 5674 ; PPC64LE-NEXT: lwarx 5, 0, 3 5675 ; PPC64LE-NEXT: cmplw 4, 5 5676 ; PPC64LE-NEXT: bge 0, .LBB330_3 5677 ; PPC64LE-NEXT: # %bb.2: 5678 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5679 ; PPC64LE-NEXT: bne 0, .LBB330_1 5680 ; PPC64LE-NEXT: .LBB330_3: 5681 ; PPC64LE-NEXT: mr 3, 5 5682 ; PPC64LE-NEXT: blr 5683 %ret = atomicrmw umin i32* %ptr, i32 %val monotonic 5684 ret i32 %ret 5685 } 5686 5687 define i32 @test331(i32* %ptr, i32 %val) { 5688 ; PPC64LE-LABEL: test331: 5689 ; PPC64LE: # %bb.0: 5690 ; PPC64LE-NEXT: mr 5, 3 5691 ; PPC64LE-NEXT: .LBB331_1: 5692 ; PPC64LE-NEXT: lwarx 3, 0, 5 5693 ; PPC64LE-NEXT: cmplw 4, 3 5694 ; PPC64LE-NEXT: bge 0, .LBB331_3 5695 ; PPC64LE-NEXT: # %bb.2: 5696 ; PPC64LE-NEXT: stwcx. 4, 0, 5 5697 ; PPC64LE-NEXT: bne 0, .LBB331_1 5698 ; PPC64LE-NEXT: .LBB331_3: 5699 ; PPC64LE-NEXT: lwsync 5700 ; PPC64LE-NEXT: blr 5701 %ret = atomicrmw umin i32* %ptr, i32 %val acquire 5702 ret i32 %ret 5703 } 5704 5705 define i32 @test332(i32* %ptr, i32 %val) { 5706 ; PPC64LE-LABEL: test332: 5707 ; PPC64LE: # %bb.0: 5708 ; PPC64LE-NEXT: lwsync 5709 ; PPC64LE-NEXT: .LBB332_1: 5710 ; PPC64LE-NEXT: lwarx 5, 0, 3 5711 ; PPC64LE-NEXT: cmplw 4, 5 5712 ; PPC64LE-NEXT: bge 0, .LBB332_3 5713 ; PPC64LE-NEXT: # %bb.2: 5714 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5715 ; PPC64LE-NEXT: bne 0, .LBB332_1 5716 ; PPC64LE-NEXT: .LBB332_3: 5717 ; PPC64LE-NEXT: mr 3, 5 5718 ; PPC64LE-NEXT: blr 5719 %ret = atomicrmw umin i32* %ptr, i32 %val release 5720 ret i32 %ret 5721 } 5722 5723 define i32 @test333(i32* %ptr, i32 %val) { 5724 ; PPC64LE-LABEL: test333: 5725 ; PPC64LE: # %bb.0: 5726 ; PPC64LE-NEXT: lwsync 5727 ; PPC64LE-NEXT: .LBB333_1: 5728 ; PPC64LE-NEXT: lwarx 5, 0, 3 5729 ; PPC64LE-NEXT: cmplw 4, 5 5730 ; PPC64LE-NEXT: bge 0, .LBB333_3 5731 ; PPC64LE-NEXT: # %bb.2: 5732 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5733 ; PPC64LE-NEXT: bne 0, .LBB333_1 5734 ; PPC64LE-NEXT: .LBB333_3: 5735 ; PPC64LE-NEXT: mr 3, 5 5736 ; PPC64LE-NEXT: lwsync 5737 ; PPC64LE-NEXT: blr 5738 %ret = atomicrmw umin i32* %ptr, i32 %val acq_rel 5739 ret i32 %ret 5740 } 5741 5742 define i32 @test334(i32* %ptr, i32 %val) { 5743 ; PPC64LE-LABEL: test334: 5744 ; PPC64LE: # %bb.0: 5745 ; PPC64LE-NEXT: sync 5746 ; PPC64LE-NEXT: .LBB334_1: 5747 ; PPC64LE-NEXT: lwarx 5, 0, 3 5748 ; PPC64LE-NEXT: cmplw 4, 5 5749 ; PPC64LE-NEXT: bge 0, .LBB334_3 5750 ; PPC64LE-NEXT: # %bb.2: 5751 ; PPC64LE-NEXT: stwcx. 4, 0, 3 5752 ; PPC64LE-NEXT: bne 0, .LBB334_1 5753 ; PPC64LE-NEXT: .LBB334_3: 5754 ; PPC64LE-NEXT: mr 3, 5 5755 ; PPC64LE-NEXT: lwsync 5756 ; PPC64LE-NEXT: blr 5757 %ret = atomicrmw umin i32* %ptr, i32 %val seq_cst 5758 ret i32 %ret 5759 } 5760 5761 define i64 @test335(i64* %ptr, i64 %val) { 5762 ; PPC64LE-LABEL: test335: 5763 ; PPC64LE: # %bb.0: 5764 ; PPC64LE-NEXT: .LBB335_1: 5765 ; PPC64LE-NEXT: ldarx 5, 0, 3 5766 ; PPC64LE-NEXT: cmpld 4, 5 5767 ; PPC64LE-NEXT: bge 0, .LBB335_3 5768 ; PPC64LE-NEXT: # %bb.2: 5769 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5770 ; PPC64LE-NEXT: bne 0, .LBB335_1 5771 ; PPC64LE-NEXT: .LBB335_3: 5772 ; PPC64LE-NEXT: mr 3, 5 5773 ; PPC64LE-NEXT: blr 5774 %ret = atomicrmw umin i64* %ptr, i64 %val monotonic 5775 ret i64 %ret 5776 } 5777 5778 define i64 @test336(i64* %ptr, i64 %val) { 5779 ; PPC64LE-LABEL: test336: 5780 ; PPC64LE: # %bb.0: 5781 ; PPC64LE-NEXT: mr 5, 3 5782 ; PPC64LE-NEXT: .LBB336_1: 5783 ; PPC64LE-NEXT: ldarx 3, 0, 5 5784 ; PPC64LE-NEXT: cmpld 4, 3 5785 ; PPC64LE-NEXT: bge 0, .LBB336_3 5786 ; PPC64LE-NEXT: # %bb.2: 5787 ; PPC64LE-NEXT: stdcx. 4, 0, 5 5788 ; PPC64LE-NEXT: bne 0, .LBB336_1 5789 ; PPC64LE-NEXT: .LBB336_3: 5790 ; PPC64LE-NEXT: lwsync 5791 ; PPC64LE-NEXT: blr 5792 %ret = atomicrmw umin i64* %ptr, i64 %val acquire 5793 ret i64 %ret 5794 } 5795 5796 define i64 @test337(i64* %ptr, i64 %val) { 5797 ; PPC64LE-LABEL: test337: 5798 ; PPC64LE: # %bb.0: 5799 ; PPC64LE-NEXT: lwsync 5800 ; PPC64LE-NEXT: .LBB337_1: 5801 ; PPC64LE-NEXT: ldarx 5, 0, 3 5802 ; PPC64LE-NEXT: cmpld 4, 5 5803 ; PPC64LE-NEXT: bge 0, .LBB337_3 5804 ; PPC64LE-NEXT: # %bb.2: 5805 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5806 ; PPC64LE-NEXT: bne 0, .LBB337_1 5807 ; PPC64LE-NEXT: .LBB337_3: 5808 ; PPC64LE-NEXT: mr 3, 5 5809 ; PPC64LE-NEXT: blr 5810 %ret = atomicrmw umin i64* %ptr, i64 %val release 5811 ret i64 %ret 5812 } 5813 5814 define i64 @test338(i64* %ptr, i64 %val) { 5815 ; PPC64LE-LABEL: test338: 5816 ; PPC64LE: # %bb.0: 5817 ; PPC64LE-NEXT: lwsync 5818 ; PPC64LE-NEXT: .LBB338_1: 5819 ; PPC64LE-NEXT: ldarx 5, 0, 3 5820 ; PPC64LE-NEXT: cmpld 4, 5 5821 ; PPC64LE-NEXT: bge 0, .LBB338_3 5822 ; PPC64LE-NEXT: # %bb.2: 5823 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5824 ; PPC64LE-NEXT: bne 0, .LBB338_1 5825 ; PPC64LE-NEXT: .LBB338_3: 5826 ; PPC64LE-NEXT: mr 3, 5 5827 ; PPC64LE-NEXT: lwsync 5828 ; PPC64LE-NEXT: blr 5829 %ret = atomicrmw umin i64* %ptr, i64 %val acq_rel 5830 ret i64 %ret 5831 } 5832 5833 define i64 @test339(i64* %ptr, i64 %val) { 5834 ; PPC64LE-LABEL: test339: 5835 ; PPC64LE: # %bb.0: 5836 ; PPC64LE-NEXT: sync 5837 ; PPC64LE-NEXT: .LBB339_1: 5838 ; PPC64LE-NEXT: ldarx 5, 0, 3 5839 ; PPC64LE-NEXT: cmpld 4, 5 5840 ; PPC64LE-NEXT: bge 0, .LBB339_3 5841 ; PPC64LE-NEXT: # %bb.2: 5842 ; PPC64LE-NEXT: stdcx. 4, 0, 3 5843 ; PPC64LE-NEXT: bne 0, .LBB339_1 5844 ; PPC64LE-NEXT: .LBB339_3: 5845 ; PPC64LE-NEXT: mr 3, 5 5846 ; PPC64LE-NEXT: lwsync 5847 ; PPC64LE-NEXT: blr 5848 %ret = atomicrmw umin i64* %ptr, i64 %val seq_cst 5849 ret i64 %ret 5850 } 5851 5852 define i8 @test340(i8* %ptr, i8 %val) { 5853 ; PPC64LE-LABEL: test340: 5854 ; PPC64LE: # %bb.0: 5855 ; PPC64LE-NEXT: .LBB340_1: 5856 ; PPC64LE-NEXT: lbarx 5, 0, 3 5857 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5858 ; PPC64LE-NEXT: bne 0, .LBB340_1 5859 ; PPC64LE-NEXT: # %bb.2: 5860 ; PPC64LE-NEXT: mr 3, 5 5861 ; PPC64LE-NEXT: blr 5862 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") monotonic 5863 ret i8 %ret 5864 } 5865 5866 define i8 @test341(i8* %ptr, i8 %val) { 5867 ; PPC64LE-LABEL: test341: 5868 ; PPC64LE: # %bb.0: 5869 ; PPC64LE-NEXT: mr 5, 3 5870 ; PPC64LE-NEXT: .LBB341_1: 5871 ; PPC64LE-NEXT: lbarx 3, 0, 5 5872 ; PPC64LE-NEXT: stbcx. 4, 0, 5 5873 ; PPC64LE-NEXT: bne 0, .LBB341_1 5874 ; PPC64LE-NEXT: # %bb.2: 5875 ; PPC64LE-NEXT: lwsync 5876 ; PPC64LE-NEXT: blr 5877 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acquire 5878 ret i8 %ret 5879 } 5880 5881 define i8 @test342(i8* %ptr, i8 %val) { 5882 ; PPC64LE-LABEL: test342: 5883 ; PPC64LE: # %bb.0: 5884 ; PPC64LE-NEXT: lwsync 5885 ; PPC64LE-NEXT: .LBB342_1: 5886 ; PPC64LE-NEXT: lbarx 5, 0, 3 5887 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5888 ; PPC64LE-NEXT: bne 0, .LBB342_1 5889 ; PPC64LE-NEXT: # %bb.2: 5890 ; PPC64LE-NEXT: mr 3, 5 5891 ; PPC64LE-NEXT: blr 5892 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") release 5893 ret i8 %ret 5894 } 5895 5896 define i8 @test343(i8* %ptr, i8 %val) { 5897 ; PPC64LE-LABEL: test343: 5898 ; PPC64LE: # %bb.0: 5899 ; PPC64LE-NEXT: lwsync 5900 ; PPC64LE-NEXT: .LBB343_1: 5901 ; PPC64LE-NEXT: lbarx 5, 0, 3 5902 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5903 ; PPC64LE-NEXT: bne 0, .LBB343_1 5904 ; PPC64LE-NEXT: # %bb.2: 5905 ; PPC64LE-NEXT: mr 3, 5 5906 ; PPC64LE-NEXT: lwsync 5907 ; PPC64LE-NEXT: blr 5908 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acq_rel 5909 ret i8 %ret 5910 } 5911 5912 define i8 @test344(i8* %ptr, i8 %val) { 5913 ; PPC64LE-LABEL: test344: 5914 ; PPC64LE: # %bb.0: 5915 ; PPC64LE-NEXT: sync 5916 ; PPC64LE-NEXT: .LBB344_1: 5917 ; PPC64LE-NEXT: lbarx 5, 0, 3 5918 ; PPC64LE-NEXT: stbcx. 4, 0, 3 5919 ; PPC64LE-NEXT: bne 0, .LBB344_1 5920 ; PPC64LE-NEXT: # %bb.2: 5921 ; PPC64LE-NEXT: mr 3, 5 5922 ; PPC64LE-NEXT: lwsync 5923 ; PPC64LE-NEXT: blr 5924 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") seq_cst 5925 ret i8 %ret 5926 } 5927 5928 define i16 @test345(i16* %ptr, i16 %val) { 5929 ; PPC64LE-LABEL: test345: 5930 ; PPC64LE: # %bb.0: 5931 ; PPC64LE-NEXT: .LBB345_1: 5932 ; PPC64LE-NEXT: lharx 5, 0, 3 5933 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5934 ; PPC64LE-NEXT: bne 0, .LBB345_1 5935 ; PPC64LE-NEXT: # %bb.2: 5936 ; PPC64LE-NEXT: mr 3, 5 5937 ; PPC64LE-NEXT: blr 5938 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") monotonic 5939 ret i16 %ret 5940 } 5941 5942 define i16 @test346(i16* %ptr, i16 %val) { 5943 ; PPC64LE-LABEL: test346: 5944 ; PPC64LE: # %bb.0: 5945 ; PPC64LE-NEXT: mr 5, 3 5946 ; PPC64LE-NEXT: .LBB346_1: 5947 ; PPC64LE-NEXT: lharx 3, 0, 5 5948 ; PPC64LE-NEXT: sthcx. 4, 0, 5 5949 ; PPC64LE-NEXT: bne 0, .LBB346_1 5950 ; PPC64LE-NEXT: # %bb.2: 5951 ; PPC64LE-NEXT: lwsync 5952 ; PPC64LE-NEXT: blr 5953 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acquire 5954 ret i16 %ret 5955 } 5956 5957 define i16 @test347(i16* %ptr, i16 %val) { 5958 ; PPC64LE-LABEL: test347: 5959 ; PPC64LE: # %bb.0: 5960 ; PPC64LE-NEXT: lwsync 5961 ; PPC64LE-NEXT: .LBB347_1: 5962 ; PPC64LE-NEXT: lharx 5, 0, 3 5963 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5964 ; PPC64LE-NEXT: bne 0, .LBB347_1 5965 ; PPC64LE-NEXT: # %bb.2: 5966 ; PPC64LE-NEXT: mr 3, 5 5967 ; PPC64LE-NEXT: blr 5968 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") release 5969 ret i16 %ret 5970 } 5971 5972 define i16 @test348(i16* %ptr, i16 %val) { 5973 ; PPC64LE-LABEL: test348: 5974 ; PPC64LE: # %bb.0: 5975 ; PPC64LE-NEXT: lwsync 5976 ; PPC64LE-NEXT: .LBB348_1: 5977 ; PPC64LE-NEXT: lharx 5, 0, 3 5978 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5979 ; PPC64LE-NEXT: bne 0, .LBB348_1 5980 ; PPC64LE-NEXT: # %bb.2: 5981 ; PPC64LE-NEXT: mr 3, 5 5982 ; PPC64LE-NEXT: lwsync 5983 ; PPC64LE-NEXT: blr 5984 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acq_rel 5985 ret i16 %ret 5986 } 5987 5988 define i16 @test349(i16* %ptr, i16 %val) { 5989 ; PPC64LE-LABEL: test349: 5990 ; PPC64LE: # %bb.0: 5991 ; PPC64LE-NEXT: sync 5992 ; PPC64LE-NEXT: .LBB349_1: 5993 ; PPC64LE-NEXT: lharx 5, 0, 3 5994 ; PPC64LE-NEXT: sthcx. 4, 0, 3 5995 ; PPC64LE-NEXT: bne 0, .LBB349_1 5996 ; PPC64LE-NEXT: # %bb.2: 5997 ; PPC64LE-NEXT: mr 3, 5 5998 ; PPC64LE-NEXT: lwsync 5999 ; PPC64LE-NEXT: blr 6000 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") seq_cst 6001 ret i16 %ret 6002 } 6003 6004 define i32 @test350(i32* %ptr, i32 %val) { 6005 ; PPC64LE-LABEL: test350: 6006 ; PPC64LE: # %bb.0: 6007 ; PPC64LE-NEXT: .LBB350_1: 6008 ; PPC64LE-NEXT: lwarx 5, 0, 3 6009 ; PPC64LE-NEXT: stwcx. 4, 0, 3 6010 ; PPC64LE-NEXT: bne 0, .LBB350_1 6011 ; PPC64LE-NEXT: # %bb.2: 6012 ; PPC64LE-NEXT: mr 3, 5 6013 ; PPC64LE-NEXT: blr 6014 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") monotonic 6015 ret i32 %ret 6016 } 6017 6018 define i32 @test351(i32* %ptr, i32 %val) { 6019 ; PPC64LE-LABEL: test351: 6020 ; PPC64LE: # %bb.0: 6021 ; PPC64LE-NEXT: mr 5, 3 6022 ; PPC64LE-NEXT: .LBB351_1: 6023 ; PPC64LE-NEXT: lwarx 3, 0, 5 6024 ; PPC64LE-NEXT: stwcx. 4, 0, 5 6025 ; PPC64LE-NEXT: bne 0, .LBB351_1 6026 ; PPC64LE-NEXT: # %bb.2: 6027 ; PPC64LE-NEXT: lwsync 6028 ; PPC64LE-NEXT: blr 6029 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acquire 6030 ret i32 %ret 6031 } 6032 6033 define i32 @test352(i32* %ptr, i32 %val) { 6034 ; PPC64LE-LABEL: test352: 6035 ; PPC64LE: # %bb.0: 6036 ; PPC64LE-NEXT: lwsync 6037 ; PPC64LE-NEXT: .LBB352_1: 6038 ; PPC64LE-NEXT: lwarx 5, 0, 3 6039 ; PPC64LE-NEXT: stwcx. 4, 0, 3 6040 ; PPC64LE-NEXT: bne 0, .LBB352_1 6041 ; PPC64LE-NEXT: # %bb.2: 6042 ; PPC64LE-NEXT: mr 3, 5 6043 ; PPC64LE-NEXT: blr 6044 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") release 6045 ret i32 %ret 6046 } 6047 6048 define i32 @test353(i32* %ptr, i32 %val) { 6049 ; PPC64LE-LABEL: test353: 6050 ; PPC64LE: # %bb.0: 6051 ; PPC64LE-NEXT: lwsync 6052 ; PPC64LE-NEXT: .LBB353_1: 6053 ; PPC64LE-NEXT: lwarx 5, 0, 3 6054 ; PPC64LE-NEXT: stwcx. 4, 0, 3 6055 ; PPC64LE-NEXT: bne 0, .LBB353_1 6056 ; PPC64LE-NEXT: # %bb.2: 6057 ; PPC64LE-NEXT: mr 3, 5 6058 ; PPC64LE-NEXT: lwsync 6059 ; PPC64LE-NEXT: blr 6060 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acq_rel 6061 ret i32 %ret 6062 } 6063 6064 define i32 @test354(i32* %ptr, i32 %val) { 6065 ; PPC64LE-LABEL: test354: 6066 ; PPC64LE: # %bb.0: 6067 ; PPC64LE-NEXT: sync 6068 ; PPC64LE-NEXT: .LBB354_1: 6069 ; PPC64LE-NEXT: lwarx 5, 0, 3 6070 ; PPC64LE-NEXT: stwcx. 4, 0, 3 6071 ; PPC64LE-NEXT: bne 0, .LBB354_1 6072 ; PPC64LE-NEXT: # %bb.2: 6073 ; PPC64LE-NEXT: mr 3, 5 6074 ; PPC64LE-NEXT: lwsync 6075 ; PPC64LE-NEXT: blr 6076 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") seq_cst 6077 ret i32 %ret 6078 } 6079 6080 define i64 @test355(i64* %ptr, i64 %val) { 6081 ; PPC64LE-LABEL: test355: 6082 ; PPC64LE: # %bb.0: 6083 ; PPC64LE-NEXT: .LBB355_1: 6084 ; PPC64LE-NEXT: ldarx 5, 0, 3 6085 ; PPC64LE-NEXT: stdcx. 4, 0, 3 6086 ; PPC64LE-NEXT: bne 0, .LBB355_1 6087 ; PPC64LE-NEXT: # %bb.2: 6088 ; PPC64LE-NEXT: mr 3, 5 6089 ; PPC64LE-NEXT: blr 6090 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") monotonic 6091 ret i64 %ret 6092 } 6093 6094 define i64 @test356(i64* %ptr, i64 %val) { 6095 ; PPC64LE-LABEL: test356: 6096 ; PPC64LE: # %bb.0: 6097 ; PPC64LE-NEXT: mr 5, 3 6098 ; PPC64LE-NEXT: .LBB356_1: 6099 ; PPC64LE-NEXT: ldarx 3, 0, 5 6100 ; PPC64LE-NEXT: stdcx. 4, 0, 5 6101 ; PPC64LE-NEXT: bne 0, .LBB356_1 6102 ; PPC64LE-NEXT: # %bb.2: 6103 ; PPC64LE-NEXT: lwsync 6104 ; PPC64LE-NEXT: blr 6105 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acquire 6106 ret i64 %ret 6107 } 6108 6109 define i64 @test357(i64* %ptr, i64 %val) { 6110 ; PPC64LE-LABEL: test357: 6111 ; PPC64LE: # %bb.0: 6112 ; PPC64LE-NEXT: lwsync 6113 ; PPC64LE-NEXT: .LBB357_1: 6114 ; PPC64LE-NEXT: ldarx 5, 0, 3 6115 ; PPC64LE-NEXT: stdcx. 4, 0, 3 6116 ; PPC64LE-NEXT: bne 0, .LBB357_1 6117 ; PPC64LE-NEXT: # %bb.2: 6118 ; PPC64LE-NEXT: mr 3, 5 6119 ; PPC64LE-NEXT: blr 6120 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") release 6121 ret i64 %ret 6122 } 6123 6124 define i64 @test358(i64* %ptr, i64 %val) { 6125 ; PPC64LE-LABEL: test358: 6126 ; PPC64LE: # %bb.0: 6127 ; PPC64LE-NEXT: lwsync 6128 ; PPC64LE-NEXT: .LBB358_1: 6129 ; PPC64LE-NEXT: ldarx 5, 0, 3 6130 ; PPC64LE-NEXT: stdcx. 4, 0, 3 6131 ; PPC64LE-NEXT: bne 0, .LBB358_1 6132 ; PPC64LE-NEXT: # %bb.2: 6133 ; PPC64LE-NEXT: mr 3, 5 6134 ; PPC64LE-NEXT: lwsync 6135 ; PPC64LE-NEXT: blr 6136 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acq_rel 6137 ret i64 %ret 6138 } 6139 6140 define i64 @test359(i64* %ptr, i64 %val) { 6141 ; PPC64LE-LABEL: test359: 6142 ; PPC64LE: # %bb.0: 6143 ; PPC64LE-NEXT: sync 6144 ; PPC64LE-NEXT: .LBB359_1: 6145 ; PPC64LE-NEXT: ldarx 5, 0, 3 6146 ; PPC64LE-NEXT: stdcx. 4, 0, 3 6147 ; PPC64LE-NEXT: bne 0, .LBB359_1 6148 ; PPC64LE-NEXT: # %bb.2: 6149 ; PPC64LE-NEXT: mr 3, 5 6150 ; PPC64LE-NEXT: lwsync 6151 ; PPC64LE-NEXT: blr 6152 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") seq_cst 6153 ret i64 %ret 6154 } 6155 6156 define i8 @test360(i8* %ptr, i8 %val) { 6157 ; PPC64LE-LABEL: test360: 6158 ; PPC64LE: # %bb.0: 6159 ; PPC64LE-NEXT: .LBB360_1: 6160 ; PPC64LE-NEXT: lbarx 5, 0, 3 6161 ; PPC64LE-NEXT: add 6, 4, 5 6162 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6163 ; PPC64LE-NEXT: bne 0, .LBB360_1 6164 ; PPC64LE-NEXT: # %bb.2: 6165 ; PPC64LE-NEXT: mr 3, 5 6166 ; PPC64LE-NEXT: blr 6167 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") monotonic 6168 ret i8 %ret 6169 } 6170 6171 define i8 @test361(i8* %ptr, i8 %val) { 6172 ; PPC64LE-LABEL: test361: 6173 ; PPC64LE: # %bb.0: 6174 ; PPC64LE-NEXT: mr 5, 3 6175 ; PPC64LE-NEXT: .LBB361_1: 6176 ; PPC64LE-NEXT: lbarx 3, 0, 5 6177 ; PPC64LE-NEXT: add 6, 4, 3 6178 ; PPC64LE-NEXT: stbcx. 6, 0, 5 6179 ; PPC64LE-NEXT: bne 0, .LBB361_1 6180 ; PPC64LE-NEXT: # %bb.2: 6181 ; PPC64LE-NEXT: lwsync 6182 ; PPC64LE-NEXT: blr 6183 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acquire 6184 ret i8 %ret 6185 } 6186 6187 define i8 @test362(i8* %ptr, i8 %val) { 6188 ; PPC64LE-LABEL: test362: 6189 ; PPC64LE: # %bb.0: 6190 ; PPC64LE-NEXT: lwsync 6191 ; PPC64LE-NEXT: .LBB362_1: 6192 ; PPC64LE-NEXT: lbarx 5, 0, 3 6193 ; PPC64LE-NEXT: add 6, 4, 5 6194 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6195 ; PPC64LE-NEXT: bne 0, .LBB362_1 6196 ; PPC64LE-NEXT: # %bb.2: 6197 ; PPC64LE-NEXT: mr 3, 5 6198 ; PPC64LE-NEXT: blr 6199 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") release 6200 ret i8 %ret 6201 } 6202 6203 define i8 @test363(i8* %ptr, i8 %val) { 6204 ; PPC64LE-LABEL: test363: 6205 ; PPC64LE: # %bb.0: 6206 ; PPC64LE-NEXT: lwsync 6207 ; PPC64LE-NEXT: .LBB363_1: 6208 ; PPC64LE-NEXT: lbarx 5, 0, 3 6209 ; PPC64LE-NEXT: add 6, 4, 5 6210 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6211 ; PPC64LE-NEXT: bne 0, .LBB363_1 6212 ; PPC64LE-NEXT: # %bb.2: 6213 ; PPC64LE-NEXT: mr 3, 5 6214 ; PPC64LE-NEXT: lwsync 6215 ; PPC64LE-NEXT: blr 6216 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acq_rel 6217 ret i8 %ret 6218 } 6219 6220 define i8 @test364(i8* %ptr, i8 %val) { 6221 ; PPC64LE-LABEL: test364: 6222 ; PPC64LE: # %bb.0: 6223 ; PPC64LE-NEXT: sync 6224 ; PPC64LE-NEXT: .LBB364_1: 6225 ; PPC64LE-NEXT: lbarx 5, 0, 3 6226 ; PPC64LE-NEXT: add 6, 4, 5 6227 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6228 ; PPC64LE-NEXT: bne 0, .LBB364_1 6229 ; PPC64LE-NEXT: # %bb.2: 6230 ; PPC64LE-NEXT: mr 3, 5 6231 ; PPC64LE-NEXT: lwsync 6232 ; PPC64LE-NEXT: blr 6233 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") seq_cst 6234 ret i8 %ret 6235 } 6236 6237 define i16 @test365(i16* %ptr, i16 %val) { 6238 ; PPC64LE-LABEL: test365: 6239 ; PPC64LE: # %bb.0: 6240 ; PPC64LE-NEXT: .LBB365_1: 6241 ; PPC64LE-NEXT: lharx 5, 0, 3 6242 ; PPC64LE-NEXT: add 6, 4, 5 6243 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6244 ; PPC64LE-NEXT: bne 0, .LBB365_1 6245 ; PPC64LE-NEXT: # %bb.2: 6246 ; PPC64LE-NEXT: mr 3, 5 6247 ; PPC64LE-NEXT: blr 6248 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") monotonic 6249 ret i16 %ret 6250 } 6251 6252 define i16 @test366(i16* %ptr, i16 %val) { 6253 ; PPC64LE-LABEL: test366: 6254 ; PPC64LE: # %bb.0: 6255 ; PPC64LE-NEXT: mr 5, 3 6256 ; PPC64LE-NEXT: .LBB366_1: 6257 ; PPC64LE-NEXT: lharx 3, 0, 5 6258 ; PPC64LE-NEXT: add 6, 4, 3 6259 ; PPC64LE-NEXT: sthcx. 6, 0, 5 6260 ; PPC64LE-NEXT: bne 0, .LBB366_1 6261 ; PPC64LE-NEXT: # %bb.2: 6262 ; PPC64LE-NEXT: lwsync 6263 ; PPC64LE-NEXT: blr 6264 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acquire 6265 ret i16 %ret 6266 } 6267 6268 define i16 @test367(i16* %ptr, i16 %val) { 6269 ; PPC64LE-LABEL: test367: 6270 ; PPC64LE: # %bb.0: 6271 ; PPC64LE-NEXT: lwsync 6272 ; PPC64LE-NEXT: .LBB367_1: 6273 ; PPC64LE-NEXT: lharx 5, 0, 3 6274 ; PPC64LE-NEXT: add 6, 4, 5 6275 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6276 ; PPC64LE-NEXT: bne 0, .LBB367_1 6277 ; PPC64LE-NEXT: # %bb.2: 6278 ; PPC64LE-NEXT: mr 3, 5 6279 ; PPC64LE-NEXT: blr 6280 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") release 6281 ret i16 %ret 6282 } 6283 6284 define i16 @test368(i16* %ptr, i16 %val) { 6285 ; PPC64LE-LABEL: test368: 6286 ; PPC64LE: # %bb.0: 6287 ; PPC64LE-NEXT: lwsync 6288 ; PPC64LE-NEXT: .LBB368_1: 6289 ; PPC64LE-NEXT: lharx 5, 0, 3 6290 ; PPC64LE-NEXT: add 6, 4, 5 6291 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6292 ; PPC64LE-NEXT: bne 0, .LBB368_1 6293 ; PPC64LE-NEXT: # %bb.2: 6294 ; PPC64LE-NEXT: mr 3, 5 6295 ; PPC64LE-NEXT: lwsync 6296 ; PPC64LE-NEXT: blr 6297 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acq_rel 6298 ret i16 %ret 6299 } 6300 6301 define i16 @test369(i16* %ptr, i16 %val) { 6302 ; PPC64LE-LABEL: test369: 6303 ; PPC64LE: # %bb.0: 6304 ; PPC64LE-NEXT: sync 6305 ; PPC64LE-NEXT: .LBB369_1: 6306 ; PPC64LE-NEXT: lharx 5, 0, 3 6307 ; PPC64LE-NEXT: add 6, 4, 5 6308 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6309 ; PPC64LE-NEXT: bne 0, .LBB369_1 6310 ; PPC64LE-NEXT: # %bb.2: 6311 ; PPC64LE-NEXT: mr 3, 5 6312 ; PPC64LE-NEXT: lwsync 6313 ; PPC64LE-NEXT: blr 6314 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") seq_cst 6315 ret i16 %ret 6316 } 6317 6318 define i32 @test370(i32* %ptr, i32 %val) { 6319 ; PPC64LE-LABEL: test370: 6320 ; PPC64LE: # %bb.0: 6321 ; PPC64LE-NEXT: .LBB370_1: 6322 ; PPC64LE-NEXT: lwarx 5, 0, 3 6323 ; PPC64LE-NEXT: add 6, 4, 5 6324 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6325 ; PPC64LE-NEXT: bne 0, .LBB370_1 6326 ; PPC64LE-NEXT: # %bb.2: 6327 ; PPC64LE-NEXT: mr 3, 5 6328 ; PPC64LE-NEXT: blr 6329 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") monotonic 6330 ret i32 %ret 6331 } 6332 6333 define i32 @test371(i32* %ptr, i32 %val) { 6334 ; PPC64LE-LABEL: test371: 6335 ; PPC64LE: # %bb.0: 6336 ; PPC64LE-NEXT: mr 5, 3 6337 ; PPC64LE-NEXT: .LBB371_1: 6338 ; PPC64LE-NEXT: lwarx 3, 0, 5 6339 ; PPC64LE-NEXT: add 6, 4, 3 6340 ; PPC64LE-NEXT: stwcx. 6, 0, 5 6341 ; PPC64LE-NEXT: bne 0, .LBB371_1 6342 ; PPC64LE-NEXT: # %bb.2: 6343 ; PPC64LE-NEXT: lwsync 6344 ; PPC64LE-NEXT: blr 6345 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acquire 6346 ret i32 %ret 6347 } 6348 6349 define i32 @test372(i32* %ptr, i32 %val) { 6350 ; PPC64LE-LABEL: test372: 6351 ; PPC64LE: # %bb.0: 6352 ; PPC64LE-NEXT: lwsync 6353 ; PPC64LE-NEXT: .LBB372_1: 6354 ; PPC64LE-NEXT: lwarx 5, 0, 3 6355 ; PPC64LE-NEXT: add 6, 4, 5 6356 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6357 ; PPC64LE-NEXT: bne 0, .LBB372_1 6358 ; PPC64LE-NEXT: # %bb.2: 6359 ; PPC64LE-NEXT: mr 3, 5 6360 ; PPC64LE-NEXT: blr 6361 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") release 6362 ret i32 %ret 6363 } 6364 6365 define i32 @test373(i32* %ptr, i32 %val) { 6366 ; PPC64LE-LABEL: test373: 6367 ; PPC64LE: # %bb.0: 6368 ; PPC64LE-NEXT: lwsync 6369 ; PPC64LE-NEXT: .LBB373_1: 6370 ; PPC64LE-NEXT: lwarx 5, 0, 3 6371 ; PPC64LE-NEXT: add 6, 4, 5 6372 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6373 ; PPC64LE-NEXT: bne 0, .LBB373_1 6374 ; PPC64LE-NEXT: # %bb.2: 6375 ; PPC64LE-NEXT: mr 3, 5 6376 ; PPC64LE-NEXT: lwsync 6377 ; PPC64LE-NEXT: blr 6378 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acq_rel 6379 ret i32 %ret 6380 } 6381 6382 define i32 @test374(i32* %ptr, i32 %val) { 6383 ; PPC64LE-LABEL: test374: 6384 ; PPC64LE: # %bb.0: 6385 ; PPC64LE-NEXT: sync 6386 ; PPC64LE-NEXT: .LBB374_1: 6387 ; PPC64LE-NEXT: lwarx 5, 0, 3 6388 ; PPC64LE-NEXT: add 6, 4, 5 6389 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6390 ; PPC64LE-NEXT: bne 0, .LBB374_1 6391 ; PPC64LE-NEXT: # %bb.2: 6392 ; PPC64LE-NEXT: mr 3, 5 6393 ; PPC64LE-NEXT: lwsync 6394 ; PPC64LE-NEXT: blr 6395 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") seq_cst 6396 ret i32 %ret 6397 } 6398 6399 define i64 @test375(i64* %ptr, i64 %val) { 6400 ; PPC64LE-LABEL: test375: 6401 ; PPC64LE: # %bb.0: 6402 ; PPC64LE-NEXT: .LBB375_1: 6403 ; PPC64LE-NEXT: ldarx 5, 0, 3 6404 ; PPC64LE-NEXT: add 6, 4, 5 6405 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6406 ; PPC64LE-NEXT: bne 0, .LBB375_1 6407 ; PPC64LE-NEXT: # %bb.2: 6408 ; PPC64LE-NEXT: mr 3, 5 6409 ; PPC64LE-NEXT: blr 6410 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") monotonic 6411 ret i64 %ret 6412 } 6413 6414 define i64 @test376(i64* %ptr, i64 %val) { 6415 ; PPC64LE-LABEL: test376: 6416 ; PPC64LE: # %bb.0: 6417 ; PPC64LE-NEXT: mr 5, 3 6418 ; PPC64LE-NEXT: .LBB376_1: 6419 ; PPC64LE-NEXT: ldarx 3, 0, 5 6420 ; PPC64LE-NEXT: add 6, 4, 3 6421 ; PPC64LE-NEXT: stdcx. 6, 0, 5 6422 ; PPC64LE-NEXT: bne 0, .LBB376_1 6423 ; PPC64LE-NEXT: # %bb.2: 6424 ; PPC64LE-NEXT: lwsync 6425 ; PPC64LE-NEXT: blr 6426 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acquire 6427 ret i64 %ret 6428 } 6429 6430 define i64 @test377(i64* %ptr, i64 %val) { 6431 ; PPC64LE-LABEL: test377: 6432 ; PPC64LE: # %bb.0: 6433 ; PPC64LE-NEXT: lwsync 6434 ; PPC64LE-NEXT: .LBB377_1: 6435 ; PPC64LE-NEXT: ldarx 5, 0, 3 6436 ; PPC64LE-NEXT: add 6, 4, 5 6437 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6438 ; PPC64LE-NEXT: bne 0, .LBB377_1 6439 ; PPC64LE-NEXT: # %bb.2: 6440 ; PPC64LE-NEXT: mr 3, 5 6441 ; PPC64LE-NEXT: blr 6442 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") release 6443 ret i64 %ret 6444 } 6445 6446 define i64 @test378(i64* %ptr, i64 %val) { 6447 ; PPC64LE-LABEL: test378: 6448 ; PPC64LE: # %bb.0: 6449 ; PPC64LE-NEXT: lwsync 6450 ; PPC64LE-NEXT: .LBB378_1: 6451 ; PPC64LE-NEXT: ldarx 5, 0, 3 6452 ; PPC64LE-NEXT: add 6, 4, 5 6453 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6454 ; PPC64LE-NEXT: bne 0, .LBB378_1 6455 ; PPC64LE-NEXT: # %bb.2: 6456 ; PPC64LE-NEXT: mr 3, 5 6457 ; PPC64LE-NEXT: lwsync 6458 ; PPC64LE-NEXT: blr 6459 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acq_rel 6460 ret i64 %ret 6461 } 6462 6463 define i64 @test379(i64* %ptr, i64 %val) { 6464 ; PPC64LE-LABEL: test379: 6465 ; PPC64LE: # %bb.0: 6466 ; PPC64LE-NEXT: sync 6467 ; PPC64LE-NEXT: .LBB379_1: 6468 ; PPC64LE-NEXT: ldarx 5, 0, 3 6469 ; PPC64LE-NEXT: add 6, 4, 5 6470 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6471 ; PPC64LE-NEXT: bne 0, .LBB379_1 6472 ; PPC64LE-NEXT: # %bb.2: 6473 ; PPC64LE-NEXT: mr 3, 5 6474 ; PPC64LE-NEXT: lwsync 6475 ; PPC64LE-NEXT: blr 6476 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") seq_cst 6477 ret i64 %ret 6478 } 6479 6480 define i8 @test380(i8* %ptr, i8 %val) { 6481 ; PPC64LE-LABEL: test380: 6482 ; PPC64LE: # %bb.0: 6483 ; PPC64LE-NEXT: .LBB380_1: 6484 ; PPC64LE-NEXT: lbarx 5, 0, 3 6485 ; PPC64LE-NEXT: subf 6, 4, 5 6486 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6487 ; PPC64LE-NEXT: bne 0, .LBB380_1 6488 ; PPC64LE-NEXT: # %bb.2: 6489 ; PPC64LE-NEXT: mr 3, 5 6490 ; PPC64LE-NEXT: blr 6491 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic 6492 ret i8 %ret 6493 } 6494 6495 define i8 @test381(i8* %ptr, i8 %val) { 6496 ; PPC64LE-LABEL: test381: 6497 ; PPC64LE: # %bb.0: 6498 ; PPC64LE-NEXT: mr 5, 3 6499 ; PPC64LE-NEXT: .LBB381_1: 6500 ; PPC64LE-NEXT: lbarx 3, 0, 5 6501 ; PPC64LE-NEXT: subf 6, 4, 3 6502 ; PPC64LE-NEXT: stbcx. 6, 0, 5 6503 ; PPC64LE-NEXT: bne 0, .LBB381_1 6504 ; PPC64LE-NEXT: # %bb.2: 6505 ; PPC64LE-NEXT: lwsync 6506 ; PPC64LE-NEXT: blr 6507 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire 6508 ret i8 %ret 6509 } 6510 6511 define i8 @test382(i8* %ptr, i8 %val) { 6512 ; PPC64LE-LABEL: test382: 6513 ; PPC64LE: # %bb.0: 6514 ; PPC64LE-NEXT: lwsync 6515 ; PPC64LE-NEXT: .LBB382_1: 6516 ; PPC64LE-NEXT: lbarx 5, 0, 3 6517 ; PPC64LE-NEXT: subf 6, 4, 5 6518 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6519 ; PPC64LE-NEXT: bne 0, .LBB382_1 6520 ; PPC64LE-NEXT: # %bb.2: 6521 ; PPC64LE-NEXT: mr 3, 5 6522 ; PPC64LE-NEXT: blr 6523 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release 6524 ret i8 %ret 6525 } 6526 6527 define i8 @test383(i8* %ptr, i8 %val) { 6528 ; PPC64LE-LABEL: test383: 6529 ; PPC64LE: # %bb.0: 6530 ; PPC64LE-NEXT: lwsync 6531 ; PPC64LE-NEXT: .LBB383_1: 6532 ; PPC64LE-NEXT: lbarx 5, 0, 3 6533 ; PPC64LE-NEXT: subf 6, 4, 5 6534 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6535 ; PPC64LE-NEXT: bne 0, .LBB383_1 6536 ; PPC64LE-NEXT: # %bb.2: 6537 ; PPC64LE-NEXT: mr 3, 5 6538 ; PPC64LE-NEXT: lwsync 6539 ; PPC64LE-NEXT: blr 6540 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acq_rel 6541 ret i8 %ret 6542 } 6543 6544 define i8 @test384(i8* %ptr, i8 %val) { 6545 ; PPC64LE-LABEL: test384: 6546 ; PPC64LE: # %bb.0: 6547 ; PPC64LE-NEXT: sync 6548 ; PPC64LE-NEXT: .LBB384_1: 6549 ; PPC64LE-NEXT: lbarx 5, 0, 3 6550 ; PPC64LE-NEXT: subf 6, 4, 5 6551 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6552 ; PPC64LE-NEXT: bne 0, .LBB384_1 6553 ; PPC64LE-NEXT: # %bb.2: 6554 ; PPC64LE-NEXT: mr 3, 5 6555 ; PPC64LE-NEXT: lwsync 6556 ; PPC64LE-NEXT: blr 6557 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") seq_cst 6558 ret i8 %ret 6559 } 6560 6561 define i16 @test385(i16* %ptr, i16 %val) { 6562 ; PPC64LE-LABEL: test385: 6563 ; PPC64LE: # %bb.0: 6564 ; PPC64LE-NEXT: .LBB385_1: 6565 ; PPC64LE-NEXT: lharx 5, 0, 3 6566 ; PPC64LE-NEXT: subf 6, 4, 5 6567 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6568 ; PPC64LE-NEXT: bne 0, .LBB385_1 6569 ; PPC64LE-NEXT: # %bb.2: 6570 ; PPC64LE-NEXT: mr 3, 5 6571 ; PPC64LE-NEXT: blr 6572 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic 6573 ret i16 %ret 6574 } 6575 6576 define i16 @test386(i16* %ptr, i16 %val) { 6577 ; PPC64LE-LABEL: test386: 6578 ; PPC64LE: # %bb.0: 6579 ; PPC64LE-NEXT: mr 5, 3 6580 ; PPC64LE-NEXT: .LBB386_1: 6581 ; PPC64LE-NEXT: lharx 3, 0, 5 6582 ; PPC64LE-NEXT: subf 6, 4, 3 6583 ; PPC64LE-NEXT: sthcx. 6, 0, 5 6584 ; PPC64LE-NEXT: bne 0, .LBB386_1 6585 ; PPC64LE-NEXT: # %bb.2: 6586 ; PPC64LE-NEXT: lwsync 6587 ; PPC64LE-NEXT: blr 6588 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire 6589 ret i16 %ret 6590 } 6591 6592 define i16 @test387(i16* %ptr, i16 %val) { 6593 ; PPC64LE-LABEL: test387: 6594 ; PPC64LE: # %bb.0: 6595 ; PPC64LE-NEXT: lwsync 6596 ; PPC64LE-NEXT: .LBB387_1: 6597 ; PPC64LE-NEXT: lharx 5, 0, 3 6598 ; PPC64LE-NEXT: subf 6, 4, 5 6599 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6600 ; PPC64LE-NEXT: bne 0, .LBB387_1 6601 ; PPC64LE-NEXT: # %bb.2: 6602 ; PPC64LE-NEXT: mr 3, 5 6603 ; PPC64LE-NEXT: blr 6604 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release 6605 ret i16 %ret 6606 } 6607 6608 define i16 @test388(i16* %ptr, i16 %val) { 6609 ; PPC64LE-LABEL: test388: 6610 ; PPC64LE: # %bb.0: 6611 ; PPC64LE-NEXT: lwsync 6612 ; PPC64LE-NEXT: .LBB388_1: 6613 ; PPC64LE-NEXT: lharx 5, 0, 3 6614 ; PPC64LE-NEXT: subf 6, 4, 5 6615 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6616 ; PPC64LE-NEXT: bne 0, .LBB388_1 6617 ; PPC64LE-NEXT: # %bb.2: 6618 ; PPC64LE-NEXT: mr 3, 5 6619 ; PPC64LE-NEXT: lwsync 6620 ; PPC64LE-NEXT: blr 6621 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acq_rel 6622 ret i16 %ret 6623 } 6624 6625 define i16 @test389(i16* %ptr, i16 %val) { 6626 ; PPC64LE-LABEL: test389: 6627 ; PPC64LE: # %bb.0: 6628 ; PPC64LE-NEXT: sync 6629 ; PPC64LE-NEXT: .LBB389_1: 6630 ; PPC64LE-NEXT: lharx 5, 0, 3 6631 ; PPC64LE-NEXT: subf 6, 4, 5 6632 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6633 ; PPC64LE-NEXT: bne 0, .LBB389_1 6634 ; PPC64LE-NEXT: # %bb.2: 6635 ; PPC64LE-NEXT: mr 3, 5 6636 ; PPC64LE-NEXT: lwsync 6637 ; PPC64LE-NEXT: blr 6638 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") seq_cst 6639 ret i16 %ret 6640 } 6641 6642 define i32 @test390(i32* %ptr, i32 %val) { 6643 ; PPC64LE-LABEL: test390: 6644 ; PPC64LE: # %bb.0: 6645 ; PPC64LE-NEXT: .LBB390_1: 6646 ; PPC64LE-NEXT: lwarx 5, 0, 3 6647 ; PPC64LE-NEXT: subf 6, 4, 5 6648 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6649 ; PPC64LE-NEXT: bne 0, .LBB390_1 6650 ; PPC64LE-NEXT: # %bb.2: 6651 ; PPC64LE-NEXT: mr 3, 5 6652 ; PPC64LE-NEXT: blr 6653 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic 6654 ret i32 %ret 6655 } 6656 6657 define i32 @test391(i32* %ptr, i32 %val) { 6658 ; PPC64LE-LABEL: test391: 6659 ; PPC64LE: # %bb.0: 6660 ; PPC64LE-NEXT: mr 5, 3 6661 ; PPC64LE-NEXT: .LBB391_1: 6662 ; PPC64LE-NEXT: lwarx 3, 0, 5 6663 ; PPC64LE-NEXT: subf 6, 4, 3 6664 ; PPC64LE-NEXT: stwcx. 6, 0, 5 6665 ; PPC64LE-NEXT: bne 0, .LBB391_1 6666 ; PPC64LE-NEXT: # %bb.2: 6667 ; PPC64LE-NEXT: lwsync 6668 ; PPC64LE-NEXT: blr 6669 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire 6670 ret i32 %ret 6671 } 6672 6673 define i32 @test392(i32* %ptr, i32 %val) { 6674 ; PPC64LE-LABEL: test392: 6675 ; PPC64LE: # %bb.0: 6676 ; PPC64LE-NEXT: lwsync 6677 ; PPC64LE-NEXT: .LBB392_1: 6678 ; PPC64LE-NEXT: lwarx 5, 0, 3 6679 ; PPC64LE-NEXT: subf 6, 4, 5 6680 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6681 ; PPC64LE-NEXT: bne 0, .LBB392_1 6682 ; PPC64LE-NEXT: # %bb.2: 6683 ; PPC64LE-NEXT: mr 3, 5 6684 ; PPC64LE-NEXT: blr 6685 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release 6686 ret i32 %ret 6687 } 6688 6689 define i32 @test393(i32* %ptr, i32 %val) { 6690 ; PPC64LE-LABEL: test393: 6691 ; PPC64LE: # %bb.0: 6692 ; PPC64LE-NEXT: lwsync 6693 ; PPC64LE-NEXT: .LBB393_1: 6694 ; PPC64LE-NEXT: lwarx 5, 0, 3 6695 ; PPC64LE-NEXT: subf 6, 4, 5 6696 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6697 ; PPC64LE-NEXT: bne 0, .LBB393_1 6698 ; PPC64LE-NEXT: # %bb.2: 6699 ; PPC64LE-NEXT: mr 3, 5 6700 ; PPC64LE-NEXT: lwsync 6701 ; PPC64LE-NEXT: blr 6702 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acq_rel 6703 ret i32 %ret 6704 } 6705 6706 define i32 @test394(i32* %ptr, i32 %val) { 6707 ; PPC64LE-LABEL: test394: 6708 ; PPC64LE: # %bb.0: 6709 ; PPC64LE-NEXT: sync 6710 ; PPC64LE-NEXT: .LBB394_1: 6711 ; PPC64LE-NEXT: lwarx 5, 0, 3 6712 ; PPC64LE-NEXT: subf 6, 4, 5 6713 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6714 ; PPC64LE-NEXT: bne 0, .LBB394_1 6715 ; PPC64LE-NEXT: # %bb.2: 6716 ; PPC64LE-NEXT: mr 3, 5 6717 ; PPC64LE-NEXT: lwsync 6718 ; PPC64LE-NEXT: blr 6719 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") seq_cst 6720 ret i32 %ret 6721 } 6722 6723 define i64 @test395(i64* %ptr, i64 %val) { 6724 ; PPC64LE-LABEL: test395: 6725 ; PPC64LE: # %bb.0: 6726 ; PPC64LE-NEXT: .LBB395_1: 6727 ; PPC64LE-NEXT: ldarx 5, 0, 3 6728 ; PPC64LE-NEXT: sub 6, 5, 4 6729 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6730 ; PPC64LE-NEXT: bne 0, .LBB395_1 6731 ; PPC64LE-NEXT: # %bb.2: 6732 ; PPC64LE-NEXT: mr 3, 5 6733 ; PPC64LE-NEXT: blr 6734 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") monotonic 6735 ret i64 %ret 6736 } 6737 6738 define i64 @test396(i64* %ptr, i64 %val) { 6739 ; PPC64LE-LABEL: test396: 6740 ; PPC64LE: # %bb.0: 6741 ; PPC64LE-NEXT: mr 5, 3 6742 ; PPC64LE-NEXT: .LBB396_1: 6743 ; PPC64LE-NEXT: ldarx 3, 0, 5 6744 ; PPC64LE-NEXT: sub 6, 3, 4 6745 ; PPC64LE-NEXT: stdcx. 6, 0, 5 6746 ; PPC64LE-NEXT: bne 0, .LBB396_1 6747 ; PPC64LE-NEXT: # %bb.2: 6748 ; PPC64LE-NEXT: lwsync 6749 ; PPC64LE-NEXT: blr 6750 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acquire 6751 ret i64 %ret 6752 } 6753 6754 define i64 @test397(i64* %ptr, i64 %val) { 6755 ; PPC64LE-LABEL: test397: 6756 ; PPC64LE: # %bb.0: 6757 ; PPC64LE-NEXT: lwsync 6758 ; PPC64LE-NEXT: .LBB397_1: 6759 ; PPC64LE-NEXT: ldarx 5, 0, 3 6760 ; PPC64LE-NEXT: sub 6, 5, 4 6761 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6762 ; PPC64LE-NEXT: bne 0, .LBB397_1 6763 ; PPC64LE-NEXT: # %bb.2: 6764 ; PPC64LE-NEXT: mr 3, 5 6765 ; PPC64LE-NEXT: blr 6766 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") release 6767 ret i64 %ret 6768 } 6769 6770 define i64 @test398(i64* %ptr, i64 %val) { 6771 ; PPC64LE-LABEL: test398: 6772 ; PPC64LE: # %bb.0: 6773 ; PPC64LE-NEXT: lwsync 6774 ; PPC64LE-NEXT: .LBB398_1: 6775 ; PPC64LE-NEXT: ldarx 5, 0, 3 6776 ; PPC64LE-NEXT: sub 6, 5, 4 6777 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6778 ; PPC64LE-NEXT: bne 0, .LBB398_1 6779 ; PPC64LE-NEXT: # %bb.2: 6780 ; PPC64LE-NEXT: mr 3, 5 6781 ; PPC64LE-NEXT: lwsync 6782 ; PPC64LE-NEXT: blr 6783 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acq_rel 6784 ret i64 %ret 6785 } 6786 6787 define i64 @test399(i64* %ptr, i64 %val) { 6788 ; PPC64LE-LABEL: test399: 6789 ; PPC64LE: # %bb.0: 6790 ; PPC64LE-NEXT: sync 6791 ; PPC64LE-NEXT: .LBB399_1: 6792 ; PPC64LE-NEXT: ldarx 5, 0, 3 6793 ; PPC64LE-NEXT: sub 6, 5, 4 6794 ; PPC64LE-NEXT: stdcx. 6, 0, 3 6795 ; PPC64LE-NEXT: bne 0, .LBB399_1 6796 ; PPC64LE-NEXT: # %bb.2: 6797 ; PPC64LE-NEXT: mr 3, 5 6798 ; PPC64LE-NEXT: lwsync 6799 ; PPC64LE-NEXT: blr 6800 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") seq_cst 6801 ret i64 %ret 6802 } 6803 6804 define i8 @test400(i8* %ptr, i8 %val) { 6805 ; PPC64LE-LABEL: test400: 6806 ; PPC64LE: # %bb.0: 6807 ; PPC64LE-NEXT: .LBB400_1: 6808 ; PPC64LE-NEXT: lbarx 5, 0, 3 6809 ; PPC64LE-NEXT: and 6, 4, 5 6810 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6811 ; PPC64LE-NEXT: bne 0, .LBB400_1 6812 ; PPC64LE-NEXT: # %bb.2: 6813 ; PPC64LE-NEXT: mr 3, 5 6814 ; PPC64LE-NEXT: blr 6815 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") monotonic 6816 ret i8 %ret 6817 } 6818 6819 define i8 @test401(i8* %ptr, i8 %val) { 6820 ; PPC64LE-LABEL: test401: 6821 ; PPC64LE: # %bb.0: 6822 ; PPC64LE-NEXT: mr 5, 3 6823 ; PPC64LE-NEXT: .LBB401_1: 6824 ; PPC64LE-NEXT: lbarx 3, 0, 5 6825 ; PPC64LE-NEXT: and 6, 4, 3 6826 ; PPC64LE-NEXT: stbcx. 6, 0, 5 6827 ; PPC64LE-NEXT: bne 0, .LBB401_1 6828 ; PPC64LE-NEXT: # %bb.2: 6829 ; PPC64LE-NEXT: lwsync 6830 ; PPC64LE-NEXT: blr 6831 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acquire 6832 ret i8 %ret 6833 } 6834 6835 define i8 @test402(i8* %ptr, i8 %val) { 6836 ; PPC64LE-LABEL: test402: 6837 ; PPC64LE: # %bb.0: 6838 ; PPC64LE-NEXT: lwsync 6839 ; PPC64LE-NEXT: .LBB402_1: 6840 ; PPC64LE-NEXT: lbarx 5, 0, 3 6841 ; PPC64LE-NEXT: and 6, 4, 5 6842 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6843 ; PPC64LE-NEXT: bne 0, .LBB402_1 6844 ; PPC64LE-NEXT: # %bb.2: 6845 ; PPC64LE-NEXT: mr 3, 5 6846 ; PPC64LE-NEXT: blr 6847 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") release 6848 ret i8 %ret 6849 } 6850 6851 define i8 @test403(i8* %ptr, i8 %val) { 6852 ; PPC64LE-LABEL: test403: 6853 ; PPC64LE: # %bb.0: 6854 ; PPC64LE-NEXT: lwsync 6855 ; PPC64LE-NEXT: .LBB403_1: 6856 ; PPC64LE-NEXT: lbarx 5, 0, 3 6857 ; PPC64LE-NEXT: and 6, 4, 5 6858 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6859 ; PPC64LE-NEXT: bne 0, .LBB403_1 6860 ; PPC64LE-NEXT: # %bb.2: 6861 ; PPC64LE-NEXT: mr 3, 5 6862 ; PPC64LE-NEXT: lwsync 6863 ; PPC64LE-NEXT: blr 6864 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acq_rel 6865 ret i8 %ret 6866 } 6867 6868 define i8 @test404(i8* %ptr, i8 %val) { 6869 ; PPC64LE-LABEL: test404: 6870 ; PPC64LE: # %bb.0: 6871 ; PPC64LE-NEXT: sync 6872 ; PPC64LE-NEXT: .LBB404_1: 6873 ; PPC64LE-NEXT: lbarx 5, 0, 3 6874 ; PPC64LE-NEXT: and 6, 4, 5 6875 ; PPC64LE-NEXT: stbcx. 6, 0, 3 6876 ; PPC64LE-NEXT: bne 0, .LBB404_1 6877 ; PPC64LE-NEXT: # %bb.2: 6878 ; PPC64LE-NEXT: mr 3, 5 6879 ; PPC64LE-NEXT: lwsync 6880 ; PPC64LE-NEXT: blr 6881 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") seq_cst 6882 ret i8 %ret 6883 } 6884 6885 define i16 @test405(i16* %ptr, i16 %val) { 6886 ; PPC64LE-LABEL: test405: 6887 ; PPC64LE: # %bb.0: 6888 ; PPC64LE-NEXT: .LBB405_1: 6889 ; PPC64LE-NEXT: lharx 5, 0, 3 6890 ; PPC64LE-NEXT: and 6, 4, 5 6891 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6892 ; PPC64LE-NEXT: bne 0, .LBB405_1 6893 ; PPC64LE-NEXT: # %bb.2: 6894 ; PPC64LE-NEXT: mr 3, 5 6895 ; PPC64LE-NEXT: blr 6896 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") monotonic 6897 ret i16 %ret 6898 } 6899 6900 define i16 @test406(i16* %ptr, i16 %val) { 6901 ; PPC64LE-LABEL: test406: 6902 ; PPC64LE: # %bb.0: 6903 ; PPC64LE-NEXT: mr 5, 3 6904 ; PPC64LE-NEXT: .LBB406_1: 6905 ; PPC64LE-NEXT: lharx 3, 0, 5 6906 ; PPC64LE-NEXT: and 6, 4, 3 6907 ; PPC64LE-NEXT: sthcx. 6, 0, 5 6908 ; PPC64LE-NEXT: bne 0, .LBB406_1 6909 ; PPC64LE-NEXT: # %bb.2: 6910 ; PPC64LE-NEXT: lwsync 6911 ; PPC64LE-NEXT: blr 6912 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acquire 6913 ret i16 %ret 6914 } 6915 6916 define i16 @test407(i16* %ptr, i16 %val) { 6917 ; PPC64LE-LABEL: test407: 6918 ; PPC64LE: # %bb.0: 6919 ; PPC64LE-NEXT: lwsync 6920 ; PPC64LE-NEXT: .LBB407_1: 6921 ; PPC64LE-NEXT: lharx 5, 0, 3 6922 ; PPC64LE-NEXT: and 6, 4, 5 6923 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6924 ; PPC64LE-NEXT: bne 0, .LBB407_1 6925 ; PPC64LE-NEXT: # %bb.2: 6926 ; PPC64LE-NEXT: mr 3, 5 6927 ; PPC64LE-NEXT: blr 6928 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") release 6929 ret i16 %ret 6930 } 6931 6932 define i16 @test408(i16* %ptr, i16 %val) { 6933 ; PPC64LE-LABEL: test408: 6934 ; PPC64LE: # %bb.0: 6935 ; PPC64LE-NEXT: lwsync 6936 ; PPC64LE-NEXT: .LBB408_1: 6937 ; PPC64LE-NEXT: lharx 5, 0, 3 6938 ; PPC64LE-NEXT: and 6, 4, 5 6939 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6940 ; PPC64LE-NEXT: bne 0, .LBB408_1 6941 ; PPC64LE-NEXT: # %bb.2: 6942 ; PPC64LE-NEXT: mr 3, 5 6943 ; PPC64LE-NEXT: lwsync 6944 ; PPC64LE-NEXT: blr 6945 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acq_rel 6946 ret i16 %ret 6947 } 6948 6949 define i16 @test409(i16* %ptr, i16 %val) { 6950 ; PPC64LE-LABEL: test409: 6951 ; PPC64LE: # %bb.0: 6952 ; PPC64LE-NEXT: sync 6953 ; PPC64LE-NEXT: .LBB409_1: 6954 ; PPC64LE-NEXT: lharx 5, 0, 3 6955 ; PPC64LE-NEXT: and 6, 4, 5 6956 ; PPC64LE-NEXT: sthcx. 6, 0, 3 6957 ; PPC64LE-NEXT: bne 0, .LBB409_1 6958 ; PPC64LE-NEXT: # %bb.2: 6959 ; PPC64LE-NEXT: mr 3, 5 6960 ; PPC64LE-NEXT: lwsync 6961 ; PPC64LE-NEXT: blr 6962 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") seq_cst 6963 ret i16 %ret 6964 } 6965 6966 define i32 @test410(i32* %ptr, i32 %val) { 6967 ; PPC64LE-LABEL: test410: 6968 ; PPC64LE: # %bb.0: 6969 ; PPC64LE-NEXT: .LBB410_1: 6970 ; PPC64LE-NEXT: lwarx 5, 0, 3 6971 ; PPC64LE-NEXT: and 6, 4, 5 6972 ; PPC64LE-NEXT: stwcx. 6, 0, 3 6973 ; PPC64LE-NEXT: bne 0, .LBB410_1 6974 ; PPC64LE-NEXT: # %bb.2: 6975 ; PPC64LE-NEXT: mr 3, 5 6976 ; PPC64LE-NEXT: blr 6977 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") monotonic 6978 ret i32 %ret 6979 } 6980 6981 define i32 @test411(i32* %ptr, i32 %val) { 6982 ; PPC64LE-LABEL: test411: 6983 ; PPC64LE: # %bb.0: 6984 ; PPC64LE-NEXT: mr 5, 3 6985 ; PPC64LE-NEXT: .LBB411_1: 6986 ; PPC64LE-NEXT: lwarx 3, 0, 5 6987 ; PPC64LE-NEXT: and 6, 4, 3 6988 ; PPC64LE-NEXT: stwcx. 6, 0, 5 6989 ; PPC64LE-NEXT: bne 0, .LBB411_1 6990 ; PPC64LE-NEXT: # %bb.2: 6991 ; PPC64LE-NEXT: lwsync 6992 ; PPC64LE-NEXT: blr 6993 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acquire 6994 ret i32 %ret 6995 } 6996 6997 define i32 @test412(i32* %ptr, i32 %val) { 6998 ; PPC64LE-LABEL: test412: 6999 ; PPC64LE: # %bb.0: 7000 ; PPC64LE-NEXT: lwsync 7001 ; PPC64LE-NEXT: .LBB412_1: 7002 ; PPC64LE-NEXT: lwarx 5, 0, 3 7003 ; PPC64LE-NEXT: and 6, 4, 5 7004 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7005 ; PPC64LE-NEXT: bne 0, .LBB412_1 7006 ; PPC64LE-NEXT: # %bb.2: 7007 ; PPC64LE-NEXT: mr 3, 5 7008 ; PPC64LE-NEXT: blr 7009 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") release 7010 ret i32 %ret 7011 } 7012 7013 define i32 @test413(i32* %ptr, i32 %val) { 7014 ; PPC64LE-LABEL: test413: 7015 ; PPC64LE: # %bb.0: 7016 ; PPC64LE-NEXT: lwsync 7017 ; PPC64LE-NEXT: .LBB413_1: 7018 ; PPC64LE-NEXT: lwarx 5, 0, 3 7019 ; PPC64LE-NEXT: and 6, 4, 5 7020 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7021 ; PPC64LE-NEXT: bne 0, .LBB413_1 7022 ; PPC64LE-NEXT: # %bb.2: 7023 ; PPC64LE-NEXT: mr 3, 5 7024 ; PPC64LE-NEXT: lwsync 7025 ; PPC64LE-NEXT: blr 7026 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acq_rel 7027 ret i32 %ret 7028 } 7029 7030 define i32 @test414(i32* %ptr, i32 %val) { 7031 ; PPC64LE-LABEL: test414: 7032 ; PPC64LE: # %bb.0: 7033 ; PPC64LE-NEXT: sync 7034 ; PPC64LE-NEXT: .LBB414_1: 7035 ; PPC64LE-NEXT: lwarx 5, 0, 3 7036 ; PPC64LE-NEXT: and 6, 4, 5 7037 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7038 ; PPC64LE-NEXT: bne 0, .LBB414_1 7039 ; PPC64LE-NEXT: # %bb.2: 7040 ; PPC64LE-NEXT: mr 3, 5 7041 ; PPC64LE-NEXT: lwsync 7042 ; PPC64LE-NEXT: blr 7043 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") seq_cst 7044 ret i32 %ret 7045 } 7046 7047 define i64 @test415(i64* %ptr, i64 %val) { 7048 ; PPC64LE-LABEL: test415: 7049 ; PPC64LE: # %bb.0: 7050 ; PPC64LE-NEXT: .LBB415_1: 7051 ; PPC64LE-NEXT: ldarx 5, 0, 3 7052 ; PPC64LE-NEXT: and 6, 4, 5 7053 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7054 ; PPC64LE-NEXT: bne 0, .LBB415_1 7055 ; PPC64LE-NEXT: # %bb.2: 7056 ; PPC64LE-NEXT: mr 3, 5 7057 ; PPC64LE-NEXT: blr 7058 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") monotonic 7059 ret i64 %ret 7060 } 7061 7062 define i64 @test416(i64* %ptr, i64 %val) { 7063 ; PPC64LE-LABEL: test416: 7064 ; PPC64LE: # %bb.0: 7065 ; PPC64LE-NEXT: mr 5, 3 7066 ; PPC64LE-NEXT: .LBB416_1: 7067 ; PPC64LE-NEXT: ldarx 3, 0, 5 7068 ; PPC64LE-NEXT: and 6, 4, 3 7069 ; PPC64LE-NEXT: stdcx. 6, 0, 5 7070 ; PPC64LE-NEXT: bne 0, .LBB416_1 7071 ; PPC64LE-NEXT: # %bb.2: 7072 ; PPC64LE-NEXT: lwsync 7073 ; PPC64LE-NEXT: blr 7074 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acquire 7075 ret i64 %ret 7076 } 7077 7078 define i64 @test417(i64* %ptr, i64 %val) { 7079 ; PPC64LE-LABEL: test417: 7080 ; PPC64LE: # %bb.0: 7081 ; PPC64LE-NEXT: lwsync 7082 ; PPC64LE-NEXT: .LBB417_1: 7083 ; PPC64LE-NEXT: ldarx 5, 0, 3 7084 ; PPC64LE-NEXT: and 6, 4, 5 7085 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7086 ; PPC64LE-NEXT: bne 0, .LBB417_1 7087 ; PPC64LE-NEXT: # %bb.2: 7088 ; PPC64LE-NEXT: mr 3, 5 7089 ; PPC64LE-NEXT: blr 7090 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") release 7091 ret i64 %ret 7092 } 7093 7094 define i64 @test418(i64* %ptr, i64 %val) { 7095 ; PPC64LE-LABEL: test418: 7096 ; PPC64LE: # %bb.0: 7097 ; PPC64LE-NEXT: lwsync 7098 ; PPC64LE-NEXT: .LBB418_1: 7099 ; PPC64LE-NEXT: ldarx 5, 0, 3 7100 ; PPC64LE-NEXT: and 6, 4, 5 7101 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7102 ; PPC64LE-NEXT: bne 0, .LBB418_1 7103 ; PPC64LE-NEXT: # %bb.2: 7104 ; PPC64LE-NEXT: mr 3, 5 7105 ; PPC64LE-NEXT: lwsync 7106 ; PPC64LE-NEXT: blr 7107 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acq_rel 7108 ret i64 %ret 7109 } 7110 7111 define i64 @test419(i64* %ptr, i64 %val) { 7112 ; PPC64LE-LABEL: test419: 7113 ; PPC64LE: # %bb.0: 7114 ; PPC64LE-NEXT: sync 7115 ; PPC64LE-NEXT: .LBB419_1: 7116 ; PPC64LE-NEXT: ldarx 5, 0, 3 7117 ; PPC64LE-NEXT: and 6, 4, 5 7118 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7119 ; PPC64LE-NEXT: bne 0, .LBB419_1 7120 ; PPC64LE-NEXT: # %bb.2: 7121 ; PPC64LE-NEXT: mr 3, 5 7122 ; PPC64LE-NEXT: lwsync 7123 ; PPC64LE-NEXT: blr 7124 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") seq_cst 7125 ret i64 %ret 7126 } 7127 7128 define i8 @test420(i8* %ptr, i8 %val) { 7129 ; PPC64LE-LABEL: test420: 7130 ; PPC64LE: # %bb.0: 7131 ; PPC64LE-NEXT: .LBB420_1: 7132 ; PPC64LE-NEXT: lbarx 5, 0, 3 7133 ; PPC64LE-NEXT: nand 6, 4, 5 7134 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7135 ; PPC64LE-NEXT: bne 0, .LBB420_1 7136 ; PPC64LE-NEXT: # %bb.2: 7137 ; PPC64LE-NEXT: mr 3, 5 7138 ; PPC64LE-NEXT: blr 7139 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") monotonic 7140 ret i8 %ret 7141 } 7142 7143 define i8 @test421(i8* %ptr, i8 %val) { 7144 ; PPC64LE-LABEL: test421: 7145 ; PPC64LE: # %bb.0: 7146 ; PPC64LE-NEXT: mr 5, 3 7147 ; PPC64LE-NEXT: .LBB421_1: 7148 ; PPC64LE-NEXT: lbarx 3, 0, 5 7149 ; PPC64LE-NEXT: nand 6, 4, 3 7150 ; PPC64LE-NEXT: stbcx. 6, 0, 5 7151 ; PPC64LE-NEXT: bne 0, .LBB421_1 7152 ; PPC64LE-NEXT: # %bb.2: 7153 ; PPC64LE-NEXT: lwsync 7154 ; PPC64LE-NEXT: blr 7155 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acquire 7156 ret i8 %ret 7157 } 7158 7159 define i8 @test422(i8* %ptr, i8 %val) { 7160 ; PPC64LE-LABEL: test422: 7161 ; PPC64LE: # %bb.0: 7162 ; PPC64LE-NEXT: lwsync 7163 ; PPC64LE-NEXT: .LBB422_1: 7164 ; PPC64LE-NEXT: lbarx 5, 0, 3 7165 ; PPC64LE-NEXT: nand 6, 4, 5 7166 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7167 ; PPC64LE-NEXT: bne 0, .LBB422_1 7168 ; PPC64LE-NEXT: # %bb.2: 7169 ; PPC64LE-NEXT: mr 3, 5 7170 ; PPC64LE-NEXT: blr 7171 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") release 7172 ret i8 %ret 7173 } 7174 7175 define i8 @test423(i8* %ptr, i8 %val) { 7176 ; PPC64LE-LABEL: test423: 7177 ; PPC64LE: # %bb.0: 7178 ; PPC64LE-NEXT: lwsync 7179 ; PPC64LE-NEXT: .LBB423_1: 7180 ; PPC64LE-NEXT: lbarx 5, 0, 3 7181 ; PPC64LE-NEXT: nand 6, 4, 5 7182 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7183 ; PPC64LE-NEXT: bne 0, .LBB423_1 7184 ; PPC64LE-NEXT: # %bb.2: 7185 ; PPC64LE-NEXT: mr 3, 5 7186 ; PPC64LE-NEXT: lwsync 7187 ; PPC64LE-NEXT: blr 7188 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acq_rel 7189 ret i8 %ret 7190 } 7191 7192 define i8 @test424(i8* %ptr, i8 %val) { 7193 ; PPC64LE-LABEL: test424: 7194 ; PPC64LE: # %bb.0: 7195 ; PPC64LE-NEXT: sync 7196 ; PPC64LE-NEXT: .LBB424_1: 7197 ; PPC64LE-NEXT: lbarx 5, 0, 3 7198 ; PPC64LE-NEXT: nand 6, 4, 5 7199 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7200 ; PPC64LE-NEXT: bne 0, .LBB424_1 7201 ; PPC64LE-NEXT: # %bb.2: 7202 ; PPC64LE-NEXT: mr 3, 5 7203 ; PPC64LE-NEXT: lwsync 7204 ; PPC64LE-NEXT: blr 7205 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") seq_cst 7206 ret i8 %ret 7207 } 7208 7209 define i16 @test425(i16* %ptr, i16 %val) { 7210 ; PPC64LE-LABEL: test425: 7211 ; PPC64LE: # %bb.0: 7212 ; PPC64LE-NEXT: .LBB425_1: 7213 ; PPC64LE-NEXT: lharx 5, 0, 3 7214 ; PPC64LE-NEXT: nand 6, 4, 5 7215 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7216 ; PPC64LE-NEXT: bne 0, .LBB425_1 7217 ; PPC64LE-NEXT: # %bb.2: 7218 ; PPC64LE-NEXT: mr 3, 5 7219 ; PPC64LE-NEXT: blr 7220 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") monotonic 7221 ret i16 %ret 7222 } 7223 7224 define i16 @test426(i16* %ptr, i16 %val) { 7225 ; PPC64LE-LABEL: test426: 7226 ; PPC64LE: # %bb.0: 7227 ; PPC64LE-NEXT: mr 5, 3 7228 ; PPC64LE-NEXT: .LBB426_1: 7229 ; PPC64LE-NEXT: lharx 3, 0, 5 7230 ; PPC64LE-NEXT: nand 6, 4, 3 7231 ; PPC64LE-NEXT: sthcx. 6, 0, 5 7232 ; PPC64LE-NEXT: bne 0, .LBB426_1 7233 ; PPC64LE-NEXT: # %bb.2: 7234 ; PPC64LE-NEXT: lwsync 7235 ; PPC64LE-NEXT: blr 7236 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acquire 7237 ret i16 %ret 7238 } 7239 7240 define i16 @test427(i16* %ptr, i16 %val) { 7241 ; PPC64LE-LABEL: test427: 7242 ; PPC64LE: # %bb.0: 7243 ; PPC64LE-NEXT: lwsync 7244 ; PPC64LE-NEXT: .LBB427_1: 7245 ; PPC64LE-NEXT: lharx 5, 0, 3 7246 ; PPC64LE-NEXT: nand 6, 4, 5 7247 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7248 ; PPC64LE-NEXT: bne 0, .LBB427_1 7249 ; PPC64LE-NEXT: # %bb.2: 7250 ; PPC64LE-NEXT: mr 3, 5 7251 ; PPC64LE-NEXT: blr 7252 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") release 7253 ret i16 %ret 7254 } 7255 7256 define i16 @test428(i16* %ptr, i16 %val) { 7257 ; PPC64LE-LABEL: test428: 7258 ; PPC64LE: # %bb.0: 7259 ; PPC64LE-NEXT: lwsync 7260 ; PPC64LE-NEXT: .LBB428_1: 7261 ; PPC64LE-NEXT: lharx 5, 0, 3 7262 ; PPC64LE-NEXT: nand 6, 4, 5 7263 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7264 ; PPC64LE-NEXT: bne 0, .LBB428_1 7265 ; PPC64LE-NEXT: # %bb.2: 7266 ; PPC64LE-NEXT: mr 3, 5 7267 ; PPC64LE-NEXT: lwsync 7268 ; PPC64LE-NEXT: blr 7269 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acq_rel 7270 ret i16 %ret 7271 } 7272 7273 define i16 @test429(i16* %ptr, i16 %val) { 7274 ; PPC64LE-LABEL: test429: 7275 ; PPC64LE: # %bb.0: 7276 ; PPC64LE-NEXT: sync 7277 ; PPC64LE-NEXT: .LBB429_1: 7278 ; PPC64LE-NEXT: lharx 5, 0, 3 7279 ; PPC64LE-NEXT: nand 6, 4, 5 7280 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7281 ; PPC64LE-NEXT: bne 0, .LBB429_1 7282 ; PPC64LE-NEXT: # %bb.2: 7283 ; PPC64LE-NEXT: mr 3, 5 7284 ; PPC64LE-NEXT: lwsync 7285 ; PPC64LE-NEXT: blr 7286 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") seq_cst 7287 ret i16 %ret 7288 } 7289 7290 define i32 @test430(i32* %ptr, i32 %val) { 7291 ; PPC64LE-LABEL: test430: 7292 ; PPC64LE: # %bb.0: 7293 ; PPC64LE-NEXT: .LBB430_1: 7294 ; PPC64LE-NEXT: lwarx 5, 0, 3 7295 ; PPC64LE-NEXT: nand 6, 4, 5 7296 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7297 ; PPC64LE-NEXT: bne 0, .LBB430_1 7298 ; PPC64LE-NEXT: # %bb.2: 7299 ; PPC64LE-NEXT: mr 3, 5 7300 ; PPC64LE-NEXT: blr 7301 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") monotonic 7302 ret i32 %ret 7303 } 7304 7305 define i32 @test431(i32* %ptr, i32 %val) { 7306 ; PPC64LE-LABEL: test431: 7307 ; PPC64LE: # %bb.0: 7308 ; PPC64LE-NEXT: mr 5, 3 7309 ; PPC64LE-NEXT: .LBB431_1: 7310 ; PPC64LE-NEXT: lwarx 3, 0, 5 7311 ; PPC64LE-NEXT: nand 6, 4, 3 7312 ; PPC64LE-NEXT: stwcx. 6, 0, 5 7313 ; PPC64LE-NEXT: bne 0, .LBB431_1 7314 ; PPC64LE-NEXT: # %bb.2: 7315 ; PPC64LE-NEXT: lwsync 7316 ; PPC64LE-NEXT: blr 7317 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acquire 7318 ret i32 %ret 7319 } 7320 7321 define i32 @test432(i32* %ptr, i32 %val) { 7322 ; PPC64LE-LABEL: test432: 7323 ; PPC64LE: # %bb.0: 7324 ; PPC64LE-NEXT: lwsync 7325 ; PPC64LE-NEXT: .LBB432_1: 7326 ; PPC64LE-NEXT: lwarx 5, 0, 3 7327 ; PPC64LE-NEXT: nand 6, 4, 5 7328 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7329 ; PPC64LE-NEXT: bne 0, .LBB432_1 7330 ; PPC64LE-NEXT: # %bb.2: 7331 ; PPC64LE-NEXT: mr 3, 5 7332 ; PPC64LE-NEXT: blr 7333 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") release 7334 ret i32 %ret 7335 } 7336 7337 define i32 @test433(i32* %ptr, i32 %val) { 7338 ; PPC64LE-LABEL: test433: 7339 ; PPC64LE: # %bb.0: 7340 ; PPC64LE-NEXT: lwsync 7341 ; PPC64LE-NEXT: .LBB433_1: 7342 ; PPC64LE-NEXT: lwarx 5, 0, 3 7343 ; PPC64LE-NEXT: nand 6, 4, 5 7344 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7345 ; PPC64LE-NEXT: bne 0, .LBB433_1 7346 ; PPC64LE-NEXT: # %bb.2: 7347 ; PPC64LE-NEXT: mr 3, 5 7348 ; PPC64LE-NEXT: lwsync 7349 ; PPC64LE-NEXT: blr 7350 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acq_rel 7351 ret i32 %ret 7352 } 7353 7354 define i32 @test434(i32* %ptr, i32 %val) { 7355 ; PPC64LE-LABEL: test434: 7356 ; PPC64LE: # %bb.0: 7357 ; PPC64LE-NEXT: sync 7358 ; PPC64LE-NEXT: .LBB434_1: 7359 ; PPC64LE-NEXT: lwarx 5, 0, 3 7360 ; PPC64LE-NEXT: nand 6, 4, 5 7361 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7362 ; PPC64LE-NEXT: bne 0, .LBB434_1 7363 ; PPC64LE-NEXT: # %bb.2: 7364 ; PPC64LE-NEXT: mr 3, 5 7365 ; PPC64LE-NEXT: lwsync 7366 ; PPC64LE-NEXT: blr 7367 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") seq_cst 7368 ret i32 %ret 7369 } 7370 7371 define i64 @test435(i64* %ptr, i64 %val) { 7372 ; PPC64LE-LABEL: test435: 7373 ; PPC64LE: # %bb.0: 7374 ; PPC64LE-NEXT: .LBB435_1: 7375 ; PPC64LE-NEXT: ldarx 5, 0, 3 7376 ; PPC64LE-NEXT: nand 6, 4, 5 7377 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7378 ; PPC64LE-NEXT: bne 0, .LBB435_1 7379 ; PPC64LE-NEXT: # %bb.2: 7380 ; PPC64LE-NEXT: mr 3, 5 7381 ; PPC64LE-NEXT: blr 7382 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") monotonic 7383 ret i64 %ret 7384 } 7385 7386 define i64 @test436(i64* %ptr, i64 %val) { 7387 ; PPC64LE-LABEL: test436: 7388 ; PPC64LE: # %bb.0: 7389 ; PPC64LE-NEXT: mr 5, 3 7390 ; PPC64LE-NEXT: .LBB436_1: 7391 ; PPC64LE-NEXT: ldarx 3, 0, 5 7392 ; PPC64LE-NEXT: nand 6, 4, 3 7393 ; PPC64LE-NEXT: stdcx. 6, 0, 5 7394 ; PPC64LE-NEXT: bne 0, .LBB436_1 7395 ; PPC64LE-NEXT: # %bb.2: 7396 ; PPC64LE-NEXT: lwsync 7397 ; PPC64LE-NEXT: blr 7398 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acquire 7399 ret i64 %ret 7400 } 7401 7402 define i64 @test437(i64* %ptr, i64 %val) { 7403 ; PPC64LE-LABEL: test437: 7404 ; PPC64LE: # %bb.0: 7405 ; PPC64LE-NEXT: lwsync 7406 ; PPC64LE-NEXT: .LBB437_1: 7407 ; PPC64LE-NEXT: ldarx 5, 0, 3 7408 ; PPC64LE-NEXT: nand 6, 4, 5 7409 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7410 ; PPC64LE-NEXT: bne 0, .LBB437_1 7411 ; PPC64LE-NEXT: # %bb.2: 7412 ; PPC64LE-NEXT: mr 3, 5 7413 ; PPC64LE-NEXT: blr 7414 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") release 7415 ret i64 %ret 7416 } 7417 7418 define i64 @test438(i64* %ptr, i64 %val) { 7419 ; PPC64LE-LABEL: test438: 7420 ; PPC64LE: # %bb.0: 7421 ; PPC64LE-NEXT: lwsync 7422 ; PPC64LE-NEXT: .LBB438_1: 7423 ; PPC64LE-NEXT: ldarx 5, 0, 3 7424 ; PPC64LE-NEXT: nand 6, 4, 5 7425 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7426 ; PPC64LE-NEXT: bne 0, .LBB438_1 7427 ; PPC64LE-NEXT: # %bb.2: 7428 ; PPC64LE-NEXT: mr 3, 5 7429 ; PPC64LE-NEXT: lwsync 7430 ; PPC64LE-NEXT: blr 7431 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acq_rel 7432 ret i64 %ret 7433 } 7434 7435 define i64 @test439(i64* %ptr, i64 %val) { 7436 ; PPC64LE-LABEL: test439: 7437 ; PPC64LE: # %bb.0: 7438 ; PPC64LE-NEXT: sync 7439 ; PPC64LE-NEXT: .LBB439_1: 7440 ; PPC64LE-NEXT: ldarx 5, 0, 3 7441 ; PPC64LE-NEXT: nand 6, 4, 5 7442 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7443 ; PPC64LE-NEXT: bne 0, .LBB439_1 7444 ; PPC64LE-NEXT: # %bb.2: 7445 ; PPC64LE-NEXT: mr 3, 5 7446 ; PPC64LE-NEXT: lwsync 7447 ; PPC64LE-NEXT: blr 7448 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") seq_cst 7449 ret i64 %ret 7450 } 7451 7452 define i8 @test440(i8* %ptr, i8 %val) { 7453 ; PPC64LE-LABEL: test440: 7454 ; PPC64LE: # %bb.0: 7455 ; PPC64LE-NEXT: .LBB440_1: 7456 ; PPC64LE-NEXT: lbarx 5, 0, 3 7457 ; PPC64LE-NEXT: or 6, 4, 5 7458 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7459 ; PPC64LE-NEXT: bne 0, .LBB440_1 7460 ; PPC64LE-NEXT: # %bb.2: 7461 ; PPC64LE-NEXT: mr 3, 5 7462 ; PPC64LE-NEXT: blr 7463 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") monotonic 7464 ret i8 %ret 7465 } 7466 7467 define i8 @test441(i8* %ptr, i8 %val) { 7468 ; PPC64LE-LABEL: test441: 7469 ; PPC64LE: # %bb.0: 7470 ; PPC64LE-NEXT: mr 5, 3 7471 ; PPC64LE-NEXT: .LBB441_1: 7472 ; PPC64LE-NEXT: lbarx 3, 0, 5 7473 ; PPC64LE-NEXT: or 6, 4, 3 7474 ; PPC64LE-NEXT: stbcx. 6, 0, 5 7475 ; PPC64LE-NEXT: bne 0, .LBB441_1 7476 ; PPC64LE-NEXT: # %bb.2: 7477 ; PPC64LE-NEXT: lwsync 7478 ; PPC64LE-NEXT: blr 7479 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acquire 7480 ret i8 %ret 7481 } 7482 7483 define i8 @test442(i8* %ptr, i8 %val) { 7484 ; PPC64LE-LABEL: test442: 7485 ; PPC64LE: # %bb.0: 7486 ; PPC64LE-NEXT: lwsync 7487 ; PPC64LE-NEXT: .LBB442_1: 7488 ; PPC64LE-NEXT: lbarx 5, 0, 3 7489 ; PPC64LE-NEXT: or 6, 4, 5 7490 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7491 ; PPC64LE-NEXT: bne 0, .LBB442_1 7492 ; PPC64LE-NEXT: # %bb.2: 7493 ; PPC64LE-NEXT: mr 3, 5 7494 ; PPC64LE-NEXT: blr 7495 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") release 7496 ret i8 %ret 7497 } 7498 7499 define i8 @test443(i8* %ptr, i8 %val) { 7500 ; PPC64LE-LABEL: test443: 7501 ; PPC64LE: # %bb.0: 7502 ; PPC64LE-NEXT: lwsync 7503 ; PPC64LE-NEXT: .LBB443_1: 7504 ; PPC64LE-NEXT: lbarx 5, 0, 3 7505 ; PPC64LE-NEXT: or 6, 4, 5 7506 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7507 ; PPC64LE-NEXT: bne 0, .LBB443_1 7508 ; PPC64LE-NEXT: # %bb.2: 7509 ; PPC64LE-NEXT: mr 3, 5 7510 ; PPC64LE-NEXT: lwsync 7511 ; PPC64LE-NEXT: blr 7512 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acq_rel 7513 ret i8 %ret 7514 } 7515 7516 define i8 @test444(i8* %ptr, i8 %val) { 7517 ; PPC64LE-LABEL: test444: 7518 ; PPC64LE: # %bb.0: 7519 ; PPC64LE-NEXT: sync 7520 ; PPC64LE-NEXT: .LBB444_1: 7521 ; PPC64LE-NEXT: lbarx 5, 0, 3 7522 ; PPC64LE-NEXT: or 6, 4, 5 7523 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7524 ; PPC64LE-NEXT: bne 0, .LBB444_1 7525 ; PPC64LE-NEXT: # %bb.2: 7526 ; PPC64LE-NEXT: mr 3, 5 7527 ; PPC64LE-NEXT: lwsync 7528 ; PPC64LE-NEXT: blr 7529 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") seq_cst 7530 ret i8 %ret 7531 } 7532 7533 define i16 @test445(i16* %ptr, i16 %val) { 7534 ; PPC64LE-LABEL: test445: 7535 ; PPC64LE: # %bb.0: 7536 ; PPC64LE-NEXT: .LBB445_1: 7537 ; PPC64LE-NEXT: lharx 5, 0, 3 7538 ; PPC64LE-NEXT: or 6, 4, 5 7539 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7540 ; PPC64LE-NEXT: bne 0, .LBB445_1 7541 ; PPC64LE-NEXT: # %bb.2: 7542 ; PPC64LE-NEXT: mr 3, 5 7543 ; PPC64LE-NEXT: blr 7544 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") monotonic 7545 ret i16 %ret 7546 } 7547 7548 define i16 @test446(i16* %ptr, i16 %val) { 7549 ; PPC64LE-LABEL: test446: 7550 ; PPC64LE: # %bb.0: 7551 ; PPC64LE-NEXT: mr 5, 3 7552 ; PPC64LE-NEXT: .LBB446_1: 7553 ; PPC64LE-NEXT: lharx 3, 0, 5 7554 ; PPC64LE-NEXT: or 6, 4, 3 7555 ; PPC64LE-NEXT: sthcx. 6, 0, 5 7556 ; PPC64LE-NEXT: bne 0, .LBB446_1 7557 ; PPC64LE-NEXT: # %bb.2: 7558 ; PPC64LE-NEXT: lwsync 7559 ; PPC64LE-NEXT: blr 7560 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acquire 7561 ret i16 %ret 7562 } 7563 7564 define i16 @test447(i16* %ptr, i16 %val) { 7565 ; PPC64LE-LABEL: test447: 7566 ; PPC64LE: # %bb.0: 7567 ; PPC64LE-NEXT: lwsync 7568 ; PPC64LE-NEXT: .LBB447_1: 7569 ; PPC64LE-NEXT: lharx 5, 0, 3 7570 ; PPC64LE-NEXT: or 6, 4, 5 7571 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7572 ; PPC64LE-NEXT: bne 0, .LBB447_1 7573 ; PPC64LE-NEXT: # %bb.2: 7574 ; PPC64LE-NEXT: mr 3, 5 7575 ; PPC64LE-NEXT: blr 7576 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") release 7577 ret i16 %ret 7578 } 7579 7580 define i16 @test448(i16* %ptr, i16 %val) { 7581 ; PPC64LE-LABEL: test448: 7582 ; PPC64LE: # %bb.0: 7583 ; PPC64LE-NEXT: lwsync 7584 ; PPC64LE-NEXT: .LBB448_1: 7585 ; PPC64LE-NEXT: lharx 5, 0, 3 7586 ; PPC64LE-NEXT: or 6, 4, 5 7587 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7588 ; PPC64LE-NEXT: bne 0, .LBB448_1 7589 ; PPC64LE-NEXT: # %bb.2: 7590 ; PPC64LE-NEXT: mr 3, 5 7591 ; PPC64LE-NEXT: lwsync 7592 ; PPC64LE-NEXT: blr 7593 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acq_rel 7594 ret i16 %ret 7595 } 7596 7597 define i16 @test449(i16* %ptr, i16 %val) { 7598 ; PPC64LE-LABEL: test449: 7599 ; PPC64LE: # %bb.0: 7600 ; PPC64LE-NEXT: sync 7601 ; PPC64LE-NEXT: .LBB449_1: 7602 ; PPC64LE-NEXT: lharx 5, 0, 3 7603 ; PPC64LE-NEXT: or 6, 4, 5 7604 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7605 ; PPC64LE-NEXT: bne 0, .LBB449_1 7606 ; PPC64LE-NEXT: # %bb.2: 7607 ; PPC64LE-NEXT: mr 3, 5 7608 ; PPC64LE-NEXT: lwsync 7609 ; PPC64LE-NEXT: blr 7610 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") seq_cst 7611 ret i16 %ret 7612 } 7613 7614 define i32 @test450(i32* %ptr, i32 %val) { 7615 ; PPC64LE-LABEL: test450: 7616 ; PPC64LE: # %bb.0: 7617 ; PPC64LE-NEXT: .LBB450_1: 7618 ; PPC64LE-NEXT: lwarx 5, 0, 3 7619 ; PPC64LE-NEXT: or 6, 4, 5 7620 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7621 ; PPC64LE-NEXT: bne 0, .LBB450_1 7622 ; PPC64LE-NEXT: # %bb.2: 7623 ; PPC64LE-NEXT: mr 3, 5 7624 ; PPC64LE-NEXT: blr 7625 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") monotonic 7626 ret i32 %ret 7627 } 7628 7629 define i32 @test451(i32* %ptr, i32 %val) { 7630 ; PPC64LE-LABEL: test451: 7631 ; PPC64LE: # %bb.0: 7632 ; PPC64LE-NEXT: mr 5, 3 7633 ; PPC64LE-NEXT: .LBB451_1: 7634 ; PPC64LE-NEXT: lwarx 3, 0, 5 7635 ; PPC64LE-NEXT: or 6, 4, 3 7636 ; PPC64LE-NEXT: stwcx. 6, 0, 5 7637 ; PPC64LE-NEXT: bne 0, .LBB451_1 7638 ; PPC64LE-NEXT: # %bb.2: 7639 ; PPC64LE-NEXT: lwsync 7640 ; PPC64LE-NEXT: blr 7641 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acquire 7642 ret i32 %ret 7643 } 7644 7645 define i32 @test452(i32* %ptr, i32 %val) { 7646 ; PPC64LE-LABEL: test452: 7647 ; PPC64LE: # %bb.0: 7648 ; PPC64LE-NEXT: lwsync 7649 ; PPC64LE-NEXT: .LBB452_1: 7650 ; PPC64LE-NEXT: lwarx 5, 0, 3 7651 ; PPC64LE-NEXT: or 6, 4, 5 7652 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7653 ; PPC64LE-NEXT: bne 0, .LBB452_1 7654 ; PPC64LE-NEXT: # %bb.2: 7655 ; PPC64LE-NEXT: mr 3, 5 7656 ; PPC64LE-NEXT: blr 7657 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") release 7658 ret i32 %ret 7659 } 7660 7661 define i32 @test453(i32* %ptr, i32 %val) { 7662 ; PPC64LE-LABEL: test453: 7663 ; PPC64LE: # %bb.0: 7664 ; PPC64LE-NEXT: lwsync 7665 ; PPC64LE-NEXT: .LBB453_1: 7666 ; PPC64LE-NEXT: lwarx 5, 0, 3 7667 ; PPC64LE-NEXT: or 6, 4, 5 7668 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7669 ; PPC64LE-NEXT: bne 0, .LBB453_1 7670 ; PPC64LE-NEXT: # %bb.2: 7671 ; PPC64LE-NEXT: mr 3, 5 7672 ; PPC64LE-NEXT: lwsync 7673 ; PPC64LE-NEXT: blr 7674 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acq_rel 7675 ret i32 %ret 7676 } 7677 7678 define i32 @test454(i32* %ptr, i32 %val) { 7679 ; PPC64LE-LABEL: test454: 7680 ; PPC64LE: # %bb.0: 7681 ; PPC64LE-NEXT: sync 7682 ; PPC64LE-NEXT: .LBB454_1: 7683 ; PPC64LE-NEXT: lwarx 5, 0, 3 7684 ; PPC64LE-NEXT: or 6, 4, 5 7685 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7686 ; PPC64LE-NEXT: bne 0, .LBB454_1 7687 ; PPC64LE-NEXT: # %bb.2: 7688 ; PPC64LE-NEXT: mr 3, 5 7689 ; PPC64LE-NEXT: lwsync 7690 ; PPC64LE-NEXT: blr 7691 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") seq_cst 7692 ret i32 %ret 7693 } 7694 7695 define i64 @test455(i64* %ptr, i64 %val) { 7696 ; PPC64LE-LABEL: test455: 7697 ; PPC64LE: # %bb.0: 7698 ; PPC64LE-NEXT: .LBB455_1: 7699 ; PPC64LE-NEXT: ldarx 5, 0, 3 7700 ; PPC64LE-NEXT: or 6, 4, 5 7701 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7702 ; PPC64LE-NEXT: bne 0, .LBB455_1 7703 ; PPC64LE-NEXT: # %bb.2: 7704 ; PPC64LE-NEXT: mr 3, 5 7705 ; PPC64LE-NEXT: blr 7706 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") monotonic 7707 ret i64 %ret 7708 } 7709 7710 define i64 @test456(i64* %ptr, i64 %val) { 7711 ; PPC64LE-LABEL: test456: 7712 ; PPC64LE: # %bb.0: 7713 ; PPC64LE-NEXT: mr 5, 3 7714 ; PPC64LE-NEXT: .LBB456_1: 7715 ; PPC64LE-NEXT: ldarx 3, 0, 5 7716 ; PPC64LE-NEXT: or 6, 4, 3 7717 ; PPC64LE-NEXT: stdcx. 6, 0, 5 7718 ; PPC64LE-NEXT: bne 0, .LBB456_1 7719 ; PPC64LE-NEXT: # %bb.2: 7720 ; PPC64LE-NEXT: lwsync 7721 ; PPC64LE-NEXT: blr 7722 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acquire 7723 ret i64 %ret 7724 } 7725 7726 define i64 @test457(i64* %ptr, i64 %val) { 7727 ; PPC64LE-LABEL: test457: 7728 ; PPC64LE: # %bb.0: 7729 ; PPC64LE-NEXT: lwsync 7730 ; PPC64LE-NEXT: .LBB457_1: 7731 ; PPC64LE-NEXT: ldarx 5, 0, 3 7732 ; PPC64LE-NEXT: or 6, 4, 5 7733 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7734 ; PPC64LE-NEXT: bne 0, .LBB457_1 7735 ; PPC64LE-NEXT: # %bb.2: 7736 ; PPC64LE-NEXT: mr 3, 5 7737 ; PPC64LE-NEXT: blr 7738 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") release 7739 ret i64 %ret 7740 } 7741 7742 define i64 @test458(i64* %ptr, i64 %val) { 7743 ; PPC64LE-LABEL: test458: 7744 ; PPC64LE: # %bb.0: 7745 ; PPC64LE-NEXT: lwsync 7746 ; PPC64LE-NEXT: .LBB458_1: 7747 ; PPC64LE-NEXT: ldarx 5, 0, 3 7748 ; PPC64LE-NEXT: or 6, 4, 5 7749 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7750 ; PPC64LE-NEXT: bne 0, .LBB458_1 7751 ; PPC64LE-NEXT: # %bb.2: 7752 ; PPC64LE-NEXT: mr 3, 5 7753 ; PPC64LE-NEXT: lwsync 7754 ; PPC64LE-NEXT: blr 7755 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acq_rel 7756 ret i64 %ret 7757 } 7758 7759 define i64 @test459(i64* %ptr, i64 %val) { 7760 ; PPC64LE-LABEL: test459: 7761 ; PPC64LE: # %bb.0: 7762 ; PPC64LE-NEXT: sync 7763 ; PPC64LE-NEXT: .LBB459_1: 7764 ; PPC64LE-NEXT: ldarx 5, 0, 3 7765 ; PPC64LE-NEXT: or 6, 4, 5 7766 ; PPC64LE-NEXT: stdcx. 6, 0, 3 7767 ; PPC64LE-NEXT: bne 0, .LBB459_1 7768 ; PPC64LE-NEXT: # %bb.2: 7769 ; PPC64LE-NEXT: mr 3, 5 7770 ; PPC64LE-NEXT: lwsync 7771 ; PPC64LE-NEXT: blr 7772 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") seq_cst 7773 ret i64 %ret 7774 } 7775 7776 define i8 @test460(i8* %ptr, i8 %val) { 7777 ; PPC64LE-LABEL: test460: 7778 ; PPC64LE: # %bb.0: 7779 ; PPC64LE-NEXT: .LBB460_1: 7780 ; PPC64LE-NEXT: lbarx 5, 0, 3 7781 ; PPC64LE-NEXT: xor 6, 4, 5 7782 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7783 ; PPC64LE-NEXT: bne 0, .LBB460_1 7784 ; PPC64LE-NEXT: # %bb.2: 7785 ; PPC64LE-NEXT: mr 3, 5 7786 ; PPC64LE-NEXT: blr 7787 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") monotonic 7788 ret i8 %ret 7789 } 7790 7791 define i8 @test461(i8* %ptr, i8 %val) { 7792 ; PPC64LE-LABEL: test461: 7793 ; PPC64LE: # %bb.0: 7794 ; PPC64LE-NEXT: mr 5, 3 7795 ; PPC64LE-NEXT: .LBB461_1: 7796 ; PPC64LE-NEXT: lbarx 3, 0, 5 7797 ; PPC64LE-NEXT: xor 6, 4, 3 7798 ; PPC64LE-NEXT: stbcx. 6, 0, 5 7799 ; PPC64LE-NEXT: bne 0, .LBB461_1 7800 ; PPC64LE-NEXT: # %bb.2: 7801 ; PPC64LE-NEXT: lwsync 7802 ; PPC64LE-NEXT: blr 7803 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acquire 7804 ret i8 %ret 7805 } 7806 7807 define i8 @test462(i8* %ptr, i8 %val) { 7808 ; PPC64LE-LABEL: test462: 7809 ; PPC64LE: # %bb.0: 7810 ; PPC64LE-NEXT: lwsync 7811 ; PPC64LE-NEXT: .LBB462_1: 7812 ; PPC64LE-NEXT: lbarx 5, 0, 3 7813 ; PPC64LE-NEXT: xor 6, 4, 5 7814 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7815 ; PPC64LE-NEXT: bne 0, .LBB462_1 7816 ; PPC64LE-NEXT: # %bb.2: 7817 ; PPC64LE-NEXT: mr 3, 5 7818 ; PPC64LE-NEXT: blr 7819 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") release 7820 ret i8 %ret 7821 } 7822 7823 define i8 @test463(i8* %ptr, i8 %val) { 7824 ; PPC64LE-LABEL: test463: 7825 ; PPC64LE: # %bb.0: 7826 ; PPC64LE-NEXT: lwsync 7827 ; PPC64LE-NEXT: .LBB463_1: 7828 ; PPC64LE-NEXT: lbarx 5, 0, 3 7829 ; PPC64LE-NEXT: xor 6, 4, 5 7830 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7831 ; PPC64LE-NEXT: bne 0, .LBB463_1 7832 ; PPC64LE-NEXT: # %bb.2: 7833 ; PPC64LE-NEXT: mr 3, 5 7834 ; PPC64LE-NEXT: lwsync 7835 ; PPC64LE-NEXT: blr 7836 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acq_rel 7837 ret i8 %ret 7838 } 7839 7840 define i8 @test464(i8* %ptr, i8 %val) { 7841 ; PPC64LE-LABEL: test464: 7842 ; PPC64LE: # %bb.0: 7843 ; PPC64LE-NEXT: sync 7844 ; PPC64LE-NEXT: .LBB464_1: 7845 ; PPC64LE-NEXT: lbarx 5, 0, 3 7846 ; PPC64LE-NEXT: xor 6, 4, 5 7847 ; PPC64LE-NEXT: stbcx. 6, 0, 3 7848 ; PPC64LE-NEXT: bne 0, .LBB464_1 7849 ; PPC64LE-NEXT: # %bb.2: 7850 ; PPC64LE-NEXT: mr 3, 5 7851 ; PPC64LE-NEXT: lwsync 7852 ; PPC64LE-NEXT: blr 7853 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") seq_cst 7854 ret i8 %ret 7855 } 7856 7857 define i16 @test465(i16* %ptr, i16 %val) { 7858 ; PPC64LE-LABEL: test465: 7859 ; PPC64LE: # %bb.0: 7860 ; PPC64LE-NEXT: .LBB465_1: 7861 ; PPC64LE-NEXT: lharx 5, 0, 3 7862 ; PPC64LE-NEXT: xor 6, 4, 5 7863 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7864 ; PPC64LE-NEXT: bne 0, .LBB465_1 7865 ; PPC64LE-NEXT: # %bb.2: 7866 ; PPC64LE-NEXT: mr 3, 5 7867 ; PPC64LE-NEXT: blr 7868 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") monotonic 7869 ret i16 %ret 7870 } 7871 7872 define i16 @test466(i16* %ptr, i16 %val) { 7873 ; PPC64LE-LABEL: test466: 7874 ; PPC64LE: # %bb.0: 7875 ; PPC64LE-NEXT: mr 5, 3 7876 ; PPC64LE-NEXT: .LBB466_1: 7877 ; PPC64LE-NEXT: lharx 3, 0, 5 7878 ; PPC64LE-NEXT: xor 6, 4, 3 7879 ; PPC64LE-NEXT: sthcx. 6, 0, 5 7880 ; PPC64LE-NEXT: bne 0, .LBB466_1 7881 ; PPC64LE-NEXT: # %bb.2: 7882 ; PPC64LE-NEXT: lwsync 7883 ; PPC64LE-NEXT: blr 7884 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acquire 7885 ret i16 %ret 7886 } 7887 7888 define i16 @test467(i16* %ptr, i16 %val) { 7889 ; PPC64LE-LABEL: test467: 7890 ; PPC64LE: # %bb.0: 7891 ; PPC64LE-NEXT: lwsync 7892 ; PPC64LE-NEXT: .LBB467_1: 7893 ; PPC64LE-NEXT: lharx 5, 0, 3 7894 ; PPC64LE-NEXT: xor 6, 4, 5 7895 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7896 ; PPC64LE-NEXT: bne 0, .LBB467_1 7897 ; PPC64LE-NEXT: # %bb.2: 7898 ; PPC64LE-NEXT: mr 3, 5 7899 ; PPC64LE-NEXT: blr 7900 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") release 7901 ret i16 %ret 7902 } 7903 7904 define i16 @test468(i16* %ptr, i16 %val) { 7905 ; PPC64LE-LABEL: test468: 7906 ; PPC64LE: # %bb.0: 7907 ; PPC64LE-NEXT: lwsync 7908 ; PPC64LE-NEXT: .LBB468_1: 7909 ; PPC64LE-NEXT: lharx 5, 0, 3 7910 ; PPC64LE-NEXT: xor 6, 4, 5 7911 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7912 ; PPC64LE-NEXT: bne 0, .LBB468_1 7913 ; PPC64LE-NEXT: # %bb.2: 7914 ; PPC64LE-NEXT: mr 3, 5 7915 ; PPC64LE-NEXT: lwsync 7916 ; PPC64LE-NEXT: blr 7917 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acq_rel 7918 ret i16 %ret 7919 } 7920 7921 define i16 @test469(i16* %ptr, i16 %val) { 7922 ; PPC64LE-LABEL: test469: 7923 ; PPC64LE: # %bb.0: 7924 ; PPC64LE-NEXT: sync 7925 ; PPC64LE-NEXT: .LBB469_1: 7926 ; PPC64LE-NEXT: lharx 5, 0, 3 7927 ; PPC64LE-NEXT: xor 6, 4, 5 7928 ; PPC64LE-NEXT: sthcx. 6, 0, 3 7929 ; PPC64LE-NEXT: bne 0, .LBB469_1 7930 ; PPC64LE-NEXT: # %bb.2: 7931 ; PPC64LE-NEXT: mr 3, 5 7932 ; PPC64LE-NEXT: lwsync 7933 ; PPC64LE-NEXT: blr 7934 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") seq_cst 7935 ret i16 %ret 7936 } 7937 7938 define i32 @test470(i32* %ptr, i32 %val) { 7939 ; PPC64LE-LABEL: test470: 7940 ; PPC64LE: # %bb.0: 7941 ; PPC64LE-NEXT: .LBB470_1: 7942 ; PPC64LE-NEXT: lwarx 5, 0, 3 7943 ; PPC64LE-NEXT: xor 6, 4, 5 7944 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7945 ; PPC64LE-NEXT: bne 0, .LBB470_1 7946 ; PPC64LE-NEXT: # %bb.2: 7947 ; PPC64LE-NEXT: mr 3, 5 7948 ; PPC64LE-NEXT: blr 7949 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") monotonic 7950 ret i32 %ret 7951 } 7952 7953 define i32 @test471(i32* %ptr, i32 %val) { 7954 ; PPC64LE-LABEL: test471: 7955 ; PPC64LE: # %bb.0: 7956 ; PPC64LE-NEXT: mr 5, 3 7957 ; PPC64LE-NEXT: .LBB471_1: 7958 ; PPC64LE-NEXT: lwarx 3, 0, 5 7959 ; PPC64LE-NEXT: xor 6, 4, 3 7960 ; PPC64LE-NEXT: stwcx. 6, 0, 5 7961 ; PPC64LE-NEXT: bne 0, .LBB471_1 7962 ; PPC64LE-NEXT: # %bb.2: 7963 ; PPC64LE-NEXT: lwsync 7964 ; PPC64LE-NEXT: blr 7965 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acquire 7966 ret i32 %ret 7967 } 7968 7969 define i32 @test472(i32* %ptr, i32 %val) { 7970 ; PPC64LE-LABEL: test472: 7971 ; PPC64LE: # %bb.0: 7972 ; PPC64LE-NEXT: lwsync 7973 ; PPC64LE-NEXT: .LBB472_1: 7974 ; PPC64LE-NEXT: lwarx 5, 0, 3 7975 ; PPC64LE-NEXT: xor 6, 4, 5 7976 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7977 ; PPC64LE-NEXT: bne 0, .LBB472_1 7978 ; PPC64LE-NEXT: # %bb.2: 7979 ; PPC64LE-NEXT: mr 3, 5 7980 ; PPC64LE-NEXT: blr 7981 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") release 7982 ret i32 %ret 7983 } 7984 7985 define i32 @test473(i32* %ptr, i32 %val) { 7986 ; PPC64LE-LABEL: test473: 7987 ; PPC64LE: # %bb.0: 7988 ; PPC64LE-NEXT: lwsync 7989 ; PPC64LE-NEXT: .LBB473_1: 7990 ; PPC64LE-NEXT: lwarx 5, 0, 3 7991 ; PPC64LE-NEXT: xor 6, 4, 5 7992 ; PPC64LE-NEXT: stwcx. 6, 0, 3 7993 ; PPC64LE-NEXT: bne 0, .LBB473_1 7994 ; PPC64LE-NEXT: # %bb.2: 7995 ; PPC64LE-NEXT: mr 3, 5 7996 ; PPC64LE-NEXT: lwsync 7997 ; PPC64LE-NEXT: blr 7998 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acq_rel 7999 ret i32 %ret 8000 } 8001 8002 define i32 @test474(i32* %ptr, i32 %val) { 8003 ; PPC64LE-LABEL: test474: 8004 ; PPC64LE: # %bb.0: 8005 ; PPC64LE-NEXT: sync 8006 ; PPC64LE-NEXT: .LBB474_1: 8007 ; PPC64LE-NEXT: lwarx 5, 0, 3 8008 ; PPC64LE-NEXT: xor 6, 4, 5 8009 ; PPC64LE-NEXT: stwcx. 6, 0, 3 8010 ; PPC64LE-NEXT: bne 0, .LBB474_1 8011 ; PPC64LE-NEXT: # %bb.2: 8012 ; PPC64LE-NEXT: mr 3, 5 8013 ; PPC64LE-NEXT: lwsync 8014 ; PPC64LE-NEXT: blr 8015 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") seq_cst 8016 ret i32 %ret 8017 } 8018 8019 define i64 @test475(i64* %ptr, i64 %val) { 8020 ; PPC64LE-LABEL: test475: 8021 ; PPC64LE: # %bb.0: 8022 ; PPC64LE-NEXT: .LBB475_1: 8023 ; PPC64LE-NEXT: ldarx 5, 0, 3 8024 ; PPC64LE-NEXT: xor 6, 4, 5 8025 ; PPC64LE-NEXT: stdcx. 6, 0, 3 8026 ; PPC64LE-NEXT: bne 0, .LBB475_1 8027 ; PPC64LE-NEXT: # %bb.2: 8028 ; PPC64LE-NEXT: mr 3, 5 8029 ; PPC64LE-NEXT: blr 8030 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") monotonic 8031 ret i64 %ret 8032 } 8033 8034 define i64 @test476(i64* %ptr, i64 %val) { 8035 ; PPC64LE-LABEL: test476: 8036 ; PPC64LE: # %bb.0: 8037 ; PPC64LE-NEXT: mr 5, 3 8038 ; PPC64LE-NEXT: .LBB476_1: 8039 ; PPC64LE-NEXT: ldarx 3, 0, 5 8040 ; PPC64LE-NEXT: xor 6, 4, 3 8041 ; PPC64LE-NEXT: stdcx. 6, 0, 5 8042 ; PPC64LE-NEXT: bne 0, .LBB476_1 8043 ; PPC64LE-NEXT: # %bb.2: 8044 ; PPC64LE-NEXT: lwsync 8045 ; PPC64LE-NEXT: blr 8046 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acquire 8047 ret i64 %ret 8048 } 8049 8050 define i64 @test477(i64* %ptr, i64 %val) { 8051 ; PPC64LE-LABEL: test477: 8052 ; PPC64LE: # %bb.0: 8053 ; PPC64LE-NEXT: lwsync 8054 ; PPC64LE-NEXT: .LBB477_1: 8055 ; PPC64LE-NEXT: ldarx 5, 0, 3 8056 ; PPC64LE-NEXT: xor 6, 4, 5 8057 ; PPC64LE-NEXT: stdcx. 6, 0, 3 8058 ; PPC64LE-NEXT: bne 0, .LBB477_1 8059 ; PPC64LE-NEXT: # %bb.2: 8060 ; PPC64LE-NEXT: mr 3, 5 8061 ; PPC64LE-NEXT: blr 8062 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") release 8063 ret i64 %ret 8064 } 8065 8066 define i64 @test478(i64* %ptr, i64 %val) { 8067 ; PPC64LE-LABEL: test478: 8068 ; PPC64LE: # %bb.0: 8069 ; PPC64LE-NEXT: lwsync 8070 ; PPC64LE-NEXT: .LBB478_1: 8071 ; PPC64LE-NEXT: ldarx 5, 0, 3 8072 ; PPC64LE-NEXT: xor 6, 4, 5 8073 ; PPC64LE-NEXT: stdcx. 6, 0, 3 8074 ; PPC64LE-NEXT: bne 0, .LBB478_1 8075 ; PPC64LE-NEXT: # %bb.2: 8076 ; PPC64LE-NEXT: mr 3, 5 8077 ; PPC64LE-NEXT: lwsync 8078 ; PPC64LE-NEXT: blr 8079 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acq_rel 8080 ret i64 %ret 8081 } 8082 8083 define i64 @test479(i64* %ptr, i64 %val) { 8084 ; PPC64LE-LABEL: test479: 8085 ; PPC64LE: # %bb.0: 8086 ; PPC64LE-NEXT: sync 8087 ; PPC64LE-NEXT: .LBB479_1: 8088 ; PPC64LE-NEXT: ldarx 5, 0, 3 8089 ; PPC64LE-NEXT: xor 6, 4, 5 8090 ; PPC64LE-NEXT: stdcx. 6, 0, 3 8091 ; PPC64LE-NEXT: bne 0, .LBB479_1 8092 ; PPC64LE-NEXT: # %bb.2: 8093 ; PPC64LE-NEXT: mr 3, 5 8094 ; PPC64LE-NEXT: lwsync 8095 ; PPC64LE-NEXT: blr 8096 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") seq_cst 8097 ret i64 %ret 8098 } 8099 8100 define i8 @test480(i8* %ptr, i8 %val) { 8101 ; PPC64LE-LABEL: test480: 8102 ; PPC64LE: # %bb.0: 8103 ; PPC64LE-NEXT: .LBB480_1: 8104 ; PPC64LE-NEXT: lbarx 5, 0, 3 8105 ; PPC64LE-NEXT: extsb 6, 5 8106 ; PPC64LE-NEXT: cmpw 4, 6 8107 ; PPC64LE-NEXT: ble 0, .LBB480_3 8108 ; PPC64LE-NEXT: # %bb.2: 8109 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8110 ; PPC64LE-NEXT: bne 0, .LBB480_1 8111 ; PPC64LE-NEXT: .LBB480_3: 8112 ; PPC64LE-NEXT: mr 3, 5 8113 ; PPC64LE-NEXT: blr 8114 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") monotonic 8115 ret i8 %ret 8116 } 8117 8118 define i8 @test481(i8* %ptr, i8 %val) { 8119 ; PPC64LE-LABEL: test481: 8120 ; PPC64LE: # %bb.0: 8121 ; PPC64LE-NEXT: mr 5, 3 8122 ; PPC64LE-NEXT: .LBB481_1: 8123 ; PPC64LE-NEXT: lbarx 3, 0, 5 8124 ; PPC64LE-NEXT: extsb 6, 3 8125 ; PPC64LE-NEXT: cmpw 4, 6 8126 ; PPC64LE-NEXT: ble 0, .LBB481_3 8127 ; PPC64LE-NEXT: # %bb.2: 8128 ; PPC64LE-NEXT: stbcx. 4, 0, 5 8129 ; PPC64LE-NEXT: bne 0, .LBB481_1 8130 ; PPC64LE-NEXT: .LBB481_3: 8131 ; PPC64LE-NEXT: lwsync 8132 ; PPC64LE-NEXT: blr 8133 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acquire 8134 ret i8 %ret 8135 } 8136 8137 define i8 @test482(i8* %ptr, i8 %val) { 8138 ; PPC64LE-LABEL: test482: 8139 ; PPC64LE: # %bb.0: 8140 ; PPC64LE-NEXT: lwsync 8141 ; PPC64LE-NEXT: .LBB482_1: 8142 ; PPC64LE-NEXT: lbarx 5, 0, 3 8143 ; PPC64LE-NEXT: extsb 6, 5 8144 ; PPC64LE-NEXT: cmpw 4, 6 8145 ; PPC64LE-NEXT: ble 0, .LBB482_3 8146 ; PPC64LE-NEXT: # %bb.2: 8147 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8148 ; PPC64LE-NEXT: bne 0, .LBB482_1 8149 ; PPC64LE-NEXT: .LBB482_3: 8150 ; PPC64LE-NEXT: mr 3, 5 8151 ; PPC64LE-NEXT: blr 8152 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") release 8153 ret i8 %ret 8154 } 8155 8156 define i8 @test483(i8* %ptr, i8 %val) { 8157 ; PPC64LE-LABEL: test483: 8158 ; PPC64LE: # %bb.0: 8159 ; PPC64LE-NEXT: lwsync 8160 ; PPC64LE-NEXT: .LBB483_1: 8161 ; PPC64LE-NEXT: lbarx 5, 0, 3 8162 ; PPC64LE-NEXT: extsb 6, 5 8163 ; PPC64LE-NEXT: cmpw 4, 6 8164 ; PPC64LE-NEXT: ble 0, .LBB483_3 8165 ; PPC64LE-NEXT: # %bb.2: 8166 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8167 ; PPC64LE-NEXT: bne 0, .LBB483_1 8168 ; PPC64LE-NEXT: .LBB483_3: 8169 ; PPC64LE-NEXT: mr 3, 5 8170 ; PPC64LE-NEXT: lwsync 8171 ; PPC64LE-NEXT: blr 8172 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acq_rel 8173 ret i8 %ret 8174 } 8175 8176 define i8 @test484(i8* %ptr, i8 %val) { 8177 ; PPC64LE-LABEL: test484: 8178 ; PPC64LE: # %bb.0: 8179 ; PPC64LE-NEXT: sync 8180 ; PPC64LE-NEXT: .LBB484_1: 8181 ; PPC64LE-NEXT: lbarx 5, 0, 3 8182 ; PPC64LE-NEXT: extsb 6, 5 8183 ; PPC64LE-NEXT: cmpw 4, 6 8184 ; PPC64LE-NEXT: ble 0, .LBB484_3 8185 ; PPC64LE-NEXT: # %bb.2: 8186 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8187 ; PPC64LE-NEXT: bne 0, .LBB484_1 8188 ; PPC64LE-NEXT: .LBB484_3: 8189 ; PPC64LE-NEXT: mr 3, 5 8190 ; PPC64LE-NEXT: lwsync 8191 ; PPC64LE-NEXT: blr 8192 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") seq_cst 8193 ret i8 %ret 8194 } 8195 8196 define i16 @test485(i16* %ptr, i16 %val) { 8197 ; PPC64LE-LABEL: test485: 8198 ; PPC64LE: # %bb.0: 8199 ; PPC64LE-NEXT: .LBB485_1: 8200 ; PPC64LE-NEXT: lharx 5, 0, 3 8201 ; PPC64LE-NEXT: extsh 6, 5 8202 ; PPC64LE-NEXT: cmpw 4, 6 8203 ; PPC64LE-NEXT: ble 0, .LBB485_3 8204 ; PPC64LE-NEXT: # %bb.2: 8205 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8206 ; PPC64LE-NEXT: bne 0, .LBB485_1 8207 ; PPC64LE-NEXT: .LBB485_3: 8208 ; PPC64LE-NEXT: mr 3, 5 8209 ; PPC64LE-NEXT: blr 8210 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") monotonic 8211 ret i16 %ret 8212 } 8213 8214 define i16 @test486(i16* %ptr, i16 %val) { 8215 ; PPC64LE-LABEL: test486: 8216 ; PPC64LE: # %bb.0: 8217 ; PPC64LE-NEXT: mr 5, 3 8218 ; PPC64LE-NEXT: .LBB486_1: 8219 ; PPC64LE-NEXT: lharx 3, 0, 5 8220 ; PPC64LE-NEXT: extsh 6, 3 8221 ; PPC64LE-NEXT: cmpw 4, 6 8222 ; PPC64LE-NEXT: ble 0, .LBB486_3 8223 ; PPC64LE-NEXT: # %bb.2: 8224 ; PPC64LE-NEXT: sthcx. 4, 0, 5 8225 ; PPC64LE-NEXT: bne 0, .LBB486_1 8226 ; PPC64LE-NEXT: .LBB486_3: 8227 ; PPC64LE-NEXT: lwsync 8228 ; PPC64LE-NEXT: blr 8229 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acquire 8230 ret i16 %ret 8231 } 8232 8233 define i16 @test487(i16* %ptr, i16 %val) { 8234 ; PPC64LE-LABEL: test487: 8235 ; PPC64LE: # %bb.0: 8236 ; PPC64LE-NEXT: lwsync 8237 ; PPC64LE-NEXT: .LBB487_1: 8238 ; PPC64LE-NEXT: lharx 5, 0, 3 8239 ; PPC64LE-NEXT: extsh 6, 5 8240 ; PPC64LE-NEXT: cmpw 4, 6 8241 ; PPC64LE-NEXT: ble 0, .LBB487_3 8242 ; PPC64LE-NEXT: # %bb.2: 8243 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8244 ; PPC64LE-NEXT: bne 0, .LBB487_1 8245 ; PPC64LE-NEXT: .LBB487_3: 8246 ; PPC64LE-NEXT: mr 3, 5 8247 ; PPC64LE-NEXT: blr 8248 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") release 8249 ret i16 %ret 8250 } 8251 8252 define i16 @test488(i16* %ptr, i16 %val) { 8253 ; PPC64LE-LABEL: test488: 8254 ; PPC64LE: # %bb.0: 8255 ; PPC64LE-NEXT: lwsync 8256 ; PPC64LE-NEXT: .LBB488_1: 8257 ; PPC64LE-NEXT: lharx 5, 0, 3 8258 ; PPC64LE-NEXT: extsh 6, 5 8259 ; PPC64LE-NEXT: cmpw 4, 6 8260 ; PPC64LE-NEXT: ble 0, .LBB488_3 8261 ; PPC64LE-NEXT: # %bb.2: 8262 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8263 ; PPC64LE-NEXT: bne 0, .LBB488_1 8264 ; PPC64LE-NEXT: .LBB488_3: 8265 ; PPC64LE-NEXT: mr 3, 5 8266 ; PPC64LE-NEXT: lwsync 8267 ; PPC64LE-NEXT: blr 8268 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acq_rel 8269 ret i16 %ret 8270 } 8271 8272 define i16 @test489(i16* %ptr, i16 %val) { 8273 ; PPC64LE-LABEL: test489: 8274 ; PPC64LE: # %bb.0: 8275 ; PPC64LE-NEXT: sync 8276 ; PPC64LE-NEXT: .LBB489_1: 8277 ; PPC64LE-NEXT: lharx 5, 0, 3 8278 ; PPC64LE-NEXT: extsh 6, 5 8279 ; PPC64LE-NEXT: cmpw 4, 6 8280 ; PPC64LE-NEXT: ble 0, .LBB489_3 8281 ; PPC64LE-NEXT: # %bb.2: 8282 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8283 ; PPC64LE-NEXT: bne 0, .LBB489_1 8284 ; PPC64LE-NEXT: .LBB489_3: 8285 ; PPC64LE-NEXT: mr 3, 5 8286 ; PPC64LE-NEXT: lwsync 8287 ; PPC64LE-NEXT: blr 8288 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") seq_cst 8289 ret i16 %ret 8290 } 8291 8292 define i32 @test490(i32* %ptr, i32 %val) { 8293 ; PPC64LE-LABEL: test490: 8294 ; PPC64LE: # %bb.0: 8295 ; PPC64LE-NEXT: .LBB490_1: 8296 ; PPC64LE-NEXT: lwarx 5, 0, 3 8297 ; PPC64LE-NEXT: cmpw 4, 5 8298 ; PPC64LE-NEXT: ble 0, .LBB490_3 8299 ; PPC64LE-NEXT: # %bb.2: 8300 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8301 ; PPC64LE-NEXT: bne 0, .LBB490_1 8302 ; PPC64LE-NEXT: .LBB490_3: 8303 ; PPC64LE-NEXT: mr 3, 5 8304 ; PPC64LE-NEXT: blr 8305 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") monotonic 8306 ret i32 %ret 8307 } 8308 8309 define i32 @test491(i32* %ptr, i32 %val) { 8310 ; PPC64LE-LABEL: test491: 8311 ; PPC64LE: # %bb.0: 8312 ; PPC64LE-NEXT: mr 5, 3 8313 ; PPC64LE-NEXT: .LBB491_1: 8314 ; PPC64LE-NEXT: lwarx 3, 0, 5 8315 ; PPC64LE-NEXT: cmpw 4, 3 8316 ; PPC64LE-NEXT: ble 0, .LBB491_3 8317 ; PPC64LE-NEXT: # %bb.2: 8318 ; PPC64LE-NEXT: stwcx. 4, 0, 5 8319 ; PPC64LE-NEXT: bne 0, .LBB491_1 8320 ; PPC64LE-NEXT: .LBB491_3: 8321 ; PPC64LE-NEXT: lwsync 8322 ; PPC64LE-NEXT: blr 8323 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acquire 8324 ret i32 %ret 8325 } 8326 8327 define i32 @test492(i32* %ptr, i32 %val) { 8328 ; PPC64LE-LABEL: test492: 8329 ; PPC64LE: # %bb.0: 8330 ; PPC64LE-NEXT: lwsync 8331 ; PPC64LE-NEXT: .LBB492_1: 8332 ; PPC64LE-NEXT: lwarx 5, 0, 3 8333 ; PPC64LE-NEXT: cmpw 4, 5 8334 ; PPC64LE-NEXT: ble 0, .LBB492_3 8335 ; PPC64LE-NEXT: # %bb.2: 8336 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8337 ; PPC64LE-NEXT: bne 0, .LBB492_1 8338 ; PPC64LE-NEXT: .LBB492_3: 8339 ; PPC64LE-NEXT: mr 3, 5 8340 ; PPC64LE-NEXT: blr 8341 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") release 8342 ret i32 %ret 8343 } 8344 8345 define i32 @test493(i32* %ptr, i32 %val) { 8346 ; PPC64LE-LABEL: test493: 8347 ; PPC64LE: # %bb.0: 8348 ; PPC64LE-NEXT: lwsync 8349 ; PPC64LE-NEXT: .LBB493_1: 8350 ; PPC64LE-NEXT: lwarx 5, 0, 3 8351 ; PPC64LE-NEXT: cmpw 4, 5 8352 ; PPC64LE-NEXT: ble 0, .LBB493_3 8353 ; PPC64LE-NEXT: # %bb.2: 8354 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8355 ; PPC64LE-NEXT: bne 0, .LBB493_1 8356 ; PPC64LE-NEXT: .LBB493_3: 8357 ; PPC64LE-NEXT: mr 3, 5 8358 ; PPC64LE-NEXT: lwsync 8359 ; PPC64LE-NEXT: blr 8360 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acq_rel 8361 ret i32 %ret 8362 } 8363 8364 define i32 @test494(i32* %ptr, i32 %val) { 8365 ; PPC64LE-LABEL: test494: 8366 ; PPC64LE: # %bb.0: 8367 ; PPC64LE-NEXT: sync 8368 ; PPC64LE-NEXT: .LBB494_1: 8369 ; PPC64LE-NEXT: lwarx 5, 0, 3 8370 ; PPC64LE-NEXT: cmpw 4, 5 8371 ; PPC64LE-NEXT: ble 0, .LBB494_3 8372 ; PPC64LE-NEXT: # %bb.2: 8373 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8374 ; PPC64LE-NEXT: bne 0, .LBB494_1 8375 ; PPC64LE-NEXT: .LBB494_3: 8376 ; PPC64LE-NEXT: mr 3, 5 8377 ; PPC64LE-NEXT: lwsync 8378 ; PPC64LE-NEXT: blr 8379 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") seq_cst 8380 ret i32 %ret 8381 } 8382 8383 define i64 @test495(i64* %ptr, i64 %val) { 8384 ; PPC64LE-LABEL: test495: 8385 ; PPC64LE: # %bb.0: 8386 ; PPC64LE-NEXT: .LBB495_1: 8387 ; PPC64LE-NEXT: ldarx 5, 0, 3 8388 ; PPC64LE-NEXT: cmpd 4, 5 8389 ; PPC64LE-NEXT: ble 0, .LBB495_3 8390 ; PPC64LE-NEXT: # %bb.2: 8391 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8392 ; PPC64LE-NEXT: bne 0, .LBB495_1 8393 ; PPC64LE-NEXT: .LBB495_3: 8394 ; PPC64LE-NEXT: mr 3, 5 8395 ; PPC64LE-NEXT: blr 8396 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") monotonic 8397 ret i64 %ret 8398 } 8399 8400 define i64 @test496(i64* %ptr, i64 %val) { 8401 ; PPC64LE-LABEL: test496: 8402 ; PPC64LE: # %bb.0: 8403 ; PPC64LE-NEXT: mr 5, 3 8404 ; PPC64LE-NEXT: .LBB496_1: 8405 ; PPC64LE-NEXT: ldarx 3, 0, 5 8406 ; PPC64LE-NEXT: cmpd 4, 3 8407 ; PPC64LE-NEXT: ble 0, .LBB496_3 8408 ; PPC64LE-NEXT: # %bb.2: 8409 ; PPC64LE-NEXT: stdcx. 4, 0, 5 8410 ; PPC64LE-NEXT: bne 0, .LBB496_1 8411 ; PPC64LE-NEXT: .LBB496_3: 8412 ; PPC64LE-NEXT: lwsync 8413 ; PPC64LE-NEXT: blr 8414 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acquire 8415 ret i64 %ret 8416 } 8417 8418 define i64 @test497(i64* %ptr, i64 %val) { 8419 ; PPC64LE-LABEL: test497: 8420 ; PPC64LE: # %bb.0: 8421 ; PPC64LE-NEXT: lwsync 8422 ; PPC64LE-NEXT: .LBB497_1: 8423 ; PPC64LE-NEXT: ldarx 5, 0, 3 8424 ; PPC64LE-NEXT: cmpd 4, 5 8425 ; PPC64LE-NEXT: ble 0, .LBB497_3 8426 ; PPC64LE-NEXT: # %bb.2: 8427 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8428 ; PPC64LE-NEXT: bne 0, .LBB497_1 8429 ; PPC64LE-NEXT: .LBB497_3: 8430 ; PPC64LE-NEXT: mr 3, 5 8431 ; PPC64LE-NEXT: blr 8432 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") release 8433 ret i64 %ret 8434 } 8435 8436 define i64 @test498(i64* %ptr, i64 %val) { 8437 ; PPC64LE-LABEL: test498: 8438 ; PPC64LE: # %bb.0: 8439 ; PPC64LE-NEXT: lwsync 8440 ; PPC64LE-NEXT: .LBB498_1: 8441 ; PPC64LE-NEXT: ldarx 5, 0, 3 8442 ; PPC64LE-NEXT: cmpd 4, 5 8443 ; PPC64LE-NEXT: ble 0, .LBB498_3 8444 ; PPC64LE-NEXT: # %bb.2: 8445 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8446 ; PPC64LE-NEXT: bne 0, .LBB498_1 8447 ; PPC64LE-NEXT: .LBB498_3: 8448 ; PPC64LE-NEXT: mr 3, 5 8449 ; PPC64LE-NEXT: lwsync 8450 ; PPC64LE-NEXT: blr 8451 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acq_rel 8452 ret i64 %ret 8453 } 8454 8455 define i64 @test499(i64* %ptr, i64 %val) { 8456 ; PPC64LE-LABEL: test499: 8457 ; PPC64LE: # %bb.0: 8458 ; PPC64LE-NEXT: sync 8459 ; PPC64LE-NEXT: .LBB499_1: 8460 ; PPC64LE-NEXT: ldarx 5, 0, 3 8461 ; PPC64LE-NEXT: cmpd 4, 5 8462 ; PPC64LE-NEXT: ble 0, .LBB499_3 8463 ; PPC64LE-NEXT: # %bb.2: 8464 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8465 ; PPC64LE-NEXT: bne 0, .LBB499_1 8466 ; PPC64LE-NEXT: .LBB499_3: 8467 ; PPC64LE-NEXT: mr 3, 5 8468 ; PPC64LE-NEXT: lwsync 8469 ; PPC64LE-NEXT: blr 8470 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") seq_cst 8471 ret i64 %ret 8472 } 8473 8474 define i8 @test500(i8* %ptr, i8 %val) { 8475 ; PPC64LE-LABEL: test500: 8476 ; PPC64LE: # %bb.0: 8477 ; PPC64LE-NEXT: .LBB500_1: 8478 ; PPC64LE-NEXT: lbarx 5, 0, 3 8479 ; PPC64LE-NEXT: extsb 6, 5 8480 ; PPC64LE-NEXT: cmpw 4, 6 8481 ; PPC64LE-NEXT: bge 0, .LBB500_3 8482 ; PPC64LE-NEXT: # %bb.2: 8483 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8484 ; PPC64LE-NEXT: bne 0, .LBB500_1 8485 ; PPC64LE-NEXT: .LBB500_3: 8486 ; PPC64LE-NEXT: mr 3, 5 8487 ; PPC64LE-NEXT: blr 8488 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") monotonic 8489 ret i8 %ret 8490 } 8491 8492 define i8 @test501(i8* %ptr, i8 %val) { 8493 ; PPC64LE-LABEL: test501: 8494 ; PPC64LE: # %bb.0: 8495 ; PPC64LE-NEXT: mr 5, 3 8496 ; PPC64LE-NEXT: .LBB501_1: 8497 ; PPC64LE-NEXT: lbarx 3, 0, 5 8498 ; PPC64LE-NEXT: extsb 6, 3 8499 ; PPC64LE-NEXT: cmpw 4, 6 8500 ; PPC64LE-NEXT: bge 0, .LBB501_3 8501 ; PPC64LE-NEXT: # %bb.2: 8502 ; PPC64LE-NEXT: stbcx. 4, 0, 5 8503 ; PPC64LE-NEXT: bne 0, .LBB501_1 8504 ; PPC64LE-NEXT: .LBB501_3: 8505 ; PPC64LE-NEXT: lwsync 8506 ; PPC64LE-NEXT: blr 8507 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acquire 8508 ret i8 %ret 8509 } 8510 8511 define i8 @test502(i8* %ptr, i8 %val) { 8512 ; PPC64LE-LABEL: test502: 8513 ; PPC64LE: # %bb.0: 8514 ; PPC64LE-NEXT: lwsync 8515 ; PPC64LE-NEXT: .LBB502_1: 8516 ; PPC64LE-NEXT: lbarx 5, 0, 3 8517 ; PPC64LE-NEXT: extsb 6, 5 8518 ; PPC64LE-NEXT: cmpw 4, 6 8519 ; PPC64LE-NEXT: bge 0, .LBB502_3 8520 ; PPC64LE-NEXT: # %bb.2: 8521 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8522 ; PPC64LE-NEXT: bne 0, .LBB502_1 8523 ; PPC64LE-NEXT: .LBB502_3: 8524 ; PPC64LE-NEXT: mr 3, 5 8525 ; PPC64LE-NEXT: blr 8526 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") release 8527 ret i8 %ret 8528 } 8529 8530 define i8 @test503(i8* %ptr, i8 %val) { 8531 ; PPC64LE-LABEL: test503: 8532 ; PPC64LE: # %bb.0: 8533 ; PPC64LE-NEXT: lwsync 8534 ; PPC64LE-NEXT: .LBB503_1: 8535 ; PPC64LE-NEXT: lbarx 5, 0, 3 8536 ; PPC64LE-NEXT: extsb 6, 5 8537 ; PPC64LE-NEXT: cmpw 4, 6 8538 ; PPC64LE-NEXT: bge 0, .LBB503_3 8539 ; PPC64LE-NEXT: # %bb.2: 8540 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8541 ; PPC64LE-NEXT: bne 0, .LBB503_1 8542 ; PPC64LE-NEXT: .LBB503_3: 8543 ; PPC64LE-NEXT: mr 3, 5 8544 ; PPC64LE-NEXT: lwsync 8545 ; PPC64LE-NEXT: blr 8546 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acq_rel 8547 ret i8 %ret 8548 } 8549 8550 define i8 @test504(i8* %ptr, i8 %val) { 8551 ; PPC64LE-LABEL: test504: 8552 ; PPC64LE: # %bb.0: 8553 ; PPC64LE-NEXT: sync 8554 ; PPC64LE-NEXT: .LBB504_1: 8555 ; PPC64LE-NEXT: lbarx 5, 0, 3 8556 ; PPC64LE-NEXT: extsb 6, 5 8557 ; PPC64LE-NEXT: cmpw 4, 6 8558 ; PPC64LE-NEXT: bge 0, .LBB504_3 8559 ; PPC64LE-NEXT: # %bb.2: 8560 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8561 ; PPC64LE-NEXT: bne 0, .LBB504_1 8562 ; PPC64LE-NEXT: .LBB504_3: 8563 ; PPC64LE-NEXT: mr 3, 5 8564 ; PPC64LE-NEXT: lwsync 8565 ; PPC64LE-NEXT: blr 8566 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") seq_cst 8567 ret i8 %ret 8568 } 8569 8570 define i16 @test505(i16* %ptr, i16 %val) { 8571 ; PPC64LE-LABEL: test505: 8572 ; PPC64LE: # %bb.0: 8573 ; PPC64LE-NEXT: .LBB505_1: 8574 ; PPC64LE-NEXT: lharx 5, 0, 3 8575 ; PPC64LE-NEXT: extsh 6, 5 8576 ; PPC64LE-NEXT: cmpw 4, 6 8577 ; PPC64LE-NEXT: bge 0, .LBB505_3 8578 ; PPC64LE-NEXT: # %bb.2: 8579 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8580 ; PPC64LE-NEXT: bne 0, .LBB505_1 8581 ; PPC64LE-NEXT: .LBB505_3: 8582 ; PPC64LE-NEXT: mr 3, 5 8583 ; PPC64LE-NEXT: blr 8584 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") monotonic 8585 ret i16 %ret 8586 } 8587 8588 define i16 @test506(i16* %ptr, i16 %val) { 8589 ; PPC64LE-LABEL: test506: 8590 ; PPC64LE: # %bb.0: 8591 ; PPC64LE-NEXT: mr 5, 3 8592 ; PPC64LE-NEXT: .LBB506_1: 8593 ; PPC64LE-NEXT: lharx 3, 0, 5 8594 ; PPC64LE-NEXT: extsh 6, 3 8595 ; PPC64LE-NEXT: cmpw 4, 6 8596 ; PPC64LE-NEXT: bge 0, .LBB506_3 8597 ; PPC64LE-NEXT: # %bb.2: 8598 ; PPC64LE-NEXT: sthcx. 4, 0, 5 8599 ; PPC64LE-NEXT: bne 0, .LBB506_1 8600 ; PPC64LE-NEXT: .LBB506_3: 8601 ; PPC64LE-NEXT: lwsync 8602 ; PPC64LE-NEXT: blr 8603 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acquire 8604 ret i16 %ret 8605 } 8606 8607 define i16 @test507(i16* %ptr, i16 %val) { 8608 ; PPC64LE-LABEL: test507: 8609 ; PPC64LE: # %bb.0: 8610 ; PPC64LE-NEXT: lwsync 8611 ; PPC64LE-NEXT: .LBB507_1: 8612 ; PPC64LE-NEXT: lharx 5, 0, 3 8613 ; PPC64LE-NEXT: extsh 6, 5 8614 ; PPC64LE-NEXT: cmpw 4, 6 8615 ; PPC64LE-NEXT: bge 0, .LBB507_3 8616 ; PPC64LE-NEXT: # %bb.2: 8617 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8618 ; PPC64LE-NEXT: bne 0, .LBB507_1 8619 ; PPC64LE-NEXT: .LBB507_3: 8620 ; PPC64LE-NEXT: mr 3, 5 8621 ; PPC64LE-NEXT: blr 8622 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") release 8623 ret i16 %ret 8624 } 8625 8626 define i16 @test508(i16* %ptr, i16 %val) { 8627 ; PPC64LE-LABEL: test508: 8628 ; PPC64LE: # %bb.0: 8629 ; PPC64LE-NEXT: lwsync 8630 ; PPC64LE-NEXT: .LBB508_1: 8631 ; PPC64LE-NEXT: lharx 5, 0, 3 8632 ; PPC64LE-NEXT: extsh 6, 5 8633 ; PPC64LE-NEXT: cmpw 4, 6 8634 ; PPC64LE-NEXT: bge 0, .LBB508_3 8635 ; PPC64LE-NEXT: # %bb.2: 8636 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8637 ; PPC64LE-NEXT: bne 0, .LBB508_1 8638 ; PPC64LE-NEXT: .LBB508_3: 8639 ; PPC64LE-NEXT: mr 3, 5 8640 ; PPC64LE-NEXT: lwsync 8641 ; PPC64LE-NEXT: blr 8642 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acq_rel 8643 ret i16 %ret 8644 } 8645 8646 define i16 @test509(i16* %ptr, i16 %val) { 8647 ; PPC64LE-LABEL: test509: 8648 ; PPC64LE: # %bb.0: 8649 ; PPC64LE-NEXT: sync 8650 ; PPC64LE-NEXT: .LBB509_1: 8651 ; PPC64LE-NEXT: lharx 5, 0, 3 8652 ; PPC64LE-NEXT: extsh 6, 5 8653 ; PPC64LE-NEXT: cmpw 4, 6 8654 ; PPC64LE-NEXT: bge 0, .LBB509_3 8655 ; PPC64LE-NEXT: # %bb.2: 8656 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8657 ; PPC64LE-NEXT: bne 0, .LBB509_1 8658 ; PPC64LE-NEXT: .LBB509_3: 8659 ; PPC64LE-NEXT: mr 3, 5 8660 ; PPC64LE-NEXT: lwsync 8661 ; PPC64LE-NEXT: blr 8662 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") seq_cst 8663 ret i16 %ret 8664 } 8665 8666 define i32 @test510(i32* %ptr, i32 %val) { 8667 ; PPC64LE-LABEL: test510: 8668 ; PPC64LE: # %bb.0: 8669 ; PPC64LE-NEXT: .LBB510_1: 8670 ; PPC64LE-NEXT: lwarx 5, 0, 3 8671 ; PPC64LE-NEXT: cmpw 4, 5 8672 ; PPC64LE-NEXT: bge 0, .LBB510_3 8673 ; PPC64LE-NEXT: # %bb.2: 8674 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8675 ; PPC64LE-NEXT: bne 0, .LBB510_1 8676 ; PPC64LE-NEXT: .LBB510_3: 8677 ; PPC64LE-NEXT: mr 3, 5 8678 ; PPC64LE-NEXT: blr 8679 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") monotonic 8680 ret i32 %ret 8681 } 8682 8683 define i32 @test511(i32* %ptr, i32 %val) { 8684 ; PPC64LE-LABEL: test511: 8685 ; PPC64LE: # %bb.0: 8686 ; PPC64LE-NEXT: mr 5, 3 8687 ; PPC64LE-NEXT: .LBB511_1: 8688 ; PPC64LE-NEXT: lwarx 3, 0, 5 8689 ; PPC64LE-NEXT: cmpw 4, 3 8690 ; PPC64LE-NEXT: bge 0, .LBB511_3 8691 ; PPC64LE-NEXT: # %bb.2: 8692 ; PPC64LE-NEXT: stwcx. 4, 0, 5 8693 ; PPC64LE-NEXT: bne 0, .LBB511_1 8694 ; PPC64LE-NEXT: .LBB511_3: 8695 ; PPC64LE-NEXT: lwsync 8696 ; PPC64LE-NEXT: blr 8697 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acquire 8698 ret i32 %ret 8699 } 8700 8701 define i32 @test512(i32* %ptr, i32 %val) { 8702 ; PPC64LE-LABEL: test512: 8703 ; PPC64LE: # %bb.0: 8704 ; PPC64LE-NEXT: lwsync 8705 ; PPC64LE-NEXT: .LBB512_1: 8706 ; PPC64LE-NEXT: lwarx 5, 0, 3 8707 ; PPC64LE-NEXT: cmpw 4, 5 8708 ; PPC64LE-NEXT: bge 0, .LBB512_3 8709 ; PPC64LE-NEXT: # %bb.2: 8710 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8711 ; PPC64LE-NEXT: bne 0, .LBB512_1 8712 ; PPC64LE-NEXT: .LBB512_3: 8713 ; PPC64LE-NEXT: mr 3, 5 8714 ; PPC64LE-NEXT: blr 8715 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") release 8716 ret i32 %ret 8717 } 8718 8719 define i32 @test513(i32* %ptr, i32 %val) { 8720 ; PPC64LE-LABEL: test513: 8721 ; PPC64LE: # %bb.0: 8722 ; PPC64LE-NEXT: lwsync 8723 ; PPC64LE-NEXT: .LBB513_1: 8724 ; PPC64LE-NEXT: lwarx 5, 0, 3 8725 ; PPC64LE-NEXT: cmpw 4, 5 8726 ; PPC64LE-NEXT: bge 0, .LBB513_3 8727 ; PPC64LE-NEXT: # %bb.2: 8728 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8729 ; PPC64LE-NEXT: bne 0, .LBB513_1 8730 ; PPC64LE-NEXT: .LBB513_3: 8731 ; PPC64LE-NEXT: mr 3, 5 8732 ; PPC64LE-NEXT: lwsync 8733 ; PPC64LE-NEXT: blr 8734 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acq_rel 8735 ret i32 %ret 8736 } 8737 8738 define i32 @test514(i32* %ptr, i32 %val) { 8739 ; PPC64LE-LABEL: test514: 8740 ; PPC64LE: # %bb.0: 8741 ; PPC64LE-NEXT: sync 8742 ; PPC64LE-NEXT: .LBB514_1: 8743 ; PPC64LE-NEXT: lwarx 5, 0, 3 8744 ; PPC64LE-NEXT: cmpw 4, 5 8745 ; PPC64LE-NEXT: bge 0, .LBB514_3 8746 ; PPC64LE-NEXT: # %bb.2: 8747 ; PPC64LE-NEXT: stwcx. 4, 0, 3 8748 ; PPC64LE-NEXT: bne 0, .LBB514_1 8749 ; PPC64LE-NEXT: .LBB514_3: 8750 ; PPC64LE-NEXT: mr 3, 5 8751 ; PPC64LE-NEXT: lwsync 8752 ; PPC64LE-NEXT: blr 8753 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") seq_cst 8754 ret i32 %ret 8755 } 8756 8757 define i64 @test515(i64* %ptr, i64 %val) { 8758 ; PPC64LE-LABEL: test515: 8759 ; PPC64LE: # %bb.0: 8760 ; PPC64LE-NEXT: .LBB515_1: 8761 ; PPC64LE-NEXT: ldarx 5, 0, 3 8762 ; PPC64LE-NEXT: cmpd 4, 5 8763 ; PPC64LE-NEXT: bge 0, .LBB515_3 8764 ; PPC64LE-NEXT: # %bb.2: 8765 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8766 ; PPC64LE-NEXT: bne 0, .LBB515_1 8767 ; PPC64LE-NEXT: .LBB515_3: 8768 ; PPC64LE-NEXT: mr 3, 5 8769 ; PPC64LE-NEXT: blr 8770 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") monotonic 8771 ret i64 %ret 8772 } 8773 8774 define i64 @test516(i64* %ptr, i64 %val) { 8775 ; PPC64LE-LABEL: test516: 8776 ; PPC64LE: # %bb.0: 8777 ; PPC64LE-NEXT: mr 5, 3 8778 ; PPC64LE-NEXT: .LBB516_1: 8779 ; PPC64LE-NEXT: ldarx 3, 0, 5 8780 ; PPC64LE-NEXT: cmpd 4, 3 8781 ; PPC64LE-NEXT: bge 0, .LBB516_3 8782 ; PPC64LE-NEXT: # %bb.2: 8783 ; PPC64LE-NEXT: stdcx. 4, 0, 5 8784 ; PPC64LE-NEXT: bne 0, .LBB516_1 8785 ; PPC64LE-NEXT: .LBB516_3: 8786 ; PPC64LE-NEXT: lwsync 8787 ; PPC64LE-NEXT: blr 8788 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acquire 8789 ret i64 %ret 8790 } 8791 8792 define i64 @test517(i64* %ptr, i64 %val) { 8793 ; PPC64LE-LABEL: test517: 8794 ; PPC64LE: # %bb.0: 8795 ; PPC64LE-NEXT: lwsync 8796 ; PPC64LE-NEXT: .LBB517_1: 8797 ; PPC64LE-NEXT: ldarx 5, 0, 3 8798 ; PPC64LE-NEXT: cmpd 4, 5 8799 ; PPC64LE-NEXT: bge 0, .LBB517_3 8800 ; PPC64LE-NEXT: # %bb.2: 8801 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8802 ; PPC64LE-NEXT: bne 0, .LBB517_1 8803 ; PPC64LE-NEXT: .LBB517_3: 8804 ; PPC64LE-NEXT: mr 3, 5 8805 ; PPC64LE-NEXT: blr 8806 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") release 8807 ret i64 %ret 8808 } 8809 8810 define i64 @test518(i64* %ptr, i64 %val) { 8811 ; PPC64LE-LABEL: test518: 8812 ; PPC64LE: # %bb.0: 8813 ; PPC64LE-NEXT: lwsync 8814 ; PPC64LE-NEXT: .LBB518_1: 8815 ; PPC64LE-NEXT: ldarx 5, 0, 3 8816 ; PPC64LE-NEXT: cmpd 4, 5 8817 ; PPC64LE-NEXT: bge 0, .LBB518_3 8818 ; PPC64LE-NEXT: # %bb.2: 8819 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8820 ; PPC64LE-NEXT: bne 0, .LBB518_1 8821 ; PPC64LE-NEXT: .LBB518_3: 8822 ; PPC64LE-NEXT: mr 3, 5 8823 ; PPC64LE-NEXT: lwsync 8824 ; PPC64LE-NEXT: blr 8825 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acq_rel 8826 ret i64 %ret 8827 } 8828 8829 define i64 @test519(i64* %ptr, i64 %val) { 8830 ; PPC64LE-LABEL: test519: 8831 ; PPC64LE: # %bb.0: 8832 ; PPC64LE-NEXT: sync 8833 ; PPC64LE-NEXT: .LBB519_1: 8834 ; PPC64LE-NEXT: ldarx 5, 0, 3 8835 ; PPC64LE-NEXT: cmpd 4, 5 8836 ; PPC64LE-NEXT: bge 0, .LBB519_3 8837 ; PPC64LE-NEXT: # %bb.2: 8838 ; PPC64LE-NEXT: stdcx. 4, 0, 3 8839 ; PPC64LE-NEXT: bne 0, .LBB519_1 8840 ; PPC64LE-NEXT: .LBB519_3: 8841 ; PPC64LE-NEXT: mr 3, 5 8842 ; PPC64LE-NEXT: lwsync 8843 ; PPC64LE-NEXT: blr 8844 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") seq_cst 8845 ret i64 %ret 8846 } 8847 8848 define i8 @test520(i8* %ptr, i8 %val) { 8849 ; PPC64LE-LABEL: test520: 8850 ; PPC64LE: # %bb.0: 8851 ; PPC64LE-NEXT: .LBB520_1: 8852 ; PPC64LE-NEXT: lbarx 5, 0, 3 8853 ; PPC64LE-NEXT: cmplw 4, 5 8854 ; PPC64LE-NEXT: ble 0, .LBB520_3 8855 ; PPC64LE-NEXT: # %bb.2: 8856 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8857 ; PPC64LE-NEXT: bne 0, .LBB520_1 8858 ; PPC64LE-NEXT: .LBB520_3: 8859 ; PPC64LE-NEXT: mr 3, 5 8860 ; PPC64LE-NEXT: blr 8861 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") monotonic 8862 ret i8 %ret 8863 } 8864 8865 define i8 @test521(i8* %ptr, i8 %val) { 8866 ; PPC64LE-LABEL: test521: 8867 ; PPC64LE: # %bb.0: 8868 ; PPC64LE-NEXT: mr 5, 3 8869 ; PPC64LE-NEXT: .LBB521_1: 8870 ; PPC64LE-NEXT: lbarx 3, 0, 5 8871 ; PPC64LE-NEXT: cmplw 4, 3 8872 ; PPC64LE-NEXT: ble 0, .LBB521_3 8873 ; PPC64LE-NEXT: # %bb.2: 8874 ; PPC64LE-NEXT: stbcx. 4, 0, 5 8875 ; PPC64LE-NEXT: bne 0, .LBB521_1 8876 ; PPC64LE-NEXT: .LBB521_3: 8877 ; PPC64LE-NEXT: lwsync 8878 ; PPC64LE-NEXT: blr 8879 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acquire 8880 ret i8 %ret 8881 } 8882 8883 define i8 @test522(i8* %ptr, i8 %val) { 8884 ; PPC64LE-LABEL: test522: 8885 ; PPC64LE: # %bb.0: 8886 ; PPC64LE-NEXT: lwsync 8887 ; PPC64LE-NEXT: .LBB522_1: 8888 ; PPC64LE-NEXT: lbarx 5, 0, 3 8889 ; PPC64LE-NEXT: cmplw 4, 5 8890 ; PPC64LE-NEXT: ble 0, .LBB522_3 8891 ; PPC64LE-NEXT: # %bb.2: 8892 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8893 ; PPC64LE-NEXT: bne 0, .LBB522_1 8894 ; PPC64LE-NEXT: .LBB522_3: 8895 ; PPC64LE-NEXT: mr 3, 5 8896 ; PPC64LE-NEXT: blr 8897 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") release 8898 ret i8 %ret 8899 } 8900 8901 define i8 @test523(i8* %ptr, i8 %val) { 8902 ; PPC64LE-LABEL: test523: 8903 ; PPC64LE: # %bb.0: 8904 ; PPC64LE-NEXT: lwsync 8905 ; PPC64LE-NEXT: .LBB523_1: 8906 ; PPC64LE-NEXT: lbarx 5, 0, 3 8907 ; PPC64LE-NEXT: cmplw 4, 5 8908 ; PPC64LE-NEXT: ble 0, .LBB523_3 8909 ; PPC64LE-NEXT: # %bb.2: 8910 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8911 ; PPC64LE-NEXT: bne 0, .LBB523_1 8912 ; PPC64LE-NEXT: .LBB523_3: 8913 ; PPC64LE-NEXT: mr 3, 5 8914 ; PPC64LE-NEXT: lwsync 8915 ; PPC64LE-NEXT: blr 8916 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acq_rel 8917 ret i8 %ret 8918 } 8919 8920 define i8 @test524(i8* %ptr, i8 %val) { 8921 ; PPC64LE-LABEL: test524: 8922 ; PPC64LE: # %bb.0: 8923 ; PPC64LE-NEXT: sync 8924 ; PPC64LE-NEXT: .LBB524_1: 8925 ; PPC64LE-NEXT: lbarx 5, 0, 3 8926 ; PPC64LE-NEXT: cmplw 4, 5 8927 ; PPC64LE-NEXT: ble 0, .LBB524_3 8928 ; PPC64LE-NEXT: # %bb.2: 8929 ; PPC64LE-NEXT: stbcx. 4, 0, 3 8930 ; PPC64LE-NEXT: bne 0, .LBB524_1 8931 ; PPC64LE-NEXT: .LBB524_3: 8932 ; PPC64LE-NEXT: mr 3, 5 8933 ; PPC64LE-NEXT: lwsync 8934 ; PPC64LE-NEXT: blr 8935 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") seq_cst 8936 ret i8 %ret 8937 } 8938 8939 define i16 @test525(i16* %ptr, i16 %val) { 8940 ; PPC64LE-LABEL: test525: 8941 ; PPC64LE: # %bb.0: 8942 ; PPC64LE-NEXT: .LBB525_1: 8943 ; PPC64LE-NEXT: lharx 5, 0, 3 8944 ; PPC64LE-NEXT: cmplw 4, 5 8945 ; PPC64LE-NEXT: ble 0, .LBB525_3 8946 ; PPC64LE-NEXT: # %bb.2: 8947 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8948 ; PPC64LE-NEXT: bne 0, .LBB525_1 8949 ; PPC64LE-NEXT: .LBB525_3: 8950 ; PPC64LE-NEXT: mr 3, 5 8951 ; PPC64LE-NEXT: blr 8952 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") monotonic 8953 ret i16 %ret 8954 } 8955 8956 define i16 @test526(i16* %ptr, i16 %val) { 8957 ; PPC64LE-LABEL: test526: 8958 ; PPC64LE: # %bb.0: 8959 ; PPC64LE-NEXT: mr 5, 3 8960 ; PPC64LE-NEXT: .LBB526_1: 8961 ; PPC64LE-NEXT: lharx 3, 0, 5 8962 ; PPC64LE-NEXT: cmplw 4, 3 8963 ; PPC64LE-NEXT: ble 0, .LBB526_3 8964 ; PPC64LE-NEXT: # %bb.2: 8965 ; PPC64LE-NEXT: sthcx. 4, 0, 5 8966 ; PPC64LE-NEXT: bne 0, .LBB526_1 8967 ; PPC64LE-NEXT: .LBB526_3: 8968 ; PPC64LE-NEXT: lwsync 8969 ; PPC64LE-NEXT: blr 8970 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acquire 8971 ret i16 %ret 8972 } 8973 8974 define i16 @test527(i16* %ptr, i16 %val) { 8975 ; PPC64LE-LABEL: test527: 8976 ; PPC64LE: # %bb.0: 8977 ; PPC64LE-NEXT: lwsync 8978 ; PPC64LE-NEXT: .LBB527_1: 8979 ; PPC64LE-NEXT: lharx 5, 0, 3 8980 ; PPC64LE-NEXT: cmplw 4, 5 8981 ; PPC64LE-NEXT: ble 0, .LBB527_3 8982 ; PPC64LE-NEXT: # %bb.2: 8983 ; PPC64LE-NEXT: sthcx. 4, 0, 3 8984 ; PPC64LE-NEXT: bne 0, .LBB527_1 8985 ; PPC64LE-NEXT: .LBB527_3: 8986 ; PPC64LE-NEXT: mr 3, 5 8987 ; PPC64LE-NEXT: blr 8988 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") release 8989 ret i16 %ret 8990 } 8991 8992 define i16 @test528(i16* %ptr, i16 %val) { 8993 ; PPC64LE-LABEL: test528: 8994 ; PPC64LE: # %bb.0: 8995 ; PPC64LE-NEXT: lwsync 8996 ; PPC64LE-NEXT: .LBB528_1: 8997 ; PPC64LE-NEXT: lharx 5, 0, 3 8998 ; PPC64LE-NEXT: cmplw 4, 5 8999 ; PPC64LE-NEXT: ble 0, .LBB528_3 9000 ; PPC64LE-NEXT: # %bb.2: 9001 ; PPC64LE-NEXT: sthcx. 4, 0, 3 9002 ; PPC64LE-NEXT: bne 0, .LBB528_1 9003 ; PPC64LE-NEXT: .LBB528_3: 9004 ; PPC64LE-NEXT: mr 3, 5 9005 ; PPC64LE-NEXT: lwsync 9006 ; PPC64LE-NEXT: blr 9007 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acq_rel 9008 ret i16 %ret 9009 } 9010 9011 define i16 @test529(i16* %ptr, i16 %val) { 9012 ; PPC64LE-LABEL: test529: 9013 ; PPC64LE: # %bb.0: 9014 ; PPC64LE-NEXT: sync 9015 ; PPC64LE-NEXT: .LBB529_1: 9016 ; PPC64LE-NEXT: lharx 5, 0, 3 9017 ; PPC64LE-NEXT: cmplw 4, 5 9018 ; PPC64LE-NEXT: ble 0, .LBB529_3 9019 ; PPC64LE-NEXT: # %bb.2: 9020 ; PPC64LE-NEXT: sthcx. 4, 0, 3 9021 ; PPC64LE-NEXT: bne 0, .LBB529_1 9022 ; PPC64LE-NEXT: .LBB529_3: 9023 ; PPC64LE-NEXT: mr 3, 5 9024 ; PPC64LE-NEXT: lwsync 9025 ; PPC64LE-NEXT: blr 9026 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") seq_cst 9027 ret i16 %ret 9028 } 9029 9030 define i32 @test530(i32* %ptr, i32 %val) { 9031 ; PPC64LE-LABEL: test530: 9032 ; PPC64LE: # %bb.0: 9033 ; PPC64LE-NEXT: .LBB530_1: 9034 ; PPC64LE-NEXT: lwarx 5, 0, 3 9035 ; PPC64LE-NEXT: cmplw 4, 5 9036 ; PPC64LE-NEXT: ble 0, .LBB530_3 9037 ; PPC64LE-NEXT: # %bb.2: 9038 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9039 ; PPC64LE-NEXT: bne 0, .LBB530_1 9040 ; PPC64LE-NEXT: .LBB530_3: 9041 ; PPC64LE-NEXT: mr 3, 5 9042 ; PPC64LE-NEXT: blr 9043 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") monotonic 9044 ret i32 %ret 9045 } 9046 9047 define i32 @test531(i32* %ptr, i32 %val) { 9048 ; PPC64LE-LABEL: test531: 9049 ; PPC64LE: # %bb.0: 9050 ; PPC64LE-NEXT: mr 5, 3 9051 ; PPC64LE-NEXT: .LBB531_1: 9052 ; PPC64LE-NEXT: lwarx 3, 0, 5 9053 ; PPC64LE-NEXT: cmplw 4, 3 9054 ; PPC64LE-NEXT: ble 0, .LBB531_3 9055 ; PPC64LE-NEXT: # %bb.2: 9056 ; PPC64LE-NEXT: stwcx. 4, 0, 5 9057 ; PPC64LE-NEXT: bne 0, .LBB531_1 9058 ; PPC64LE-NEXT: .LBB531_3: 9059 ; PPC64LE-NEXT: lwsync 9060 ; PPC64LE-NEXT: blr 9061 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acquire 9062 ret i32 %ret 9063 } 9064 9065 define i32 @test532(i32* %ptr, i32 %val) { 9066 ; PPC64LE-LABEL: test532: 9067 ; PPC64LE: # %bb.0: 9068 ; PPC64LE-NEXT: lwsync 9069 ; PPC64LE-NEXT: .LBB532_1: 9070 ; PPC64LE-NEXT: lwarx 5, 0, 3 9071 ; PPC64LE-NEXT: cmplw 4, 5 9072 ; PPC64LE-NEXT: ble 0, .LBB532_3 9073 ; PPC64LE-NEXT: # %bb.2: 9074 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9075 ; PPC64LE-NEXT: bne 0, .LBB532_1 9076 ; PPC64LE-NEXT: .LBB532_3: 9077 ; PPC64LE-NEXT: mr 3, 5 9078 ; PPC64LE-NEXT: blr 9079 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") release 9080 ret i32 %ret 9081 } 9082 9083 define i32 @test533(i32* %ptr, i32 %val) { 9084 ; PPC64LE-LABEL: test533: 9085 ; PPC64LE: # %bb.0: 9086 ; PPC64LE-NEXT: lwsync 9087 ; PPC64LE-NEXT: .LBB533_1: 9088 ; PPC64LE-NEXT: lwarx 5, 0, 3 9089 ; PPC64LE-NEXT: cmplw 4, 5 9090 ; PPC64LE-NEXT: ble 0, .LBB533_3 9091 ; PPC64LE-NEXT: # %bb.2: 9092 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9093 ; PPC64LE-NEXT: bne 0, .LBB533_1 9094 ; PPC64LE-NEXT: .LBB533_3: 9095 ; PPC64LE-NEXT: mr 3, 5 9096 ; PPC64LE-NEXT: lwsync 9097 ; PPC64LE-NEXT: blr 9098 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acq_rel 9099 ret i32 %ret 9100 } 9101 9102 define i32 @test534(i32* %ptr, i32 %val) { 9103 ; PPC64LE-LABEL: test534: 9104 ; PPC64LE: # %bb.0: 9105 ; PPC64LE-NEXT: sync 9106 ; PPC64LE-NEXT: .LBB534_1: 9107 ; PPC64LE-NEXT: lwarx 5, 0, 3 9108 ; PPC64LE-NEXT: cmplw 4, 5 9109 ; PPC64LE-NEXT: ble 0, .LBB534_3 9110 ; PPC64LE-NEXT: # %bb.2: 9111 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9112 ; PPC64LE-NEXT: bne 0, .LBB534_1 9113 ; PPC64LE-NEXT: .LBB534_3: 9114 ; PPC64LE-NEXT: mr 3, 5 9115 ; PPC64LE-NEXT: lwsync 9116 ; PPC64LE-NEXT: blr 9117 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") seq_cst 9118 ret i32 %ret 9119 } 9120 9121 define i64 @test535(i64* %ptr, i64 %val) { 9122 ; PPC64LE-LABEL: test535: 9123 ; PPC64LE: # %bb.0: 9124 ; PPC64LE-NEXT: .LBB535_1: 9125 ; PPC64LE-NEXT: ldarx 5, 0, 3 9126 ; PPC64LE-NEXT: cmpld 4, 5 9127 ; PPC64LE-NEXT: ble 0, .LBB535_3 9128 ; PPC64LE-NEXT: # %bb.2: 9129 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9130 ; PPC64LE-NEXT: bne 0, .LBB535_1 9131 ; PPC64LE-NEXT: .LBB535_3: 9132 ; PPC64LE-NEXT: mr 3, 5 9133 ; PPC64LE-NEXT: blr 9134 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") monotonic 9135 ret i64 %ret 9136 } 9137 9138 define i64 @test536(i64* %ptr, i64 %val) { 9139 ; PPC64LE-LABEL: test536: 9140 ; PPC64LE: # %bb.0: 9141 ; PPC64LE-NEXT: mr 5, 3 9142 ; PPC64LE-NEXT: .LBB536_1: 9143 ; PPC64LE-NEXT: ldarx 3, 0, 5 9144 ; PPC64LE-NEXT: cmpld 4, 3 9145 ; PPC64LE-NEXT: ble 0, .LBB536_3 9146 ; PPC64LE-NEXT: # %bb.2: 9147 ; PPC64LE-NEXT: stdcx. 4, 0, 5 9148 ; PPC64LE-NEXT: bne 0, .LBB536_1 9149 ; PPC64LE-NEXT: .LBB536_3: 9150 ; PPC64LE-NEXT: lwsync 9151 ; PPC64LE-NEXT: blr 9152 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acquire 9153 ret i64 %ret 9154 } 9155 9156 define i64 @test537(i64* %ptr, i64 %val) { 9157 ; PPC64LE-LABEL: test537: 9158 ; PPC64LE: # %bb.0: 9159 ; PPC64LE-NEXT: lwsync 9160 ; PPC64LE-NEXT: .LBB537_1: 9161 ; PPC64LE-NEXT: ldarx 5, 0, 3 9162 ; PPC64LE-NEXT: cmpld 4, 5 9163 ; PPC64LE-NEXT: ble 0, .LBB537_3 9164 ; PPC64LE-NEXT: # %bb.2: 9165 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9166 ; PPC64LE-NEXT: bne 0, .LBB537_1 9167 ; PPC64LE-NEXT: .LBB537_3: 9168 ; PPC64LE-NEXT: mr 3, 5 9169 ; PPC64LE-NEXT: blr 9170 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") release 9171 ret i64 %ret 9172 } 9173 9174 define i64 @test538(i64* %ptr, i64 %val) { 9175 ; PPC64LE-LABEL: test538: 9176 ; PPC64LE: # %bb.0: 9177 ; PPC64LE-NEXT: lwsync 9178 ; PPC64LE-NEXT: .LBB538_1: 9179 ; PPC64LE-NEXT: ldarx 5, 0, 3 9180 ; PPC64LE-NEXT: cmpld 4, 5 9181 ; PPC64LE-NEXT: ble 0, .LBB538_3 9182 ; PPC64LE-NEXT: # %bb.2: 9183 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9184 ; PPC64LE-NEXT: bne 0, .LBB538_1 9185 ; PPC64LE-NEXT: .LBB538_3: 9186 ; PPC64LE-NEXT: mr 3, 5 9187 ; PPC64LE-NEXT: lwsync 9188 ; PPC64LE-NEXT: blr 9189 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acq_rel 9190 ret i64 %ret 9191 } 9192 9193 define i64 @test539(i64* %ptr, i64 %val) { 9194 ; PPC64LE-LABEL: test539: 9195 ; PPC64LE: # %bb.0: 9196 ; PPC64LE-NEXT: sync 9197 ; PPC64LE-NEXT: .LBB539_1: 9198 ; PPC64LE-NEXT: ldarx 5, 0, 3 9199 ; PPC64LE-NEXT: cmpld 4, 5 9200 ; PPC64LE-NEXT: ble 0, .LBB539_3 9201 ; PPC64LE-NEXT: # %bb.2: 9202 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9203 ; PPC64LE-NEXT: bne 0, .LBB539_1 9204 ; PPC64LE-NEXT: .LBB539_3: 9205 ; PPC64LE-NEXT: mr 3, 5 9206 ; PPC64LE-NEXT: lwsync 9207 ; PPC64LE-NEXT: blr 9208 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") seq_cst 9209 ret i64 %ret 9210 } 9211 9212 define i8 @test540(i8* %ptr, i8 %val) { 9213 ; PPC64LE-LABEL: test540: 9214 ; PPC64LE: # %bb.0: 9215 ; PPC64LE-NEXT: .LBB540_1: 9216 ; PPC64LE-NEXT: lbarx 5, 0, 3 9217 ; PPC64LE-NEXT: cmplw 4, 5 9218 ; PPC64LE-NEXT: bge 0, .LBB540_3 9219 ; PPC64LE-NEXT: # %bb.2: 9220 ; PPC64LE-NEXT: stbcx. 4, 0, 3 9221 ; PPC64LE-NEXT: bne 0, .LBB540_1 9222 ; PPC64LE-NEXT: .LBB540_3: 9223 ; PPC64LE-NEXT: mr 3, 5 9224 ; PPC64LE-NEXT: blr 9225 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") monotonic 9226 ret i8 %ret 9227 } 9228 9229 define i8 @test541(i8* %ptr, i8 %val) { 9230 ; PPC64LE-LABEL: test541: 9231 ; PPC64LE: # %bb.0: 9232 ; PPC64LE-NEXT: mr 5, 3 9233 ; PPC64LE-NEXT: .LBB541_1: 9234 ; PPC64LE-NEXT: lbarx 3, 0, 5 9235 ; PPC64LE-NEXT: cmplw 4, 3 9236 ; PPC64LE-NEXT: bge 0, .LBB541_3 9237 ; PPC64LE-NEXT: # %bb.2: 9238 ; PPC64LE-NEXT: stbcx. 4, 0, 5 9239 ; PPC64LE-NEXT: bne 0, .LBB541_1 9240 ; PPC64LE-NEXT: .LBB541_3: 9241 ; PPC64LE-NEXT: lwsync 9242 ; PPC64LE-NEXT: blr 9243 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acquire 9244 ret i8 %ret 9245 } 9246 9247 define i8 @test542(i8* %ptr, i8 %val) { 9248 ; PPC64LE-LABEL: test542: 9249 ; PPC64LE: # %bb.0: 9250 ; PPC64LE-NEXT: lwsync 9251 ; PPC64LE-NEXT: .LBB542_1: 9252 ; PPC64LE-NEXT: lbarx 5, 0, 3 9253 ; PPC64LE-NEXT: cmplw 4, 5 9254 ; PPC64LE-NEXT: bge 0, .LBB542_3 9255 ; PPC64LE-NEXT: # %bb.2: 9256 ; PPC64LE-NEXT: stbcx. 4, 0, 3 9257 ; PPC64LE-NEXT: bne 0, .LBB542_1 9258 ; PPC64LE-NEXT: .LBB542_3: 9259 ; PPC64LE-NEXT: mr 3, 5 9260 ; PPC64LE-NEXT: blr 9261 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") release 9262 ret i8 %ret 9263 } 9264 9265 define i8 @test543(i8* %ptr, i8 %val) { 9266 ; PPC64LE-LABEL: test543: 9267 ; PPC64LE: # %bb.0: 9268 ; PPC64LE-NEXT: lwsync 9269 ; PPC64LE-NEXT: .LBB543_1: 9270 ; PPC64LE-NEXT: lbarx 5, 0, 3 9271 ; PPC64LE-NEXT: cmplw 4, 5 9272 ; PPC64LE-NEXT: bge 0, .LBB543_3 9273 ; PPC64LE-NEXT: # %bb.2: 9274 ; PPC64LE-NEXT: stbcx. 4, 0, 3 9275 ; PPC64LE-NEXT: bne 0, .LBB543_1 9276 ; PPC64LE-NEXT: .LBB543_3: 9277 ; PPC64LE-NEXT: mr 3, 5 9278 ; PPC64LE-NEXT: lwsync 9279 ; PPC64LE-NEXT: blr 9280 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acq_rel 9281 ret i8 %ret 9282 } 9283 9284 define i8 @test544(i8* %ptr, i8 %val) { 9285 ; PPC64LE-LABEL: test544: 9286 ; PPC64LE: # %bb.0: 9287 ; PPC64LE-NEXT: sync 9288 ; PPC64LE-NEXT: .LBB544_1: 9289 ; PPC64LE-NEXT: lbarx 5, 0, 3 9290 ; PPC64LE-NEXT: cmplw 4, 5 9291 ; PPC64LE-NEXT: bge 0, .LBB544_3 9292 ; PPC64LE-NEXT: # %bb.2: 9293 ; PPC64LE-NEXT: stbcx. 4, 0, 3 9294 ; PPC64LE-NEXT: bne 0, .LBB544_1 9295 ; PPC64LE-NEXT: .LBB544_3: 9296 ; PPC64LE-NEXT: mr 3, 5 9297 ; PPC64LE-NEXT: lwsync 9298 ; PPC64LE-NEXT: blr 9299 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") seq_cst 9300 ret i8 %ret 9301 } 9302 9303 define i16 @test545(i16* %ptr, i16 %val) { 9304 ; PPC64LE-LABEL: test545: 9305 ; PPC64LE: # %bb.0: 9306 ; PPC64LE-NEXT: .LBB545_1: 9307 ; PPC64LE-NEXT: lharx 5, 0, 3 9308 ; PPC64LE-NEXT: cmplw 4, 5 9309 ; PPC64LE-NEXT: bge 0, .LBB545_3 9310 ; PPC64LE-NEXT: # %bb.2: 9311 ; PPC64LE-NEXT: sthcx. 4, 0, 3 9312 ; PPC64LE-NEXT: bne 0, .LBB545_1 9313 ; PPC64LE-NEXT: .LBB545_3: 9314 ; PPC64LE-NEXT: mr 3, 5 9315 ; PPC64LE-NEXT: blr 9316 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") monotonic 9317 ret i16 %ret 9318 } 9319 9320 define i16 @test546(i16* %ptr, i16 %val) { 9321 ; PPC64LE-LABEL: test546: 9322 ; PPC64LE: # %bb.0: 9323 ; PPC64LE-NEXT: mr 5, 3 9324 ; PPC64LE-NEXT: .LBB546_1: 9325 ; PPC64LE-NEXT: lharx 3, 0, 5 9326 ; PPC64LE-NEXT: cmplw 4, 3 9327 ; PPC64LE-NEXT: bge 0, .LBB546_3 9328 ; PPC64LE-NEXT: # %bb.2: 9329 ; PPC64LE-NEXT: sthcx. 4, 0, 5 9330 ; PPC64LE-NEXT: bne 0, .LBB546_1 9331 ; PPC64LE-NEXT: .LBB546_3: 9332 ; PPC64LE-NEXT: lwsync 9333 ; PPC64LE-NEXT: blr 9334 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acquire 9335 ret i16 %ret 9336 } 9337 9338 define i16 @test547(i16* %ptr, i16 %val) { 9339 ; PPC64LE-LABEL: test547: 9340 ; PPC64LE: # %bb.0: 9341 ; PPC64LE-NEXT: lwsync 9342 ; PPC64LE-NEXT: .LBB547_1: 9343 ; PPC64LE-NEXT: lharx 5, 0, 3 9344 ; PPC64LE-NEXT: cmplw 4, 5 9345 ; PPC64LE-NEXT: bge 0, .LBB547_3 9346 ; PPC64LE-NEXT: # %bb.2: 9347 ; PPC64LE-NEXT: sthcx. 4, 0, 3 9348 ; PPC64LE-NEXT: bne 0, .LBB547_1 9349 ; PPC64LE-NEXT: .LBB547_3: 9350 ; PPC64LE-NEXT: mr 3, 5 9351 ; PPC64LE-NEXT: blr 9352 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") release 9353 ret i16 %ret 9354 } 9355 9356 define i16 @test548(i16* %ptr, i16 %val) { 9357 ; PPC64LE-LABEL: test548: 9358 ; PPC64LE: # %bb.0: 9359 ; PPC64LE-NEXT: lwsync 9360 ; PPC64LE-NEXT: .LBB548_1: 9361 ; PPC64LE-NEXT: lharx 5, 0, 3 9362 ; PPC64LE-NEXT: cmplw 4, 5 9363 ; PPC64LE-NEXT: bge 0, .LBB548_3 9364 ; PPC64LE-NEXT: # %bb.2: 9365 ; PPC64LE-NEXT: sthcx. 4, 0, 3 9366 ; PPC64LE-NEXT: bne 0, .LBB548_1 9367 ; PPC64LE-NEXT: .LBB548_3: 9368 ; PPC64LE-NEXT: mr 3, 5 9369 ; PPC64LE-NEXT: lwsync 9370 ; PPC64LE-NEXT: blr 9371 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acq_rel 9372 ret i16 %ret 9373 } 9374 9375 define i16 @test549(i16* %ptr, i16 %val) { 9376 ; PPC64LE-LABEL: test549: 9377 ; PPC64LE: # %bb.0: 9378 ; PPC64LE-NEXT: sync 9379 ; PPC64LE-NEXT: .LBB549_1: 9380 ; PPC64LE-NEXT: lharx 5, 0, 3 9381 ; PPC64LE-NEXT: cmplw 4, 5 9382 ; PPC64LE-NEXT: bge 0, .LBB549_3 9383 ; PPC64LE-NEXT: # %bb.2: 9384 ; PPC64LE-NEXT: sthcx. 4, 0, 3 9385 ; PPC64LE-NEXT: bne 0, .LBB549_1 9386 ; PPC64LE-NEXT: .LBB549_3: 9387 ; PPC64LE-NEXT: mr 3, 5 9388 ; PPC64LE-NEXT: lwsync 9389 ; PPC64LE-NEXT: blr 9390 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") seq_cst 9391 ret i16 %ret 9392 } 9393 9394 define i32 @test550(i32* %ptr, i32 %val) { 9395 ; PPC64LE-LABEL: test550: 9396 ; PPC64LE: # %bb.0: 9397 ; PPC64LE-NEXT: .LBB550_1: 9398 ; PPC64LE-NEXT: lwarx 5, 0, 3 9399 ; PPC64LE-NEXT: cmplw 4, 5 9400 ; PPC64LE-NEXT: bge 0, .LBB550_3 9401 ; PPC64LE-NEXT: # %bb.2: 9402 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9403 ; PPC64LE-NEXT: bne 0, .LBB550_1 9404 ; PPC64LE-NEXT: .LBB550_3: 9405 ; PPC64LE-NEXT: mr 3, 5 9406 ; PPC64LE-NEXT: blr 9407 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") monotonic 9408 ret i32 %ret 9409 } 9410 9411 define i32 @test551(i32* %ptr, i32 %val) { 9412 ; PPC64LE-LABEL: test551: 9413 ; PPC64LE: # %bb.0: 9414 ; PPC64LE-NEXT: mr 5, 3 9415 ; PPC64LE-NEXT: .LBB551_1: 9416 ; PPC64LE-NEXT: lwarx 3, 0, 5 9417 ; PPC64LE-NEXT: cmplw 4, 3 9418 ; PPC64LE-NEXT: bge 0, .LBB551_3 9419 ; PPC64LE-NEXT: # %bb.2: 9420 ; PPC64LE-NEXT: stwcx. 4, 0, 5 9421 ; PPC64LE-NEXT: bne 0, .LBB551_1 9422 ; PPC64LE-NEXT: .LBB551_3: 9423 ; PPC64LE-NEXT: lwsync 9424 ; PPC64LE-NEXT: blr 9425 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acquire 9426 ret i32 %ret 9427 } 9428 9429 define i32 @test552(i32* %ptr, i32 %val) { 9430 ; PPC64LE-LABEL: test552: 9431 ; PPC64LE: # %bb.0: 9432 ; PPC64LE-NEXT: lwsync 9433 ; PPC64LE-NEXT: .LBB552_1: 9434 ; PPC64LE-NEXT: lwarx 5, 0, 3 9435 ; PPC64LE-NEXT: cmplw 4, 5 9436 ; PPC64LE-NEXT: bge 0, .LBB552_3 9437 ; PPC64LE-NEXT: # %bb.2: 9438 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9439 ; PPC64LE-NEXT: bne 0, .LBB552_1 9440 ; PPC64LE-NEXT: .LBB552_3: 9441 ; PPC64LE-NEXT: mr 3, 5 9442 ; PPC64LE-NEXT: blr 9443 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") release 9444 ret i32 %ret 9445 } 9446 9447 define i32 @test553(i32* %ptr, i32 %val) { 9448 ; PPC64LE-LABEL: test553: 9449 ; PPC64LE: # %bb.0: 9450 ; PPC64LE-NEXT: lwsync 9451 ; PPC64LE-NEXT: .LBB553_1: 9452 ; PPC64LE-NEXT: lwarx 5, 0, 3 9453 ; PPC64LE-NEXT: cmplw 4, 5 9454 ; PPC64LE-NEXT: bge 0, .LBB553_3 9455 ; PPC64LE-NEXT: # %bb.2: 9456 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9457 ; PPC64LE-NEXT: bne 0, .LBB553_1 9458 ; PPC64LE-NEXT: .LBB553_3: 9459 ; PPC64LE-NEXT: mr 3, 5 9460 ; PPC64LE-NEXT: lwsync 9461 ; PPC64LE-NEXT: blr 9462 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acq_rel 9463 ret i32 %ret 9464 } 9465 9466 define i32 @test554(i32* %ptr, i32 %val) { 9467 ; PPC64LE-LABEL: test554: 9468 ; PPC64LE: # %bb.0: 9469 ; PPC64LE-NEXT: sync 9470 ; PPC64LE-NEXT: .LBB554_1: 9471 ; PPC64LE-NEXT: lwarx 5, 0, 3 9472 ; PPC64LE-NEXT: cmplw 4, 5 9473 ; PPC64LE-NEXT: bge 0, .LBB554_3 9474 ; PPC64LE-NEXT: # %bb.2: 9475 ; PPC64LE-NEXT: stwcx. 4, 0, 3 9476 ; PPC64LE-NEXT: bne 0, .LBB554_1 9477 ; PPC64LE-NEXT: .LBB554_3: 9478 ; PPC64LE-NEXT: mr 3, 5 9479 ; PPC64LE-NEXT: lwsync 9480 ; PPC64LE-NEXT: blr 9481 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") seq_cst 9482 ret i32 %ret 9483 } 9484 9485 define i64 @test555(i64* %ptr, i64 %val) { 9486 ; PPC64LE-LABEL: test555: 9487 ; PPC64LE: # %bb.0: 9488 ; PPC64LE-NEXT: .LBB555_1: 9489 ; PPC64LE-NEXT: ldarx 5, 0, 3 9490 ; PPC64LE-NEXT: cmpld 4, 5 9491 ; PPC64LE-NEXT: bge 0, .LBB555_3 9492 ; PPC64LE-NEXT: # %bb.2: 9493 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9494 ; PPC64LE-NEXT: bne 0, .LBB555_1 9495 ; PPC64LE-NEXT: .LBB555_3: 9496 ; PPC64LE-NEXT: mr 3, 5 9497 ; PPC64LE-NEXT: blr 9498 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") monotonic 9499 ret i64 %ret 9500 } 9501 9502 define i64 @test556(i64* %ptr, i64 %val) { 9503 ; PPC64LE-LABEL: test556: 9504 ; PPC64LE: # %bb.0: 9505 ; PPC64LE-NEXT: mr 5, 3 9506 ; PPC64LE-NEXT: .LBB556_1: 9507 ; PPC64LE-NEXT: ldarx 3, 0, 5 9508 ; PPC64LE-NEXT: cmpld 4, 3 9509 ; PPC64LE-NEXT: bge 0, .LBB556_3 9510 ; PPC64LE-NEXT: # %bb.2: 9511 ; PPC64LE-NEXT: stdcx. 4, 0, 5 9512 ; PPC64LE-NEXT: bne 0, .LBB556_1 9513 ; PPC64LE-NEXT: .LBB556_3: 9514 ; PPC64LE-NEXT: lwsync 9515 ; PPC64LE-NEXT: blr 9516 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acquire 9517 ret i64 %ret 9518 } 9519 9520 define i64 @test557(i64* %ptr, i64 %val) { 9521 ; PPC64LE-LABEL: test557: 9522 ; PPC64LE: # %bb.0: 9523 ; PPC64LE-NEXT: lwsync 9524 ; PPC64LE-NEXT: .LBB557_1: 9525 ; PPC64LE-NEXT: ldarx 5, 0, 3 9526 ; PPC64LE-NEXT: cmpld 4, 5 9527 ; PPC64LE-NEXT: bge 0, .LBB557_3 9528 ; PPC64LE-NEXT: # %bb.2: 9529 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9530 ; PPC64LE-NEXT: bne 0, .LBB557_1 9531 ; PPC64LE-NEXT: .LBB557_3: 9532 ; PPC64LE-NEXT: mr 3, 5 9533 ; PPC64LE-NEXT: blr 9534 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") release 9535 ret i64 %ret 9536 } 9537 9538 define i64 @test558(i64* %ptr, i64 %val) { 9539 ; PPC64LE-LABEL: test558: 9540 ; PPC64LE: # %bb.0: 9541 ; PPC64LE-NEXT: lwsync 9542 ; PPC64LE-NEXT: .LBB558_1: 9543 ; PPC64LE-NEXT: ldarx 5, 0, 3 9544 ; PPC64LE-NEXT: cmpld 4, 5 9545 ; PPC64LE-NEXT: bge 0, .LBB558_3 9546 ; PPC64LE-NEXT: # %bb.2: 9547 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9548 ; PPC64LE-NEXT: bne 0, .LBB558_1 9549 ; PPC64LE-NEXT: .LBB558_3: 9550 ; PPC64LE-NEXT: mr 3, 5 9551 ; PPC64LE-NEXT: lwsync 9552 ; PPC64LE-NEXT: blr 9553 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acq_rel 9554 ret i64 %ret 9555 } 9556 9557 define i64 @test559(i64* %ptr, i64 %val) { 9558 ; PPC64LE-LABEL: test559: 9559 ; PPC64LE: # %bb.0: 9560 ; PPC64LE-NEXT: sync 9561 ; PPC64LE-NEXT: .LBB559_1: 9562 ; PPC64LE-NEXT: ldarx 5, 0, 3 9563 ; PPC64LE-NEXT: cmpld 4, 5 9564 ; PPC64LE-NEXT: bge 0, .LBB559_3 9565 ; PPC64LE-NEXT: # %bb.2: 9566 ; PPC64LE-NEXT: stdcx. 4, 0, 3 9567 ; PPC64LE-NEXT: bne 0, .LBB559_1 9568 ; PPC64LE-NEXT: .LBB559_3: 9569 ; PPC64LE-NEXT: mr 3, 5 9570 ; PPC64LE-NEXT: lwsync 9571 ; PPC64LE-NEXT: blr 9572 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") seq_cst 9573 ret i64 %ret 9574 } 9575 9576 ; The second load should never be scheduled before isync. 9577 define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { 9578 ; PPC64LE-LABEL: test_ordering0: 9579 ; PPC64LE: # %bb.0: 9580 ; PPC64LE-NEXT: lwz 4, 0(3) 9581 ; PPC64LE-NEXT: cmpd 7, 4, 4 9582 ; PPC64LE-NEXT: bne- 7, .+4 9583 ; PPC64LE-NEXT: isync 9584 ; PPC64LE-NEXT: lwz 3, 0(3) 9585 ; PPC64LE-NEXT: add 3, 4, 3 9586 ; PPC64LE-NEXT: blr 9587 %val1 = load atomic i32, i32* %ptr1 acquire, align 4 9588 %val2 = load i32, i32* %ptr1 9589 %add = add i32 %val1, %val2 9590 ret i32 %add 9591 } 9592 9593 ; The second store should never be scheduled before isync. 9594 define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) { 9595 ; PPC64LE-LABEL: test_ordering1: 9596 ; PPC64LE: # %bb.0: 9597 ; PPC64LE-NEXT: lwz 3, 0(3) 9598 ; PPC64LE-NEXT: cmpd 7, 3, 3 9599 ; PPC64LE-NEXT: bne- 7, .+4 9600 ; PPC64LE-NEXT: isync 9601 ; PPC64LE-NEXT: stw 4, 0(5) 9602 ; PPC64LE-NEXT: blr 9603 %val2 = load atomic i32, i32* %ptr1 acquire, align 4 9604 store i32 %val1, i32* %ptr2 9605 ret i32 %val2 9606 } 9607