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      1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
      2 ; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
      3 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false  < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
      4 ; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
      5 
      6 target datalayout = "E-m:e-i64:64-n32:64"
      7 target triple = "powerpc64-unknown-linux-gnu"
      8 
      9 define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
     10 entry:
     11   %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
     12   %1 = and i8 %0, 1
     13   %tobool3 = icmp ne i8 %1, 0
     14   ret i1 %tobool3
     15 
     16 ; CHECK-LABEL: @testi1
     17 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
     18 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
     19 ; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
     20 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
     21 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
     22 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
     23 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
     24 ; CHECK-NO-ISEL-LABEL: @testi1
     25 ; CHECK-NO-ISEL: bclr 12, 20, 0
     26 ; CHECK-NO-ISEL: ori 3, 5, 0
     27 ; CHECK-NO-ISEL-NEXT: blr
     28 ; CHECK: blr
     29 }
     30 
     31 define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
     32 entry:
     33   %0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
     34   ret i32 %0
     35 
     36 ; The ABI sign_extend should combine with the any_extend from the asm result,
     37 ; and the result will be 0 or -1. This highlights the fact that only the first
     38 ; bit is meaningful.
     39 ; CHECK-LABEL: @testi32
     40 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
     41 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
     42 ; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
     43 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
     44 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
     45 ; CHECK-DAG: li [[REG4:[0-9]+]], -1
     46 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
     47 ; CHECK: blr
     48 }
     49 
     50 define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
     51 entry:
     52   %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
     53   ret i8 %0
     54 
     55 ; CHECK-LABEL: @testi8
     56 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
     57 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
     58 ; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
     59 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
     60 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
     61 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
     62 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
     63 ; CHECK: blr
     64 }
     65 
     66 attributes #0 = { nounwind "target-features"="+crbits" }
     67 
     68