1 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s 2 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s 3 target datalayout = "E-m:e-i64:64-n32:64" 4 target triple = "powerpc64-unknown-linux-gnu" 5 6 ; Function Attrs: nounwind readnone 7 define zeroext i1 @test1(float %v1, float %v2) #0 { 8 entry: 9 %cmp = fcmp oge float %v1, %v2 10 %cmp2 = fcmp ole float %v2, 0.000000e+00 11 %and5 = and i1 %cmp, %cmp2 12 ret i1 %and5 13 14 ; CHECK-LABEL: @test1 15 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 16 ; CHECK-DAG: li [[REG1:[0-9]+]], 1 17 ; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]] 18 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 19 ; CHECK: crnor 20 ; CHECK: crnor 21 ; CHECK: crnand [[REG4:[0-9]+]], 22 ; CHECK: isel 3, 0, [[REG1]], [[REG4]] 23 ; CHECK-NO-ISEL-LABEL: @test1 24 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 25 ; CHECK-NO-ISEL-NEXT: blr 26 ; CHECK-NO-ISEL-NEXT: [[TRUE]] 27 ; CHECK-NO-ISEL-NEXT: addi 3, 0, 0 28 ; CHECK-NO-ISEL-NEXT: blr 29 ; CHECK: blr 30 } 31 32 ; Function Attrs: nounwind readnone 33 define zeroext i1 @test2(float %v1, float %v2) #0 { 34 entry: 35 %cmp = fcmp oge float %v1, %v2 36 %cmp2 = fcmp ole float %v2, 0.000000e+00 37 %xor5 = xor i1 %cmp, %cmp2 38 ret i1 %xor5 39 40 ; CHECK-LABEL: @test2 41 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 42 ; CHECK-DAG: li [[REG1:[0-9]+]], 1 43 ; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]] 44 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 45 ; CHECK: crnor 46 ; CHECK: crnor 47 ; CHECK: creqv [[REG4:[0-9]+]], 48 ; CHECK: isel 3, 0, [[REG1]], [[REG4]] 49 ; CHECK: blr 50 } 51 52 ; Function Attrs: nounwind readnone 53 define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 { 54 entry: 55 %cmp = fcmp oge float %v1, %v2 56 %cmp2 = fcmp ole float %v2, 0.000000e+00 57 %cmp4 = icmp ne i32 %x, -2 58 %and7 = and i1 %cmp2, %cmp4 59 %xor8 = xor i1 %cmp, %and7 60 ret i1 %xor8 61 62 ; CHECK-LABEL: @test3 63 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 64 ; CHECK-DAG: li [[REG1:[0-9]+]], 1 65 ; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]] 66 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 67 ; CHECK: crnor 68 ; CHECK: crnor 69 ; CHECK: crandc 70 ; CHECK: creqv [[REG4:[0-9]+]], 71 ; CHECK: isel 3, 0, [[REG1]], [[REG4]] 72 ; CHECK: blr 73 } 74 75 ; Function Attrs: nounwind readnone 76 define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 { 77 entry: 78 %and8 = and i1 %v1, %v2 79 %or9 = or i1 %and8, %v3 80 ret i1 %or9 81 82 ; CHECK-DAG: @test4 83 ; CHECK: and [[REG1:[0-9]+]], 3, 4 84 ; CHECK: or 3, [[REG1]], 5 85 ; CHECK: blr 86 } 87 88 ; Function Attrs: nounwind readnone 89 define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { 90 entry: 91 %and6 = and i1 %v1, %v2 92 %cmp = icmp ne i32 %v3, -2 93 %or7 = or i1 %and6, %cmp 94 ret i1 %or7 95 96 ; CHECK-LABEL: @test5 97 ; CHECK-DAG: li [[NEG2:[0-9]+]], -2 98 ; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4 99 ; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]] 100 ; CHECK-DAG: clrldi [[TRUNC:[0-9]+]], [[REG1]], 63 101 ; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]] 102 ; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5 103 ; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1 104 ; CHECK: or 3, [[TRUNC]], [[NE4]] 105 ; CHECK-NEXT: blr 106 } 107 108 ; Function Attrs: nounwind readnone 109 define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { 110 entry: 111 %cmp = icmp ne i32 %v3, -2 112 %or6 = or i1 %cmp, %v2 113 %and7 = and i1 %or6, %v1 114 ret i1 %and7 115 116 ; CHECK-LABEL: @test6 117 ; CHECK-DAG: li [[NEG2:[0-9]+]], -2 118 ; CHECK-DAG: clrldi [[CLR1:[0-9]+]], 4, 63 119 ; CHECK-DAG: clrldi [[CLR2:[0-9]+]], 3, 63 120 ; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]] 121 ; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]] 122 ; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5 123 ; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1 124 ; CHECK: or [[OR:[0-9]+]], [[NE4]], [[CLR1]] 125 ; CHECK: and 3, [[OR]], [[CLR2]] 126 ; CHECK-NEXT: blr 127 } 128 129 ; Function Attrs: nounwind readnone 130 define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 { 131 entry: 132 %cond = select i1 %v2, i32 %i1, i32 %i2 133 ret i32 %cond 134 135 ; CHECK-LABEL: @test7 136 ; CHECK: andi. {{[0-9]+}}, 3, 1 137 ; CHECK: isel 3, 4, 5, 1 138 ; CHECK: blr 139 } 140 141 define signext i32 @exttest7(i32 signext %a) #0 { 142 entry: 143 %cmp = icmp eq i32 %a, 5 144 %cond = select i1 %cmp, i32 7, i32 8 145 ret i32 %cond 146 147 ; CHECK-LABEL: @exttest7 148 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5 149 ; CHECK-DAG: li [[REG1:[0-9]+]], 8 150 ; CHECK-DAG: li [[REG2:[0-9]+]], 7 151 ; CHECK: isel 3, [[REG2]], [[REG1]], 152 ; CHECK-NOT: rldicl 153 ; CHECK: blr 154 } 155 156 define zeroext i32 @exttest8() #0 { 157 entry: 158 %v0 = load i64, i64* undef, align 8 159 %sub = sub i64 80, %v0 160 %div = lshr i64 %sub, 1 161 %conv13 = trunc i64 %div to i32 162 %cmp14 = icmp ugt i32 %conv13, 80 163 %.conv13 = select i1 %cmp14, i32 0, i32 %conv13 164 ret i32 %.conv13 165 ; CHECK-LABEL: @exttest8 166 ; This is a don't-crash test: %conv13 is both one of the possible select output 167 ; values and also an input to the conditional feeding it. 168 } 169 170 ; Function Attrs: nounwind readnone 171 define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 { 172 entry: 173 %cond = select i1 %v2, float %v1, float %v3 174 ret float %cond 175 176 ; CHECK-LABEL: @test8 177 ; CHECK: andi. {{[0-9]+}}, 3, 1 178 ; CHECK: bclr 12, 1, 0 179 ; CHECK: fmr 1, 2 180 ; CHECK: blr 181 } 182 183 ; Function Attrs: nounwind readnone 184 define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 { 185 entry: 186 %tobool = icmp ne i32 %v1, 0 187 %lnot = icmp eq i32 %v2, 0 188 %and3 = and i1 %tobool, %lnot 189 %and = zext i1 %and3 to i32 190 ret i32 %and 191 192 ; CHECK-LABEL: @test10 193 ; CHECK-DAG: cntlzw 3, 3 194 ; CHECK-DAG: cntlzw 4, 4 195 ; CHECK-DAG: srwi 3, 3, 5 196 ; CHECK-DAG: srwi 4, 4, 5 197 ; CHECK: xori 3, 3, 1 198 ; CHECK: and 3, 3, 4 199 ; CHECK-NEXT: blr 200 } 201 202 attributes #0 = { nounwind readnone } 203 204
