1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s 3 4 declare i8 @llvm.fshl.i8(i8, i8, i8) 5 declare i16 @llvm.fshl.i16(i16, i16, i16) 6 declare i32 @llvm.fshl.i32(i32, i32, i32) 7 declare i64 @llvm.fshl.i64(i64, i64, i64) 8 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 9 10 declare i8 @llvm.fshr.i8(i8, i8, i8) 11 declare i16 @llvm.fshr.i16(i16, i16, i16) 12 declare i32 @llvm.fshr.i32(i32, i32, i32) 13 declare i64 @llvm.fshr.i64(i64, i64, i64) 14 declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 15 16 ; When first 2 operands match, it's a rotate. 17 18 define i8 @rotl_i8_const_shift(i8 %x) { 19 ; CHECK-LABEL: rotl_i8_const_shift: 20 ; CHECK: # %bb.0: 21 ; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31 22 ; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28 23 ; CHECK-NEXT: mr 3, 4 24 ; CHECK-NEXT: blr 25 %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3) 26 ret i8 %f 27 } 28 29 define i64 @rotl_i64_const_shift(i64 %x) { 30 ; CHECK-LABEL: rotl_i64_const_shift: 31 ; CHECK: # %bb.0: 32 ; CHECK-NEXT: rotldi 3, 3, 3 33 ; CHECK-NEXT: blr 34 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3) 35 ret i64 %f 36 } 37 38 ; When first 2 operands match, it's a rotate (by variable amount). 39 40 define i16 @rotl_i16(i16 %x, i16 %z) { 41 ; CHECK-LABEL: rotl_i16: 42 ; CHECK: # %bb.0: 43 ; CHECK-NEXT: subfic 5, 4, 16 44 ; CHECK-NEXT: clrlwi 6, 3, 16 45 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 46 ; CHECK-NEXT: clrlwi 5, 5, 28 47 ; CHECK-NEXT: slw 3, 3, 4 48 ; CHECK-NEXT: srw 4, 6, 5 49 ; CHECK-NEXT: or 3, 3, 4 50 ; CHECK-NEXT: blr 51 %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z) 52 ret i16 %f 53 } 54 55 define i32 @rotl_i32(i32 %x, i32 %z) { 56 ; CHECK-LABEL: rotl_i32: 57 ; CHECK: # %bb.0: 58 ; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31 59 ; CHECK-NEXT: blr 60 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z) 61 ret i32 %f 62 } 63 64 define i64 @rotl_i64(i64 %x, i64 %z) { 65 ; CHECK-LABEL: rotl_i64: 66 ; CHECK: # %bb.0: 67 ; CHECK-NEXT: rldcl 3, 3, 4, 0 68 ; CHECK-NEXT: blr 69 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z) 70 ret i64 %f 71 } 72 73 ; Vector rotate. 74 75 define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) { 76 ; CHECK-LABEL: rotl_v4i32: 77 ; CHECK: # %bb.0: 78 ; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha 79 ; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l 80 ; CHECK-NEXT: lvx 4, 0, 3 81 ; CHECK-NEXT: vsubuwm 4, 4, 3 82 ; CHECK-NEXT: vslw 3, 2, 3 83 ; CHECK-NEXT: vsrw 2, 2, 4 84 ; CHECK-NEXT: xxlor 34, 35, 34 85 ; CHECK-NEXT: blr 86 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z) 87 ret <4 x i32> %f 88 } 89 90 ; Vector rotate by constant splat amount. 91 92 define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) { 93 ; CHECK-LABEL: rotl_v4i32_const_shift: 94 ; CHECK: # %bb.0: 95 ; CHECK-NEXT: vspltisw 3, -16 96 ; CHECK-NEXT: vspltisw 4, 13 97 ; CHECK-NEXT: vspltisw 5, 3 98 ; CHECK-NEXT: vsubuwm 3, 4, 3 99 ; CHECK-NEXT: vslw 4, 2, 5 100 ; CHECK-NEXT: vsrw 2, 2, 3 101 ; CHECK-NEXT: xxlor 34, 36, 34 102 ; CHECK-NEXT: blr 103 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) 104 ret <4 x i32> %f 105 } 106 107 ; Repeat everything for funnel shift right. 108 109 define i8 @rotr_i8_const_shift(i8 %x) { 110 ; CHECK-LABEL: rotr_i8_const_shift: 111 ; CHECK: # %bb.0: 112 ; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31 113 ; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26 114 ; CHECK-NEXT: mr 3, 4 115 ; CHECK-NEXT: blr 116 %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3) 117 ret i8 %f 118 } 119 120 define i32 @rotr_i32_const_shift(i32 %x) { 121 ; CHECK-LABEL: rotr_i32_const_shift: 122 ; CHECK: # %bb.0: 123 ; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31 124 ; CHECK-NEXT: blr 125 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3) 126 ret i32 %f 127 } 128 129 ; When first 2 operands match, it's a rotate (by variable amount). 130 131 define i16 @rotr_i16(i16 %x, i16 %z) { 132 ; CHECK-LABEL: rotr_i16: 133 ; CHECK: # %bb.0: 134 ; CHECK-NEXT: subfic 5, 4, 16 135 ; CHECK-NEXT: clrlwi 6, 3, 16 136 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 137 ; CHECK-NEXT: clrlwi 5, 5, 28 138 ; CHECK-NEXT: srw 4, 6, 4 139 ; CHECK-NEXT: slw 3, 3, 5 140 ; CHECK-NEXT: or 3, 3, 4 141 ; CHECK-NEXT: blr 142 %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z) 143 ret i16 %f 144 } 145 146 define i32 @rotr_i32(i32 %x, i32 %z) { 147 ; CHECK-LABEL: rotr_i32: 148 ; CHECK: # %bb.0: 149 ; CHECK-NEXT: subfic 4, 4, 32 150 ; CHECK-NEXT: clrlwi 4, 4, 27 151 ; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31 152 ; CHECK-NEXT: blr 153 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z) 154 ret i32 %f 155 } 156 157 define i64 @rotr_i64(i64 %x, i64 %z) { 158 ; CHECK-LABEL: rotr_i64: 159 ; CHECK: # %bb.0: 160 ; CHECK-NEXT: subfic 4, 4, 64 161 ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 162 ; CHECK-NEXT: rotld 3, 3, 4 163 ; CHECK-NEXT: blr 164 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z) 165 ret i64 %f 166 } 167 168 ; Vector rotate. 169 170 define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) { 171 ; CHECK-LABEL: rotr_v4i32: 172 ; CHECK: # %bb.0: 173 ; CHECK-NEXT: addis 3, 2, .LCPI12_0@toc@ha 174 ; CHECK-NEXT: addi 3, 3, .LCPI12_0@toc@l 175 ; CHECK-NEXT: lvx 4, 0, 3 176 ; CHECK-NEXT: vsubuwm 4, 4, 3 177 ; CHECK-NEXT: vsrw 3, 2, 3 178 ; CHECK-NEXT: vslw 2, 2, 4 179 ; CHECK-NEXT: xxlor 34, 34, 35 180 ; CHECK-NEXT: blr 181 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z) 182 ret <4 x i32> %f 183 } 184 185 ; Vector rotate by constant splat amount. 186 187 define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) { 188 ; CHECK-LABEL: rotr_v4i32_const_shift: 189 ; CHECK: # %bb.0: 190 ; CHECK-NEXT: vspltisw 3, -16 191 ; CHECK-NEXT: vspltisw 4, 13 192 ; CHECK-NEXT: vspltisw 5, 3 193 ; CHECK-NEXT: vsubuwm 3, 4, 3 194 ; CHECK-NEXT: vsrw 4, 2, 5 195 ; CHECK-NEXT: vslw 2, 2, 3 196 ; CHECK-NEXT: xxlor 34, 34, 36 197 ; CHECK-NEXT: blr 198 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>) 199 ret <4 x i32> %f 200 } 201 202 define i32 @rotl_i32_shift_by_bitwidth(i32 %x) { 203 ; CHECK-LABEL: rotl_i32_shift_by_bitwidth: 204 ; CHECK: # %bb.0: 205 ; CHECK-NEXT: blr 206 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32) 207 ret i32 %f 208 } 209 210 define i32 @rotr_i32_shift_by_bitwidth(i32 %x) { 211 ; CHECK-LABEL: rotr_i32_shift_by_bitwidth: 212 ; CHECK: # %bb.0: 213 ; CHECK-NEXT: blr 214 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32) 215 ret i32 %f 216 } 217 218 define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) { 219 ; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth: 220 ; CHECK: # %bb.0: 221 ; CHECK-NEXT: blr 222 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>) 223 ret <4 x i32> %f 224 } 225 226 define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) { 227 ; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth: 228 ; CHECK: # %bb.0: 229 ; CHECK-NEXT: blr 230 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>) 231 ret <4 x i32> %f 232 } 233 234
