1 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr8 \ 2 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s 3 4 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 \ 5 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s \ 6 ; RUN: | FileCheck %s --check-prefix=CHECK-P9 --implicit-check-not xxswapd 7 8 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 -mattr=-power9-vector \ 9 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s 10 11 ; Function Attrs: nounwind 12 define void @test() { 13 entry: 14 %__a.addr.i = alloca i32, align 4 15 %__b.addr.i = alloca <4 x i32>*, align 8 16 %i = alloca <4 x i32>, align 16 17 %j = alloca <4 x i32>, align 16 18 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %i, align 16 19 store i32 0, i32* %__a.addr.i, align 4 20 store <4 x i32>* %i, <4 x i32>** %__b.addr.i, align 8 21 %0 = load i32, i32* %__a.addr.i, align 4 22 %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8 23 %2 = bitcast <4 x i32>* %1 to i8* 24 %3 = getelementptr i8, i8* %2, i32 %0 25 %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3) 26 ; CHECK: lwa [[REG0:[0-9]+]], 27 ; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]] 28 ; CHECK: xxswapd [[REG1]], [[REG1]] 29 ; CHECK-P9: lwa [[REG0:[0-9]+]], 30 ; CHECK-P9: lxvx [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]] 31 store <4 x i32> %4, <4 x i32>* %j, align 16 32 ret void 33 } 34 35 ; Function Attrs: nounwind readonly 36 declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*) 37
