1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \ 2 ; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s 3 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \ 4 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s 5 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \ 6 ; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s 7 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \ 8 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s 9 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=medium \ 10 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s 11 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=large \ 12 ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-P9 %s 13 14 ; Test correct code generation for medium and large code model 15 ; for loading a value from the constant pool (TOC-relative). 16 17 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 18 target triple = "powerpc64-unknown-linux-gnu" 19 20 define double @test_double_const() nounwind { 21 entry: 22 ret double 0x3F4FD4920B498CF0 23 } 24 25 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]: 26 ; MEDIUM: .quad 4562098671269285104 27 ; MEDIUM-LABEL: test_double_const: 28 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha 29 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l 30 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) 31 32 ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: 33 ; MEDIUM-VSX: .quad 4562098671269285104 34 ; MEDIUM-VSX-LABEL: test_double_const: 35 ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha 36 ; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l 37 ; MEDIUM-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] 38 39 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: 40 ; LARGE: .quad 4562098671269285104 41 ; LARGE-LABEL: test_double_const: 42 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha 43 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) 44 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) 45 46 ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]: 47 ; LARGE-VSX: .quad 4562098671269285104 48 ; LARGE-VSX-LABEL: test_double_const: 49 ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha 50 ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) 51 ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] 52 53 ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: 54 ; MEDIUM-P9: .quad 4562098671269285104 55 ; MEDIUM-P9-LABEL: test_double_const: 56 ; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha 57 ; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l 58 ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) 59 60 ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: 61 ; LARGE-P9: .quad 4562098671269285104 62 ; LARGE-P9-LABEL: test_double_const: 63 ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha 64 ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) 65 ; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]]) 66
