1 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 2 ; RUN: -verify-machineinstrs < %s | FileCheck %s 3 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 4 ; RUN: -verify-machineinstrs < %s | FileCheck %s 5 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ 6 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE 7 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ 8 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE 9 10 ; The following testcases take one halfword element from the second vector and 11 ; inserts it at various locations in the first vector 12 define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) { 13 entry: 14 ; CHECK-LABEL: shuffle_vector_halfword_0_8 15 ; CHECK: vsldoi 3, 3, 3, 8 16 ; CHECK: vinserth 2, 3, 14 17 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_8 18 ; CHECK-BE: vsldoi 3, 3, 3, 10 19 ; CHECK-BE: vinserth 2, 3, 0 20 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 21 ret <8 x i16> %vecins 22 } 23 24 define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) { 25 entry: 26 ; CHECK-LABEL: shuffle_vector_halfword_1_15 27 ; CHECK: vsldoi 3, 3, 3, 10 28 ; CHECK: vinserth 2, 3, 12 29 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_15 30 ; CHECK-BE: vsldoi 3, 3, 3, 8 31 ; CHECK-BE: vinserth 2, 3, 2 32 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 33 ret <8 x i16> %vecins 34 } 35 36 define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) { 37 entry: 38 ; CHECK-LABEL: shuffle_vector_halfword_2_9 39 ; CHECK: vsldoi 3, 3, 3, 6 40 ; CHECK: vinserth 2, 3, 10 41 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_9 42 ; CHECK-BE: vsldoi 3, 3, 3, 12 43 ; CHECK-BE: vinserth 2, 3, 4 44 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7> 45 ret <8 x i16> %vecins 46 } 47 48 define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) { 49 entry: 50 ; CHECK-LABEL: shuffle_vector_halfword_3_13 51 ; CHECK: vsldoi 3, 3, 3, 14 52 ; CHECK: vinserth 2, 3, 8 53 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_13 54 ; CHECK-BE: vsldoi 3, 3, 3, 4 55 ; CHECK-BE: vinserth 2, 3, 6 56 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7> 57 ret <8 x i16> %vecins 58 } 59 60 define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) { 61 entry: 62 ; CHECK-LABEL: shuffle_vector_halfword_4_10 63 ; CHECK: vsldoi 3, 3, 3, 4 64 ; CHECK: vinserth 2, 3, 6 65 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_10 66 ; CHECK-BE: vsldoi 3, 3, 3, 14 67 ; CHECK-BE: vinserth 2, 3, 8 68 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7> 69 ret <8 x i16> %vecins 70 } 71 72 define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) { 73 entry: 74 ; CHECK-LABEL: shuffle_vector_halfword_5_14 75 ; CHECK: vsldoi 3, 3, 3, 12 76 ; CHECK: vinserth 2, 3, 4 77 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_14 78 ; CHECK-BE: vsldoi 3, 3, 3, 6 79 ; CHECK-BE: vinserth 2, 3, 10 80 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7> 81 ret <8 x i16> %vecins 82 } 83 84 define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) { 85 entry: 86 ; CHECK-LABEL: shuffle_vector_halfword_6_11 87 ; CHECK: vsldoi 3, 3, 3, 2 88 ; CHECK: vinserth 2, 3, 2 89 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_11 90 ; CHECK-BE: vinserth 2, 3, 12 91 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7> 92 ret <8 x i16> %vecins 93 } 94 95 define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) { 96 entry: 97 ; CHECK-LABEL: shuffle_vector_halfword_7_12 98 ; CHECK: vinserth 2, 3, 0 99 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_12 100 ; CHECK-BE: vsldoi 3, 3, 3, 2 101 ; CHECK-BE: vinserth 2, 3, 14 102 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12> 103 ret <8 x i16> %vecins 104 } 105 106 define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) { 107 entry: 108 ; CHECK-LABEL: shuffle_vector_halfword_8_1 109 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 6 110 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 14 111 ; CHECK-BE-LABEL: shuffle_vector_halfword_8_1 112 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 12 113 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 0 114 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 115 ret <8 x i16> %vecins 116 } 117 118 ; The following testcases take one halfword element from the first vector and 119 ; inserts it at various locations in the second vector 120 define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) { 121 entry: 122 ; CHECK-LABEL: shuffle_vector_halfword_9_7 123 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 10 124 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 12 125 ; CHECK-BE-LABEL: shuffle_vector_halfword_9_7 126 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 8 127 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 2 128 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 129 ret <8 x i16> %vecins 130 } 131 132 define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) { 133 entry: 134 ; CHECK-LABEL: shuffle_vector_halfword_10_4 135 ; CHECK: vinserth 3, 2, 10 136 ; CHECK: vmr 2, 3 137 ; CHECK-BE-LABEL: shuffle_vector_halfword_10_4 138 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 2 139 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 4 140 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15> 141 ret <8 x i16> %vecins 142 } 143 144 define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) { 145 entry: 146 ; CHECK-LABEL: shuffle_vector_halfword_11_2 147 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 4 148 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 8 149 ; CHECK-BE-LABEL: shuffle_vector_halfword_11_2 150 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 14 151 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 6 152 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15> 153 ret <8 x i16> %vecins 154 } 155 156 define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) { 157 entry: 158 ; CHECK-LABEL: shuffle_vector_halfword_12_6 159 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 12 160 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 6 161 ; CHECK-BE-LABEL: shuffle_vector_halfword_12_6 162 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 6 163 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 8 164 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15> 165 ret <8 x i16> %vecins 166 } 167 168 define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) { 169 entry: 170 ; CHECK-LABEL: shuffle_vector_halfword_13_3 171 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 2 172 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 4 173 ; CHECK-BE-LABEL: shuffle_vector_halfword_13_3 174 ; CHECK-BE: vinserth 3, 2, 10 175 ; CHECK-BE: vmr 2, 3 176 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15> 177 ret <8 x i16> %vecins 178 } 179 180 define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) { 181 entry: 182 ; CHECK-LABEL: shuffle_vector_halfword_14_5 183 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 14 184 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 2 185 ; CHECK-BE-LABEL: shuffle_vector_halfword_14_5 186 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 4 187 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 12 188 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15> 189 ret <8 x i16> %vecins 190 } 191 192 define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) { 193 entry: 194 ; CHECK-LABEL: shuffle_vector_halfword_15_0 195 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 8 196 ; CHECK: vinserth {{[0-9]+}}, {{[0-9]+}}, 0 197 ; CHECK-BE-LABEL: shuffle_vector_halfword_15_0 198 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 10 199 ; CHECK-BE: vinserth {{[0-9]+}}, {{[0-9]+}}, 14 200 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0> 201 ret <8 x i16> %vecins 202 } 203 204 ; The following testcases use the same vector in both arguments of the 205 ; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one 206 ; we're attempting to insert, then we can use the vector insert instruction 207 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) { 208 entry: 209 ; CHECK-LABEL: shuffle_vector_halfword_0_4 210 ; CHECK: vinserth 2, 2, 14 211 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4 212 ; CHECK-BE-NOT: vinserth 213 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 214 ret <8 x i16> %vecins 215 } 216 217 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) { 218 entry: 219 ; CHECK-LABEL: shuffle_vector_halfword_1_3 220 ; CHECK-NOT: vinserth 221 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3 222 ; CHECK-BE: vinserth 2, 2, 2 223 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 224 ret <8 x i16> %vecins 225 } 226 227 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) { 228 entry: 229 ; CHECK-LABEL: shuffle_vector_halfword_2_3 230 ; CHECK-NOT: vinserth 231 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3 232 ; CHECK-BE: vinserth 2, 2, 4 233 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> 234 ret <8 x i16> %vecins 235 } 236 237 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) { 238 entry: 239 ; CHECK-LABEL: shuffle_vector_halfword_3_4 240 ; CHECK: vinserth 2, 2, 8 241 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4 242 ; CHECK-BE-NOT: vinserth 243 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7> 244 ret <8 x i16> %vecins 245 } 246 247 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) { 248 entry: 249 ; CHECK-LABEL: shuffle_vector_halfword_4_3 250 ; CHECK-NOT: vinserth 251 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3 252 ; CHECK-BE: vinserth 2, 2, 8 253 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7> 254 ret <8 x i16> %vecins 255 } 256 257 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) { 258 entry: 259 ; CHECK-LABEL: shuffle_vector_halfword_5_3 260 ; CHECK-NOT: vinserth 261 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3 262 ; CHECK-BE: vinserth 2, 2, 10 263 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7> 264 ret <8 x i16> %vecins 265 } 266 267 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) { 268 entry: 269 ; CHECK-LABEL: shuffle_vector_halfword_6_4 270 ; CHECK: vinserth 2, 2, 2 271 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4 272 ; CHECK-BE-NOT: vinserth 273 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7> 274 ret <8 x i16> %vecins 275 } 276 277 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) { 278 entry: 279 ; CHECK-LABEL: shuffle_vector_halfword_7_4 280 ; CHECK: vinserth 2, 2, 0 281 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4 282 ; CHECK-BE-NOT: vinserth 283 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4> 284 ret <8 x i16> %vecins 285 } 286 287 ; The following testcases take one byte element from the second vector and 288 ; inserts it at various locations in the first vector 289 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) { 290 entry: 291 ; CHECK-LABEL: shuffle_vector_byte_0_16 292 ; CHECK: vsldoi 3, 3, 3, 8 293 ; CHECK: vinsertb 2, 3, 15 294 ; CHECK-BE-LABEL: shuffle_vector_byte_0_16 295 ; CHECK-BE: vsldoi 3, 3, 3, 9 296 ; CHECK-BE: vinsertb 2, 3, 0 297 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 298 ret <16 x i8> %vecins 299 } 300 301 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) { 302 entry: 303 ; CHECK-LABEL: shuffle_vector_byte_1_25 304 ; CHECK: vsldoi 3, 3, 3, 15 305 ; CHECK: vinsertb 2, 3, 14 306 ; CHECK-BE-LABEL: shuffle_vector_byte_1_25 307 ; CHECK-BE: vsldoi 3, 3, 3, 2 308 ; CHECK-BE: vinsertb 2, 3, 1 309 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 310 ret <16 x i8> %vecins 311 } 312 313 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) { 314 entry: 315 ; CHECK-LABEL: shuffle_vector_byte_2_18 316 ; CHECK: vsldoi 3, 3, 3, 6 317 ; CHECK: vinsertb 2, 3, 13 318 ; CHECK-BE-LABEL: shuffle_vector_byte_2_18 319 ; CHECK-BE: vsldoi 3, 3, 3, 11 320 ; CHECK-BE: vinsertb 2, 3, 2 321 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 322 ret <16 x i8> %vecins 323 } 324 325 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) { 326 entry: 327 ; CHECK-LABEL: shuffle_vector_byte_3_27 328 ; CHECK: vsldoi 3, 3, 3, 13 329 ; CHECK: vinsertb 2, 3, 12 330 ; CHECK-BE-LABEL: shuffle_vector_byte_3_27 331 ; CHECK-BE: vsldoi 3, 3, 3, 4 332 ; CHECK-BE: vinsertb 2, 3, 3 333 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 334 ret <16 x i8> %vecins 335 } 336 337 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) { 338 entry: 339 ; CHECK-LABEL: shuffle_vector_byte_4_20 340 ; CHECK: vsldoi 3, 3, 3, 4 341 ; CHECK: vinsertb 2, 3, 11 342 ; CHECK-BE-LABEL: shuffle_vector_byte_4_20 343 ; CHECK-BE: vsldoi 3, 3, 3, 13 344 ; CHECK-BE: vinsertb 2, 3, 4 345 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 346 ret <16 x i8> %vecins 347 } 348 349 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) { 350 entry: 351 ; CHECK-LABEL: shuffle_vector_byte_5_29 352 ; CHECK: vsldoi 3, 3, 3, 11 353 ; CHECK: vinsertb 2, 3, 10 354 ; CHECK-BE-LABEL: shuffle_vector_byte_5_29 355 ; CHECK-BE: vsldoi 3, 3, 3, 6 356 ; CHECK-BE: vinsertb 2, 3, 5 357 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 358 ret <16 x i8> %vecins 359 } 360 361 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) { 362 entry: 363 ; CHECK-LABEL: shuffle_vector_byte_6_22 364 ; CHECK: vsldoi 3, 3, 3, 2 365 ; CHECK: vinsertb 2, 3, 9 366 ; CHECK-BE-LABEL: shuffle_vector_byte_6_22 367 ; CHECK-BE: vsldoi 3, 3, 3, 15 368 ; CHECK-BE: vinsertb 2, 3, 6 369 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 370 ret <16 x i8> %vecins 371 } 372 373 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) { 374 entry: 375 ; CHECK-LABEL: shuffle_vector_byte_7_31 376 ; CHECK: vsldoi 3, 3, 3, 9 377 ; CHECK: vinsertb 2, 3, 8 378 ; CHECK-BE-LABEL: shuffle_vector_byte_7_31 379 ; CHECK-BE: vsldoi 3, 3, 3, 8 380 ; CHECK-BE: vinsertb 2, 3, 7 381 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 382 ret <16 x i8> %vecins 383 } 384 385 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) { 386 entry: 387 ; CHECK-LABEL: shuffle_vector_byte_8_24 388 ; CHECK: vinsertb 2, 3, 7 389 ; CHECK-BE-LABEL: shuffle_vector_byte_8_24 390 ; CHECK-BE: vsldoi 3, 3, 3, 1 391 ; CHECK-BE: vinsertb 2, 3, 8 392 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 393 ret <16 x i8> %vecins 394 } 395 396 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) { 397 entry: 398 ; CHECK-LABEL: shuffle_vector_byte_9_17 399 ; CHECK: vsldoi 3, 3, 3, 7 400 ; CHECK: vinsertb 2, 3, 6 401 ; CHECK-BE-LABEL: shuffle_vector_byte_9_17 402 ; CHECK-BE: vsldoi 3, 3, 3, 10 403 ; CHECK-BE: vinsertb 2, 3, 9 404 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 405 ret <16 x i8> %vecins 406 } 407 408 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) { 409 entry: 410 ; CHECK-LABEL: shuffle_vector_byte_10_26 411 ; CHECK: vsldoi 3, 3, 3, 14 412 ; CHECK: vinsertb 2, 3, 5 413 ; CHECK-BE-LABEL: shuffle_vector_byte_10_26 414 ; CHECK-BE: vsldoi 3, 3, 3, 3 415 ; CHECK-BE: vinsertb 2, 3, 10 416 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15> 417 ret <16 x i8> %vecins 418 } 419 420 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) { 421 entry: 422 ; CHECK-LABEL: shuffle_vector_byte_11_19 423 ; CHECK: vsldoi 3, 3, 3, 5 424 ; CHECK: vinsertb 2, 3, 4 425 ; CHECK-BE-LABEL: shuffle_vector_byte_11_19 426 ; CHECK-BE: vsldoi 3, 3, 3, 12 427 ; CHECK-BE: vinsertb 2, 3, 11 428 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15> 429 ret <16 x i8> %vecins 430 } 431 432 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) { 433 entry: 434 ; CHECK-LABEL: shuffle_vector_byte_12_28 435 ; CHECK: vsldoi 3, 3, 3, 12 436 ; CHECK: vinsertb 2, 3, 3 437 ; CHECK-BE-LABEL: shuffle_vector_byte_12_28 438 ; CHECK-BE: vsldoi 3, 3, 3, 5 439 ; CHECK-BE: vinsertb 2, 3, 12 440 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15> 441 ret <16 x i8> %vecins 442 } 443 444 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) { 445 entry: 446 ; CHECK-LABEL: shuffle_vector_byte_13_21 447 ; CHECK: vsldoi 3, 3, 3, 3 448 ; CHECK: vinsertb 2, 3, 2 449 ; CHECK-BE-LABEL: shuffle_vector_byte_13_21 450 ; CHECK-BE: vsldoi 3, 3, 3, 14 451 ; CHECK-BE: vinsertb 2, 3, 13 452 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15> 453 ret <16 x i8> %vecins 454 } 455 456 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) { 457 entry: 458 ; CHECK-LABEL: shuffle_vector_byte_14_30 459 ; CHECK: vsldoi 3, 3, 3, 10 460 ; CHECK: vinsertb 2, 3, 1 461 ; CHECK-BE-LABEL: shuffle_vector_byte_14_30 462 ; CHECK-BE: vsldoi 3, 3, 3, 7 463 ; CHECK-BE: vinsertb 2, 3, 14 464 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15> 465 ret <16 x i8> %vecins 466 } 467 468 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) { 469 entry: 470 ; CHECK-LABEL: shuffle_vector_byte_15_23 471 ; CHECK: vsldoi 3, 3, 3, 1 472 ; CHECK: vinsertb 2, 3, 0 473 ; CHECK-BE-LABEL: shuffle_vector_byte_15_23 474 ; CHECK-BE: vinsertb 2, 3, 15 475 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23> 476 ret <16 x i8> %vecins 477 } 478 479 ; The following testcases take one byte element from the first vector and 480 ; inserts it at various locations in the second vector 481 define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) { 482 entry: 483 ; CHECK-LABEL: shuffle_vector_byte_16_8 484 ; CHECK: vinsertb 3, 2, 15 485 ; CHECK: vmr 2, 3 486 ; CHECK-BE-LABEL: shuffle_vector_byte_16_8 487 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 1 488 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 0 489 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 490 ret <16 x i8> %vecins 491 } 492 493 define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) { 494 entry: 495 ; CHECK-LABEL: shuffle_vector_byte_17_1 496 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 7 497 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 14 498 ; CHECK-BE-LABEL: shuffle_vector_byte_17_1 499 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 10 500 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 1 501 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 502 ret <16 x i8> %vecins 503 } 504 505 define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) { 506 entry: 507 ; CHECK-LABEL: shuffle_vector_byte_18_10 508 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 14 509 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 13 510 ; CHECK-BE-LABEL: shuffle_vector_byte_18_10 511 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 3 512 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 2 513 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 514 ret <16 x i8> %vecins 515 } 516 517 define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) { 518 entry: 519 ; CHECK-LABEL: shuffle_vector_byte_19_3 520 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 5 521 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 12 522 ; CHECK-BE-LABEL: shuffle_vector_byte_19_3 523 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 12 524 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 3 525 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 526 ret <16 x i8> %vecins 527 } 528 529 define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) { 530 entry: 531 ; CHECK-LABEL: shuffle_vector_byte_20_12 532 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 12 533 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 11 534 ; CHECK-BE-LABEL: shuffle_vector_byte_20_12 535 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 5 536 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 4 537 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 538 ret <16 x i8> %vecins 539 } 540 541 define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) { 542 entry: 543 ; CHECK-LABEL: shuffle_vector_byte_21_5 544 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 3 545 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 10 546 ; CHECK-BE-LABEL: shuffle_vector_byte_21_5 547 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 14 548 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 5 549 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 550 ret <16 x i8> %vecins 551 } 552 553 define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) { 554 entry: 555 ; CHECK-LABEL: shuffle_vector_byte_22_14 556 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 10 557 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 9 558 ; CHECK-BE-LABEL: shuffle_vector_byte_22_14 559 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 7 560 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 6 561 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 562 ret <16 x i8> %vecins 563 } 564 565 define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) { 566 entry: 567 ; CHECK-LABEL: shuffle_vector_byte_23_7 568 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 1 569 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 8 570 ; CHECK-BE-LABEL: shuffle_vector_byte_23_7 571 ; CHECK-BE: vinsertb 3, 2, 7 572 ; CHECK-BE: vmr 2, 3 573 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 574 ret <16 x i8> %vecins 575 } 576 577 define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) { 578 entry: 579 ; CHECK-LABEL: shuffle_vector_byte_24_0 580 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 8 581 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 7 582 ; CHECK-BE-LABEL: shuffle_vector_byte_24_0 583 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 9 584 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 8 585 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 586 ret <16 x i8> %vecins 587 } 588 589 define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) { 590 entry: 591 ; CHECK-LABEL: shuffle_vector_byte_25_9 592 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 15 593 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 6 594 ; CHECK-BE-LABEL: shuffle_vector_byte_25_9 595 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 2 596 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 9 597 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 598 ret <16 x i8> %vecins 599 } 600 601 define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) { 602 entry: 603 ; CHECK-LABEL: shuffle_vector_byte_26_2 604 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 6 605 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 5 606 ; CHECK-BE-LABEL: shuffle_vector_byte_26_2 607 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 11 608 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 10 609 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31> 610 ret <16 x i8> %vecins 611 } 612 613 define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) { 614 entry: 615 ; CHECK-LABEL: shuffle_vector_byte_27_11 616 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 13 617 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 4 618 ; CHECK-BE-LABEL: shuffle_vector_byte_27_11 619 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 4 620 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 11 621 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31> 622 ret <16 x i8> %vecins 623 } 624 625 define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) { 626 entry: 627 ; CHECK-LABEL: shuffle_vector_byte_28_4 628 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 4 629 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 3 630 ; CHECK-BE-LABEL: shuffle_vector_byte_28_4 631 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 13 632 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 12 633 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31> 634 ret <16 x i8> %vecins 635 } 636 637 define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) { 638 entry: 639 ; CHECK-LABEL: shuffle_vector_byte_29_13 640 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 11 641 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 2 642 ; CHECK-BE-LABEL: shuffle_vector_byte_29_13 643 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 6 644 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 13 645 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31> 646 ret <16 x i8> %vecins 647 } 648 649 define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) { 650 entry: 651 ; CHECK-LABEL: shuffle_vector_byte_30_6 652 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 2 653 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 1 654 ; CHECK-BE-LABEL: shuffle_vector_byte_30_6 655 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 15 656 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 14 657 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31> 658 ret <16 x i8> %vecins 659 } 660 661 define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) { 662 entry: 663 ; CHECK-LABEL: shuffle_vector_byte_31_15 664 ; CHECK: vsldoi {{[0-9]+}}, 2, 2, 9 665 ; CHECK: vinsertb {{[0-9]+}}, {{[0-9]+}}, 0 666 ; CHECK-BE-LABEL: shuffle_vector_byte_31_15 667 ; CHECK-BE: vsldoi {{[0-9]+}}, 2, 2, 8 668 ; CHECK-BE: vinsertb {{[0-9]+}}, {{[0-9]+}}, 15 669 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15> 670 ret <16 x i8> %vecins 671 } 672 673 ; The following testcases use the same vector in both arguments of the 674 ; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one 675 ; we're attempting to insert, then we can use the vector insert instruction 676 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) { 677 entry: 678 ; CHECK-LABEL: shuffle_vector_byte_0_7 679 ; CHECK-NOT: vinsertb 680 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7 681 ; CHECK-BE: vinsertb 2, 2, 0 682 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 683 ret <16 x i8> %vecins 684 } 685 686 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) { 687 entry: 688 ; CHECK-LABEL: shuffle_vector_byte_1_8 689 ; CHECK: vinsertb 2, 2, 14 690 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8 691 ; CHECK-BE-NOT: vinsertb 692 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 693 ret <16 x i8> %vecins 694 } 695 696 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) { 697 entry: 698 ; CHECK-LABEL: shuffle_vector_byte_2_8 699 ; CHECK: vinsertb 2, 2, 13 700 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8 701 ; CHECK-BE-NOT: vinsertb 702 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 703 ret <16 x i8> %vecins 704 } 705 706 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) { 707 entry: 708 ; CHECK-LABEL: shuffle_vector_byte_3_7 709 ; CHECK-NOT: vinsertb 710 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7 711 ; CHECK-BE: vinsertb 2, 2, 3 712 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 713 ret <16 x i8> %vecins 714 } 715 716 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) { 717 entry: 718 ; CHECK-LABEL: shuffle_vector_byte_4_7 719 ; CHECK-NOT: vinsertb 720 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7 721 ; CHECK-BE: vinsertb 2, 2, 4 722 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 723 ret <16 x i8> %vecins 724 } 725 726 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) { 727 entry: 728 ; CHECK-LABEL: shuffle_vector_byte_5_8 729 ; CHECK: vinsertb 2, 2, 10 730 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8 731 ; CHECK-BE-NOT: vinsertb 732 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 733 ret <16 x i8> %vecins 734 } 735 736 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) { 737 entry: 738 ; CHECK-LABEL: shuffle_vector_byte_6_8 739 ; CHECK: vinsertb 2, 2, 9 740 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8 741 ; CHECK-BE-NOT: vinsertb 742 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 743 ret <16 x i8> %vecins 744 } 745 746 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) { 747 entry: 748 ; CHECK-LABEL: shuffle_vector_byte_7_8 749 ; CHECK: vinsertb 2, 2, 8 750 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8 751 ; CHECK-BE-NOT: vinsertb 752 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 753 ret <16 x i8> %vecins 754 } 755 756 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) { 757 entry: 758 ; CHECK-LABEL: shuffle_vector_byte_8_7 759 ; CHECK-NOT: vinsertb 760 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7 761 ; CHECK-BE: vinsertb 2, 2, 8 762 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 763 ret <16 x i8> %vecins 764 } 765 766 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) { 767 entry: 768 ; CHECK-LABEL: shuffle_vector_byte_9_7 769 ; CHECK-NOT: vinsertb 770 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7 771 ; CHECK-BE: vinsertb 2, 2, 9 772 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 773 ret <16 x i8> %vecins 774 } 775 776 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) { 777 entry: 778 ; CHECK-LABEL: shuffle_vector_byte_10_7 779 ; CHECK-NOT: vinsertb 780 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7 781 ; CHECK-BE: vinsertb 2, 2, 10 782 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15> 783 ret <16 x i8> %vecins 784 } 785 786 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) { 787 entry: 788 ; CHECK-LABEL: shuffle_vector_byte_11_8 789 ; CHECK: vinsertb 2, 2, 4 790 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8 791 ; CHECK-BE-NOT: vinsertb 792 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15> 793 ret <16 x i8> %vecins 794 } 795 796 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) { 797 entry: 798 ; CHECK-LABEL: shuffle_vector_byte_12_8 799 ; CHECK: vinsertb 2, 2, 3 800 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8 801 ; CHECK-BE-NOT: vinsertb 802 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15> 803 ret <16 x i8> %vecins 804 } 805 806 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) { 807 entry: 808 ; CHECK-LABEL: shuffle_vector_byte_13_7 809 ; CHECK-NOT: vinsertb 810 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7 811 ; CHECK-BE: vinsertb 2, 2, 13 812 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15> 813 ret <16 x i8> %vecins 814 } 815 816 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) { 817 entry: 818 ; CHECK-LABEL: shuffle_vector_byte_14_7 819 ; CHECK-NOT: vinsertb 820 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7 821 ; CHECK-BE: vinsertb 2, 2, 14 822 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15> 823 ret <16 x i8> %vecins 824 } 825 826 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) { 827 entry: 828 ; CHECK-LABEL: shuffle_vector_byte_15_8 829 ; CHECK: vinsertb 2, 2, 0 830 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8 831 ; CHECK-BE-NOT: vinsertb 832 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8> 833 ret <16 x i8> %vecins 834 } 835 836 ; The following tests try to insert one halfword element into the vector. We 837 ; should always be using the 'vinserth' instruction. 838 define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) { 839 entry: 840 ; CHECK-LABEL: insert_halfword_0 841 ; CHECK: vinserth 2, 3, 14 842 ; CHECK-BE-LABEL: insert_halfword_0 843 ; CHECK-BE: vinserth 2, 3, 0 844 %vecins = insertelement <8 x i16> %a, i16 %b, i32 0 845 ret <8 x i16> %vecins 846 } 847 848 define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) { 849 entry: 850 ; CHECK-LABEL: insert_halfword_1 851 ; CHECK: vinserth 2, 3, 12 852 ; CHECK-BE-LABEL: insert_halfword_1 853 ; CHECK-BE: vinserth 2, 3, 2 854 %vecins = insertelement <8 x i16> %a, i16 %b, i32 1 855 ret <8 x i16> %vecins 856 } 857 858 define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) { 859 entry: 860 ; CHECK-LABEL: insert_halfword_2 861 ; CHECK: vinserth 2, 3, 10 862 ; CHECK-BE-LABEL: insert_halfword_2 863 ; CHECK-BE: vinserth 2, 3, 4 864 %vecins = insertelement <8 x i16> %a, i16 %b, i32 2 865 ret <8 x i16> %vecins 866 } 867 868 define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) { 869 entry: 870 ; CHECK-LABEL: insert_halfword_3 871 ; CHECK: vinserth 2, 3, 8 872 ; CHECK-BE-LABEL: insert_halfword_3 873 ; CHECK-BE: vinserth 2, 3, 6 874 %vecins = insertelement <8 x i16> %a, i16 %b, i32 3 875 ret <8 x i16> %vecins 876 } 877 878 define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) { 879 entry: 880 ; CHECK-LABEL: insert_halfword_4 881 ; CHECK: vinserth 2, 3, 6 882 ; CHECK-BE-LABEL: insert_halfword_4 883 ; CHECK-BE: vinserth 2, 3, 8 884 %vecins = insertelement <8 x i16> %a, i16 %b, i32 4 885 ret <8 x i16> %vecins 886 } 887 888 define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) { 889 entry: 890 ; CHECK-LABEL: insert_halfword_5 891 ; CHECK: vinserth 2, 3, 4 892 ; CHECK-BE-LABEL: insert_halfword_5 893 ; CHECK-BE: vinserth 2, 3, 10 894 %vecins = insertelement <8 x i16> %a, i16 %b, i32 5 895 ret <8 x i16> %vecins 896 } 897 898 define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) { 899 entry: 900 ; CHECK-LABEL: insert_halfword_6 901 ; CHECK: vinserth 2, 3, 2 902 ; CHECK-BE-LABEL: insert_halfword_6 903 ; CHECK-BE: vinserth 2, 3, 12 904 %vecins = insertelement <8 x i16> %a, i16 %b, i32 6 905 ret <8 x i16> %vecins 906 } 907 908 define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) { 909 entry: 910 ; CHECK-LABEL: insert_halfword_7 911 ; CHECK: vinserth 2, 3, 0 912 ; CHECK-BE-LABEL: insert_halfword_7 913 ; CHECK-BE: vinserth 2, 3, 14 914 %vecins = insertelement <8 x i16> %a, i16 %b, i32 7 915 ret <8 x i16> %vecins 916 } 917 918 ; The following tests try to insert one byte element into the vector. We 919 ; should always be using the 'vinsertb' instruction. 920 define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) { 921 entry: 922 ; CHECK-LABEL: insert_byte_0 923 ; CHECK: vinsertb 2, 3, 15 924 ; CHECK-BE-LABEL: insert_byte_0 925 ; CHECK-BE: vinsertb 2, 3, 0 926 %vecins = insertelement <16 x i8> %a, i8 %b, i32 0 927 ret <16 x i8> %vecins 928 } 929 930 define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) { 931 entry: 932 ; CHECK-LABEL: insert_byte_1 933 ; CHECK: vinsertb 2, 3, 14 934 ; CHECK-BE-LABEL: insert_byte_1 935 ; CHECK-BE: vinsertb 2, 3, 1 936 %vecins = insertelement <16 x i8> %a, i8 %b, i32 1 937 ret <16 x i8> %vecins 938 } 939 940 define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) { 941 entry: 942 ; CHECK-LABEL: insert_byte_2 943 ; CHECK: vinsertb 2, 3, 13 944 ; CHECK-BE-LABEL: insert_byte_2 945 ; CHECK-BE: vinsertb 2, 3, 2 946 %vecins = insertelement <16 x i8> %a, i8 %b, i32 2 947 ret <16 x i8> %vecins 948 } 949 950 define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) { 951 entry: 952 ; CHECK-LABEL: insert_byte_3 953 ; CHECK: vinsertb 2, 3, 12 954 ; CHECK-BE-LABEL: insert_byte_3 955 ; CHECK-BE: vinsertb 2, 3, 3 956 %vecins = insertelement <16 x i8> %a, i8 %b, i32 3 957 ret <16 x i8> %vecins 958 } 959 960 define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) { 961 entry: 962 ; CHECK-LABEL: insert_byte_4 963 ; CHECK: vinsertb 2, 3, 11 964 ; CHECK-BE-LABEL: insert_byte_4 965 ; CHECK-BE: vinsertb 2, 3, 4 966 %vecins = insertelement <16 x i8> %a, i8 %b, i32 4 967 ret <16 x i8> %vecins 968 } 969 970 define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) { 971 entry: 972 ; CHECK-LABEL: insert_byte_5 973 ; CHECK: vinsertb 2, 3, 10 974 ; CHECK-BE-LABEL: insert_byte_5 975 ; CHECK-BE: vinsertb 2, 3, 5 976 %vecins = insertelement <16 x i8> %a, i8 %b, i32 5 977 ret <16 x i8> %vecins 978 } 979 980 define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) { 981 entry: 982 ; CHECK-LABEL: insert_byte_6 983 ; CHECK: vinsertb 2, 3, 9 984 ; CHECK-BE-LABEL: insert_byte_6 985 ; CHECK-BE: vinsertb 2, 3, 6 986 %vecins = insertelement <16 x i8> %a, i8 %b, i32 6 987 ret <16 x i8> %vecins 988 } 989 990 define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) { 991 entry: 992 ; CHECK-LABEL: insert_byte_7 993 ; CHECK: vinsertb 2, 3, 8 994 ; CHECK-BE-LABEL: insert_byte_7 995 ; CHECK-BE: vinsertb 2, 3, 7 996 %vecins = insertelement <16 x i8> %a, i8 %b, i32 7 997 ret <16 x i8> %vecins 998 } 999 1000 define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) { 1001 entry: 1002 ; CHECK-LABEL: insert_byte_8 1003 ; CHECK: vinsertb 2, 3, 7 1004 ; CHECK-BE-LABEL: insert_byte_8 1005 ; CHECK-BE: vinsertb 2, 3, 8 1006 %vecins = insertelement <16 x i8> %a, i8 %b, i32 8 1007 ret <16 x i8> %vecins 1008 } 1009 1010 define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) { 1011 entry: 1012 ; CHECK-LABEL: insert_byte_9 1013 ; CHECK: vinsertb 2, 3, 6 1014 ; CHECK-BE-LABEL: insert_byte_9 1015 ; CHECK-BE: vinsertb 2, 3, 9 1016 %vecins = insertelement <16 x i8> %a, i8 %b, i32 9 1017 ret <16 x i8> %vecins 1018 } 1019 1020 define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) { 1021 entry: 1022 ; CHECK-LABEL: insert_byte_10 1023 ; CHECK: vinsertb 2, 3, 5 1024 ; CHECK-BE-LABEL: insert_byte_10 1025 ; CHECK-BE: vinsertb 2, 3, 10 1026 %vecins = insertelement <16 x i8> %a, i8 %b, i32 10 1027 ret <16 x i8> %vecins 1028 } 1029 1030 define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) { 1031 entry: 1032 ; CHECK-LABEL: insert_byte_11 1033 ; CHECK: vinsertb 2, 3, 4 1034 ; CHECK-BE-LABEL: insert_byte_11 1035 ; CHECK-BE: vinsertb 2, 3, 11 1036 %vecins = insertelement <16 x i8> %a, i8 %b, i32 11 1037 ret <16 x i8> %vecins 1038 } 1039 1040 define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) { 1041 entry: 1042 ; CHECK-LABEL: insert_byte_12 1043 ; CHECK: vinsertb 2, 3, 3 1044 ; CHECK-BE-LABEL: insert_byte_12 1045 ; CHECK-BE: vinsertb 2, 3, 12 1046 %vecins = insertelement <16 x i8> %a, i8 %b, i32 12 1047 ret <16 x i8> %vecins 1048 } 1049 1050 define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) { 1051 entry: 1052 ; CHECK-LABEL: insert_byte_13 1053 ; CHECK: vinsertb 2, 3, 2 1054 ; CHECK-BE-LABEL: insert_byte_13 1055 ; CHECK-BE: vinsertb 2, 3, 13 1056 %vecins = insertelement <16 x i8> %a, i8 %b, i32 13 1057 ret <16 x i8> %vecins 1058 } 1059 1060 define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) { 1061 entry: 1062 ; CHECK-LABEL: insert_byte_14 1063 ; CHECK: vinsertb 2, 3, 1 1064 ; CHECK-BE-LABEL: insert_byte_14 1065 ; CHECK-BE: vinsertb 2, 3, 14 1066 %vecins = insertelement <16 x i8> %a, i8 %b, i32 14 1067 ret <16 x i8> %vecins 1068 } 1069 1070 define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) { 1071 entry: 1072 ; CHECK-LABEL: insert_byte_15 1073 ; CHECK: vinsertb 2, 3, 0 1074 ; CHECK-BE-LABEL: insert_byte_15 1075 ; CHECK-BE: vinsertb 2, 3, 15 1076 %vecins = insertelement <16 x i8> %a, i8 %b, i32 15 1077 ret <16 x i8> %vecins 1078 } 1079
