1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 3 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4 5 define zeroext i32 @ReverseBits(i32 zeroext %n) { 6 ; CHECK-LABEL: ReverseBits: 7 ; CHECK: # %bb.0: # %entry 8 ; CHECK-NEXT: lis 4, -21846 9 ; CHECK-NEXT: lis 5, 21845 10 ; CHECK-NEXT: slwi 6, 3, 1 11 ; CHECK-NEXT: srwi 3, 3, 1 12 ; CHECK-NEXT: ori 4, 4, 43690 13 ; CHECK-NEXT: ori 5, 5, 21845 14 ; CHECK-NEXT: and 4, 6, 4 15 ; CHECK-NEXT: and 3, 3, 5 16 ; CHECK-NEXT: lis 5, 13107 17 ; CHECK-NEXT: or 3, 3, 4 18 ; CHECK-NEXT: lis 4, -13108 19 ; CHECK-NEXT: ori 5, 5, 13107 20 ; CHECK-NEXT: slwi 6, 3, 2 21 ; CHECK-NEXT: ori 4, 4, 52428 22 ; CHECK-NEXT: srwi 3, 3, 2 23 ; CHECK-NEXT: and 4, 6, 4 24 ; CHECK-NEXT: and 3, 3, 5 25 ; CHECK-NEXT: lis 5, 3855 26 ; CHECK-NEXT: or 3, 3, 4 27 ; CHECK-NEXT: lis 4, -3856 28 ; CHECK-NEXT: ori 5, 5, 3855 29 ; CHECK-NEXT: slwi 6, 3, 4 30 ; CHECK-NEXT: ori 4, 4, 61680 31 ; CHECK-NEXT: srwi 3, 3, 4 32 ; CHECK-NEXT: and 4, 6, 4 33 ; CHECK-NEXT: and 3, 3, 5 34 ; CHECK-NEXT: or 3, 3, 4 35 ; CHECK-NEXT: rotlwi 4, 3, 24 36 ; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15 37 ; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31 38 ; CHECK-NEXT: rldicl 3, 4, 0, 32 39 ; CHECK-NEXT: clrldi 3, 3, 32 40 ; CHECK-NEXT: blr 41 entry: 42 %shr = lshr i32 %n, 1 43 %and = and i32 %shr, 1431655765 44 %and1 = shl i32 %n, 1 45 %shl = and i32 %and1, -1431655766 46 %or = or i32 %and, %shl 47 %shr2 = lshr i32 %or, 2 48 %and3 = and i32 %shr2, 858993459 49 %and4 = shl i32 %or, 2 50 %shl5 = and i32 %and4, -858993460 51 %or6 = or i32 %and3, %shl5 52 %shr7 = lshr i32 %or6, 4 53 %and8 = and i32 %shr7, 252645135 54 %and9 = shl i32 %or6, 4 55 %shl10 = and i32 %and9, -252645136 56 %or11 = or i32 %and8, %shl10 57 %shr13 = lshr i32 %or11, 24 58 %and14 = lshr i32 %or11, 8 59 %shr15 = and i32 %and14, 65280 60 %and17 = shl i32 %or11, 8 61 %shl18 = and i32 %and17, 16711680 62 %shl21 = shl i32 %or11, 24 63 %or16 = or i32 %shl21, %shr13 64 %or19 = or i32 %or16, %shr15 65 %or22 = or i32 %or19, %shl18 66 ret i32 %or22 67 } 68 69 define i64 @ReverseBits64(i64 %n) { 70 ; CHECK-LABEL: ReverseBits64: 71 ; CHECK: # %bb.0: # %entry 72 ; CHECK-NEXT: lis 4, -21846 73 ; CHECK-NEXT: lis 5, 21845 74 ; CHECK-NEXT: lis 6, -13108 75 ; CHECK-NEXT: lis 7, 13107 76 ; CHECK-NEXT: sldi 8, 3, 1 77 ; CHECK-NEXT: rldicl 3, 3, 63, 1 78 ; CHECK-NEXT: ori 4, 4, 43690 79 ; CHECK-NEXT: ori 5, 5, 21845 80 ; CHECK-NEXT: ori 6, 6, 52428 81 ; CHECK-NEXT: ori 7, 7, 13107 82 ; CHECK-NEXT: sldi 4, 4, 32 83 ; CHECK-NEXT: sldi 5, 5, 32 84 ; CHECK-NEXT: oris 4, 4, 43690 85 ; CHECK-NEXT: oris 5, 5, 21845 86 ; CHECK-NEXT: ori 4, 4, 43690 87 ; CHECK-NEXT: ori 5, 5, 21845 88 ; CHECK-NEXT: and 4, 8, 4 89 ; CHECK-NEXT: and 3, 3, 5 90 ; CHECK-NEXT: sldi 5, 6, 32 91 ; CHECK-NEXT: sldi 6, 7, 32 92 ; CHECK-NEXT: lis 7, 3855 93 ; CHECK-NEXT: or 3, 3, 4 94 ; CHECK-NEXT: oris 4, 5, 52428 95 ; CHECK-NEXT: oris 5, 6, 13107 96 ; CHECK-NEXT: lis 6, -3856 97 ; CHECK-NEXT: ori 7, 7, 3855 98 ; CHECK-NEXT: sldi 8, 3, 2 99 ; CHECK-NEXT: ori 4, 4, 52428 100 ; CHECK-NEXT: rldicl 3, 3, 62, 2 101 ; CHECK-NEXT: ori 5, 5, 13107 102 ; CHECK-NEXT: ori 6, 6, 61680 103 ; CHECK-NEXT: and 4, 8, 4 104 ; CHECK-NEXT: and 3, 3, 5 105 ; CHECK-NEXT: sldi 5, 6, 32 106 ; CHECK-NEXT: sldi 6, 7, 32 107 ; CHECK-NEXT: or 3, 3, 4 108 ; CHECK-NEXT: oris 4, 5, 61680 109 ; CHECK-NEXT: oris 5, 6, 3855 110 ; CHECK-NEXT: sldi 6, 3, 4 111 ; CHECK-NEXT: ori 4, 4, 61680 112 ; CHECK-NEXT: rldicl 3, 3, 60, 4 113 ; CHECK-NEXT: ori 5, 5, 3855 114 ; CHECK-NEXT: and 4, 6, 4 115 ; CHECK-NEXT: and 3, 3, 5 116 ; CHECK-NEXT: or 3, 3, 4 117 ; CHECK-NEXT: rldicl 4, 3, 32, 32 118 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 119 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 120 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 121 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 122 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 123 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 124 ; CHECK-NEXT: sldi 3, 5, 32 125 ; CHECK-NEXT: or 3, 3, 6 126 ; CHECK-NEXT: blr 127 entry: 128 %shr = lshr i64 %n, 1 129 %and = and i64 %shr, 6148914691236517205 130 %and1 = shl i64 %n, 1 131 %shl = and i64 %and1, -6148914691236517206 132 %or = or i64 %and, %shl 133 %shr2 = lshr i64 %or, 2 134 %and3 = and i64 %shr2, 3689348814741910323 135 %and4 = shl i64 %or, 2 136 %shl5 = and i64 %and4, -3689348814741910324 137 %or6 = or i64 %and3, %shl5 138 %shr7 = lshr i64 %or6, 4 139 %and8 = and i64 %shr7, 1085102592571150095 140 %and9 = shl i64 %or6, 4 141 %shl10 = and i64 %and9, -1085102592571150096 142 %or11 = or i64 %and8, %shl10 143 %shr13 = lshr i64 %or11, 56 144 %and14 = lshr i64 %or11, 40 145 %shr15 = and i64 %and14, 65280 146 %and17 = lshr i64 %or11, 24 147 %shr18 = and i64 %and17, 16711680 148 %and20 = lshr i64 %or11, 8 149 %shr21 = and i64 %and20, 4278190080 150 %and23 = shl i64 %or11, 8 151 %shl24 = and i64 %and23, 1095216660480 152 %and26 = shl i64 %or11, 24 153 %shl27 = and i64 %and26, 280375465082880 154 %and29 = shl i64 %or11, 40 155 %shl30 = and i64 %and29, 71776119061217280 156 %shl33 = shl i64 %or11, 56 157 %or16 = or i64 %shl33, %shr13 158 %or19 = or i64 %or16, %shr15 159 %or22 = or i64 %or19, %shr18 160 %or25 = or i64 %or22, %shr21 161 %or28 = or i64 %or25, %shl24 162 %or31 = or i64 %or28, %shl27 163 %or34 = or i64 %or31, %shl30 164 ret i64 %or34 165 } 166
