1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 3 ; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s | \ 4 ; RUN: FileCheck %s 5 ; Function Attrs: nounwind readnone speculatable 6 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 7 8 ; Function Attrs: nounwind readnone speculatable 9 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0 10 11 define void @draw_llvm_vs_variant0() { 12 ; CHECK-LABEL: draw_llvm_vs_variant0: 13 ; CHECK: # %bb.0: # %entry 14 ; CHECK-NEXT: lfd f0, 0(r3) 15 ; CHECK-NEXT: xxpermdi v2, f0, f0, 2 16 ; CHECK-NEXT: vmrglh v2, v2, v2 17 ; CHECK-NEXT: vextsh2w v2, v2 18 ; CHECK-NEXT: xvcvsxwsp vs0, v2 19 ; CHECK-NEXT: xxspltw vs0, vs0, 2 20 ; CHECK-NEXT: xvmaddasp vs0, vs0, vs0 21 ; CHECK-NEXT: stxvx vs0, 0, r3 22 ; CHECK-NEXT: blr 23 entry: 24 %.size = load i32, i32* undef 25 %0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7) 26 %1 = extractvalue { i32, i1 } %0, 0 27 %2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0) 28 %3 = extractvalue { i32, i1 } %2, 0 29 %4 = select i1 false, i32 0, i32 %3 30 %5 = xor i1 false, true 31 %6 = sext i1 %5 to i32 32 %7 = load <4 x i16>, <4 x i16>* undef, align 2 33 %8 = extractelement <4 x i16> %7, i32 0 34 %9 = sext i16 %8 to i32 35 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 36 %11 = extractelement <4 x i16> %7, i32 1 37 %12 = sext i16 %11 to i32 38 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 39 %14 = extractelement <4 x i16> %7, i32 2 40 %15 = sext i16 %14 to i32 41 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 42 %17 = extractelement <4 x i16> %7, i32 3 43 %18 = sext i16 %17 to i32 44 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 45 %20 = sitofp <4 x i32> %19 to <4 x float> 46 %21 = insertelement <4 x i32> undef, i32 %6, i32 0 47 %22 = shufflevector <4 x i32> %21, <4 x i32> undef, <4 x i32> zeroinitializer 48 %23 = bitcast <4 x float> %20 to <4 x i32> 49 %24 = and <4 x i32> %23, %22 50 %25 = bitcast <4 x i32> %24 to <4 x float> 51 %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 52 %27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> undef, <4 x float> %26) 53 store <4 x float> %27, <4 x float>* undef 54 ret void 55 } 56
