1 ; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs < %s | FileCheck %s 2 ; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \ 3 ; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s 4 target datalayout = "E-m:e-i64:64-n32:64" 5 target triple = "powerpc64-unknown-linux-gnu" 6 7 ; FIXME: We should check the operands to the cr* logical operation itself, but 8 ; unfortunately, FileCheck does not yet understand how to do arithmetic, so we 9 ; can't do so without introducing a register-allocation dependency. 10 11 define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 12 entry: 13 %cmp1 = icmp eq i32 %c3, %c4 14 %cmp3tmp = icmp eq i32 %c1, %c2 15 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 16 %cond = select i1 %cmp3, i32 %a1, i32 %a2 17 ret i32 %cond 18 19 ; CHECK-LABEL: @testi32slt 20 ; CHECK-NO-ISEL-LABEL: @testi32slt 21 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 22 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 23 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 24 ; CHECK: isel 3, 7, 8, [[REG1]] 25 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 26 ; CHECK-NO-ISEL: ori 3, 8, 0 27 ; CHECK-NO-ISEL-NEXT: blr 28 ; CHECK-NO-ISEL: [[TRUE]] 29 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 30 ; CHECK-NO-ISEL-NEXT: blr 31 ; CHECK: blr 32 } 33 34 define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 35 entry: 36 %cmp1 = icmp eq i32 %c3, %c4 37 %cmp3tmp = icmp eq i32 %c1, %c2 38 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 39 %cond = select i1 %cmp3, i32 %a1, i32 %a2 40 ret i32 %cond 41 42 ; CHECK-NO-ISEL-LABEL: @testi32ult 43 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 44 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 45 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 46 ; CHECK: isel 3, 7, 8, [[REG1]] 47 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 48 ; CHECK-NO-ISEL: ori 3, 8, 0 49 ; CHECK-NO-ISEL-NEXT: blr 50 ; CHECK-NO-ISEL: [[TRUE]] 51 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 52 ; CHECK-NO-ISEL-NEXT: blr 53 ; CHECK: blr 54 } 55 56 define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 57 entry: 58 %cmp1 = icmp eq i32 %c3, %c4 59 %cmp3tmp = icmp eq i32 %c1, %c2 60 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 61 %cond = select i1 %cmp3, i32 %a1, i32 %a2 62 ret i32 %cond 63 64 ; CHECK-LABEL: @testi32sle 65 ; CHECK-NO-ISEL-LABEL: @testi32sle 66 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 67 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 68 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 69 ; CHECK: isel 3, 7, 8, [[REG1]] 70 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 71 ; CHECK-NO-ISEL: ori 3, 8, 0 72 ; CHECK-NO-ISEL-NEXT: blr 73 ; CHECK-NO-ISEL: [[TRUE]] 74 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 75 ; CHECK-NO-ISEL-NEXT: blr 76 ; CHECK: blr 77 } 78 79 define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 80 entry: 81 %cmp1 = icmp eq i32 %c3, %c4 82 %cmp3tmp = icmp eq i32 %c1, %c2 83 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 84 %cond = select i1 %cmp3, i32 %a1, i32 %a2 85 ret i32 %cond 86 87 ; CHECK-LABEL: @testi32ule 88 ; CHECK-NO-ISEL-LABEL: @testi32ule 89 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 90 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 91 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 92 ; CHECK: isel 3, 7, 8, [[REG1]] 93 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 94 ; CHECK-NO-ISEL: ori 3, 8, 0 95 ; CHECK-NO-ISEL-NEXT: blr 96 ; CHECK-NO-ISEL: [[TRUE]] 97 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 98 ; CHECK-NO-ISEL-NEXT: blr 99 ; CHECK: blr 100 } 101 102 define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 103 entry: 104 %cmp1 = icmp eq i32 %c3, %c4 105 %cmp3tmp = icmp eq i32 %c1, %c2 106 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 107 %cond = select i1 %cmp3, i32 %a1, i32 %a2 108 ret i32 %cond 109 110 ; CHECK-LABEL: @testi32eq 111 ; CHECK-NO-ISEL-LABEL: @testi32eq 112 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 113 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 114 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 115 ; CHECK: isel 3, 7, 8, [[REG1]] 116 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 117 ; CHECK-NO-ISEL: ori 3, 8, 0 118 ; CHECK-NO-ISEL-NEXT: blr 119 ; CHECK-NO-ISEL: [[TRUE]] 120 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 121 ; CHECK-NO-ISEL-NEXT: blr 122 ; CHECK: blr 123 } 124 125 define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 126 entry: 127 %cmp1 = icmp eq i32 %c3, %c4 128 %cmp3tmp = icmp eq i32 %c1, %c2 129 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 130 %cond = select i1 %cmp3, i32 %a1, i32 %a2 131 ret i32 %cond 132 133 ; CHECK-LABEL: @testi32sge 134 ; CHECK-NO-ISEL-LABEL: @testi32sge 135 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 136 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 137 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 138 ; CHECK: isel 3, 7, 8, [[REG1]] 139 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 140 ; CHECK-NO-ISEL: ori 3, 8, 0 141 ; CHECK-NO-ISEL-NEXT: blr 142 ; CHECK-NO-ISEL: [[TRUE]] 143 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 144 ; CHECK-NO-ISEL-NEXT: blr 145 ; CHECK: blr 146 } 147 148 define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 149 entry: 150 %cmp1 = icmp eq i32 %c3, %c4 151 %cmp3tmp = icmp eq i32 %c1, %c2 152 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 153 %cond = select i1 %cmp3, i32 %a1, i32 %a2 154 ret i32 %cond 155 156 ; CHECK-LABEL: @testi32uge 157 ; CHECK-NO-ISEL-LABEL: @testi32uge 158 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 159 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 160 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 161 ; CHECK: isel 3, 7, 8, [[REG1]] 162 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 163 ; CHECK-NO-ISEL: ori 3, 8, 0 164 ; CHECK-NO-ISEL-NEXT: blr 165 ; CHECK-NO-ISEL: [[TRUE]] 166 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 167 ; CHECK-NO-ISEL-NEXT: blr 168 ; CHECK: blr 169 } 170 171 define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 172 entry: 173 %cmp1 = icmp eq i32 %c3, %c4 174 %cmp3tmp = icmp eq i32 %c1, %c2 175 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 176 %cond = select i1 %cmp3, i32 %a1, i32 %a2 177 ret i32 %cond 178 179 ; CHECK-LABEL: @testi32sgt 180 ; CHECK-NO-ISEL-LABEL: @testi32sgt 181 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 182 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 183 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 184 ; CHECK: isel 3, 7, 8, [[REG1]] 185 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 186 ; CHECK-NO-ISEL: ori 3, 8, 0 187 ; CHECK-NO-ISEL-NEXT: blr 188 ; CHECK-NO-ISEL: [[TRUE]] 189 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 190 ; CHECK-NO-ISEL-NEXT: blr 191 ; CHECK: blr 192 } 193 194 define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 195 entry: 196 %cmp1 = icmp eq i32 %c3, %c4 197 %cmp3tmp = icmp eq i32 %c1, %c2 198 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 199 %cond = select i1 %cmp3, i32 %a1, i32 %a2 200 ret i32 %cond 201 202 ; CHECK-LABEL: @testi32ugt 203 ; CHECK-NO-ISEL-LABEL: @testi32ugt 204 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 205 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 206 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 207 ; CHECK: isel 3, 7, 8, [[REG1]] 208 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 209 ; CHECK-NO-ISEL: ori 3, 8, 0 210 ; CHECK-NO-ISEL-NEXT: blr 211 ; CHECK-NO-ISEL: [[TRUE]] 212 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 213 ; CHECK-NO-ISEL-NEXT: blr 214 ; CHECK: blr 215 } 216 217 define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { 218 entry: 219 %cmp1 = icmp eq i32 %c3, %c4 220 %cmp3tmp = icmp eq i32 %c1, %c2 221 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 222 %cond = select i1 %cmp3, i32 %a1, i32 %a2 223 ret i32 %cond 224 225 ; CHECK-LABEL: @testi32ne 226 ; CHECK-NO-ISEL-LABEL: @testi32ne 227 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 228 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 229 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 230 ; CHECK: isel 3, 7, 8, [[REG1]] 231 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 232 ; CHECK-NO-ISEL: ori 3, 8, 0 233 ; CHECK-NO-ISEL-NEXT: blr 234 ; CHECK-NO-ISEL: [[TRUE]] 235 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 236 ; CHECK-NO-ISEL-NEXT: blr 237 ; CHECK: blr 238 } 239 240 define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 241 entry: 242 %cmp1 = icmp eq i64 %c3, %c4 243 %cmp3tmp = icmp eq i64 %c1, %c2 244 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 245 %cond = select i1 %cmp3, i64 %a1, i64 %a2 246 ret i64 %cond 247 248 ; CHECK-LABEL: @testi64slt 249 ; CHECK-NO-ISEL-LABEL: @testi64slt 250 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 251 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 252 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 253 ; CHECK: isel 3, 7, 8, [[REG1]] 254 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 255 ; CHECK-NO-ISEL: ori 3, 8, 0 256 ; CHECK-NO-ISEL-NEXT: blr 257 ; CHECK-NO-ISEL: [[TRUE]] 258 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 259 ; CHECK-NO-ISEL-NEXT: blr 260 ; CHECK: blr 261 } 262 263 define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 264 entry: 265 %cmp1 = icmp eq i64 %c3, %c4 266 %cmp3tmp = icmp eq i64 %c1, %c2 267 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 268 %cond = select i1 %cmp3, i64 %a1, i64 %a2 269 ret i64 %cond 270 271 ; CHECK-LABEL: @testi64ult 272 ; CHECK-NO-ISEL-LABEL: @testi64ult 273 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 274 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 275 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 276 ; CHECK: isel 3, 7, 8, [[REG1]] 277 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 278 ; CHECK-NO-ISEL: ori 3, 8, 0 279 ; CHECK-NO-ISEL-NEXT: blr 280 ; CHECK-NO-ISEL: [[TRUE]] 281 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 282 ; CHECK-NO-ISEL-NEXT: blr 283 ; CHECK: blr 284 } 285 286 define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 287 entry: 288 %cmp1 = icmp eq i64 %c3, %c4 289 %cmp3tmp = icmp eq i64 %c1, %c2 290 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 291 %cond = select i1 %cmp3, i64 %a1, i64 %a2 292 ret i64 %cond 293 294 ; CHECK-LABEL: @testi64sle 295 ; CHECK-NO-ISEL-LABEL: @testi64sle 296 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 297 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 298 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 299 ; CHECK: isel 3, 7, 8, [[REG1]] 300 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 301 ; CHECK-NO-ISEL: ori 3, 8, 0 302 ; CHECK-NO-ISEL-NEXT: blr 303 ; CHECK-NO-ISEL: [[TRUE]] 304 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 305 ; CHECK-NO-ISEL-NEXT: blr 306 ; CHECK: blr 307 } 308 309 define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 310 entry: 311 %cmp1 = icmp eq i64 %c3, %c4 312 %cmp3tmp = icmp eq i64 %c1, %c2 313 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 314 %cond = select i1 %cmp3, i64 %a1, i64 %a2 315 ret i64 %cond 316 317 ; CHECK-LABEL: @testi64ule 318 ; CHECK-NO-ISEL-LABEL: @testi64ule 319 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 320 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 321 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 322 ; CHECK: isel 3, 7, 8, [[REG1]] 323 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 324 ; CHECK-NO-ISEL: ori 3, 8, 0 325 ; CHECK-NO-ISEL-NEXT: blr 326 ; CHECK-NO-ISEL: [[TRUE]] 327 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 328 ; CHECK-NO-ISEL-NEXT: blr 329 ; CHECK: blr 330 } 331 332 define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 333 entry: 334 %cmp1 = icmp eq i64 %c3, %c4 335 %cmp3tmp = icmp eq i64 %c1, %c2 336 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 337 %cond = select i1 %cmp3, i64 %a1, i64 %a2 338 ret i64 %cond 339 340 ; CHECK-LABEL: @testi64eq 341 ; CHECK-NO-ISEL-LABEL: @testi64eq 342 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 343 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 344 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 345 ; CHECK: isel 3, 7, 8, [[REG1]] 346 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 347 ; CHECK-NO-ISEL: ori 3, 8, 0 348 ; CHECK-NO-ISEL-NEXT: blr 349 ; CHECK-NO-ISEL: [[TRUE]] 350 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 351 ; CHECK-NO-ISEL-NEXT: blr 352 ; CHECK: blr 353 } 354 355 define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 356 entry: 357 %cmp1 = icmp eq i64 %c3, %c4 358 %cmp3tmp = icmp eq i64 %c1, %c2 359 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 360 %cond = select i1 %cmp3, i64 %a1, i64 %a2 361 ret i64 %cond 362 363 ; CHECK-LABEL: @testi64sge 364 ; CHECK-NO-ISEL-LABEL: @testi64sge 365 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 366 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 367 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 368 ; CHECK: isel 3, 7, 8, [[REG1]] 369 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 370 ; CHECK-NO-ISEL: ori 3, 8, 0 371 ; CHECK-NO-ISEL-NEXT: blr 372 ; CHECK-NO-ISEL: [[TRUE]] 373 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 374 ; CHECK-NO-ISEL-NEXT: blr 375 ; CHECK: blr 376 } 377 378 define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 379 entry: 380 %cmp1 = icmp eq i64 %c3, %c4 381 %cmp3tmp = icmp eq i64 %c1, %c2 382 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 383 %cond = select i1 %cmp3, i64 %a1, i64 %a2 384 ret i64 %cond 385 386 ; CHECK-LABEL: @testi64uge 387 ; CHECK-NO-ISEL-LABEL: @testi64uge 388 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 389 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 390 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 391 ; CHECK: isel 3, 7, 8, [[REG1]] 392 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 393 ; CHECK-NO-ISEL: ori 3, 8, 0 394 ; CHECK-NO-ISEL-NEXT: blr 395 ; CHECK-NO-ISEL: [[TRUE]] 396 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 397 ; CHECK-NO-ISEL-NEXT: blr 398 ; CHECK: blr 399 } 400 401 define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 402 entry: 403 %cmp1 = icmp eq i64 %c3, %c4 404 %cmp3tmp = icmp eq i64 %c1, %c2 405 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 406 %cond = select i1 %cmp3, i64 %a1, i64 %a2 407 ret i64 %cond 408 409 ; CHECK-LABEL: @testi64sgt 410 ; CHECK-NO-ISEL-LABEL: @testi64sgt 411 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 412 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 413 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 414 ; CHECK: isel 3, 7, 8, [[REG1]] 415 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 416 ; CHECK-NO-ISEL: ori 3, 8, 0 417 ; CHECK-NO-ISEL-NEXT: blr 418 ; CHECK-NO-ISEL: [[TRUE]] 419 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 420 ; CHECK-NO-ISEL-NEXT: blr 421 ; CHECK: blr 422 } 423 424 define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 425 entry: 426 %cmp1 = icmp eq i64 %c3, %c4 427 %cmp3tmp = icmp eq i64 %c1, %c2 428 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 429 %cond = select i1 %cmp3, i64 %a1, i64 %a2 430 ret i64 %cond 431 432 ; CHECK-LABEL: @testi64ugt 433 ; CHECK-NO-ISEL-LABEL: @testi64ugt 434 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 435 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 436 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 437 ; CHECK: isel 3, 7, 8, [[REG1]] 438 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 439 ; CHECK-NO-ISEL: ori 3, 8, 0 440 ; CHECK-NO-ISEL-NEXT: blr 441 ; CHECK-NO-ISEL: [[TRUE]] 442 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 443 ; CHECK-NO-ISEL-NEXT: blr 444 ; CHECK: blr 445 } 446 447 define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { 448 entry: 449 %cmp1 = icmp eq i64 %c3, %c4 450 %cmp3tmp = icmp eq i64 %c1, %c2 451 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 452 %cond = select i1 %cmp3, i64 %a1, i64 %a2 453 ret i64 %cond 454 455 ; CHECK-LABEL: @testi64ne 456 ; CHECK-NO-ISEL-LABEL: @testi64ne 457 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6 458 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4 459 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 460 ; CHECK: isel 3, 7, 8, [[REG1]] 461 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 462 ; CHECK-NO-ISEL: ori 3, 8, 0 463 ; CHECK-NO-ISEL-NEXT: blr 464 ; CHECK-NO-ISEL: [[TRUE]] 465 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 466 ; CHECK-NO-ISEL-NEXT: blr 467 ; CHECK: blr 468 } 469 470 define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 471 entry: 472 %cmp1 = fcmp oeq float %c3, %c4 473 %cmp3tmp = fcmp oeq float %c1, %c2 474 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 475 %cond = select i1 %cmp3, float %a1, float %a2 476 ret float %cond 477 478 ; CHECK-LABEL: @testfloatslt 479 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 480 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 481 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 482 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 483 ; CHECK: .LBB[[BB1]]: 484 ; CHECK: fmr 5, 6 485 ; CHECK: .LBB[[BB2]]: 486 ; CHECK: fmr 1, 5 487 ; CHECK: blr 488 } 489 490 define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 491 entry: 492 %cmp1 = fcmp oeq float %c3, %c4 493 %cmp3tmp = fcmp oeq float %c1, %c2 494 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 495 %cond = select i1 %cmp3, float %a1, float %a2 496 ret float %cond 497 498 ; CHECK-LABEL: @testfloatult 499 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 500 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 501 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 502 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 503 ; CHECK: .LBB[[BB1]]: 504 ; CHECK: fmr 5, 6 505 ; CHECK: .LBB[[BB2]]: 506 ; CHECK: fmr 1, 5 507 ; CHECK: blr 508 } 509 510 define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 511 entry: 512 %cmp1 = fcmp oeq float %c3, %c4 513 %cmp3tmp = fcmp oeq float %c1, %c2 514 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 515 %cond = select i1 %cmp3, float %a1, float %a2 516 ret float %cond 517 518 ; CHECK-LABEL: @testfloatsle 519 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 520 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 521 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 522 ; CHECK: bc 12, 2, .LBB[[BB]] 523 ; CHECK: fmr 5, 6 524 ; CHECK: .LBB[[BB]]: 525 ; CHECK: fmr 1, 5 526 ; CHECK: blr 527 } 528 529 define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 530 entry: 531 %cmp1 = fcmp oeq float %c3, %c4 532 %cmp3tmp = fcmp oeq float %c1, %c2 533 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 534 %cond = select i1 %cmp3, float %a1, float %a2 535 ret float %cond 536 537 ; CHECK-LABEL: @testfloatule 538 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 539 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 540 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 541 ; CHECK: bc 4, 2, .LBB[[BB]] 542 ; CHECK: fmr 5, 6 543 ; CHECK: .LBB[[BB]]: 544 ; CHECK: fmr 1, 5 545 ; CHECK: blr 546 } 547 548 define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 549 entry: 550 %cmp1 = fcmp oeq float %c3, %c4 551 %cmp3tmp = fcmp oeq float %c1, %c2 552 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 553 %cond = select i1 %cmp3, float %a1, float %a2 554 ret float %cond 555 556 ; CHECK-LABEL: @testfloateq 557 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 558 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 559 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 560 ; CHECK: bclr 12, [[REG1]], 0 561 ; CHECK: fmr 1, 6 562 ; CHECK: blr 563 } 564 565 define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 566 entry: 567 %cmp1 = fcmp oeq float %c3, %c4 568 %cmp3tmp = fcmp oeq float %c1, %c2 569 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 570 %cond = select i1 %cmp3, float %a1, float %a2 571 ret float %cond 572 573 ; CHECK-LABEL: @testfloatsge 574 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 575 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 576 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 577 ; CHECK: bc 4, 2, .LBB[[BB]] 578 ; CHECK: fmr 5, 6 579 ; CHECK: .LBB[[BB]]: 580 ; CHECK: fmr 1, 5 581 ; CHECK: blr 582 } 583 584 define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 585 entry: 586 %cmp1 = fcmp oeq float %c3, %c4 587 %cmp3tmp = fcmp oeq float %c1, %c2 588 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 589 %cond = select i1 %cmp3, float %a1, float %a2 590 ret float %cond 591 592 ; CHECK-LABEL: @testfloatuge 593 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 594 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 595 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 596 ; CHECK: bc 12, 2, .LBB[[BB]] 597 ; CHECK: fmr 5, 6 598 ; CHECK: .LBB[[BB]]: 599 ; CHECK: fmr 1, 5 600 ; CHECK: blr 601 } 602 603 define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 604 entry: 605 %cmp1 = fcmp oeq float %c3, %c4 606 %cmp3tmp = fcmp oeq float %c1, %c2 607 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 608 %cond = select i1 %cmp3, float %a1, float %a2 609 ret float %cond 610 611 ; CHECK-LABEL: @testfloatsgt 612 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 613 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 614 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 615 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 616 ; CHECK: .LBB[[BB1]]: 617 ; CHECK: fmr 5, 6 618 ; CHECK: .LBB[[BB2]]: 619 ; CHECK: fmr 1, 5 620 ; CHECK: blr 621 } 622 623 define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 624 entry: 625 %cmp1 = fcmp oeq float %c3, %c4 626 %cmp3tmp = fcmp oeq float %c1, %c2 627 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 628 %cond = select i1 %cmp3, float %a1, float %a2 629 ret float %cond 630 631 ; CHECK-LABEL: @testfloatugt 632 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 633 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 634 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 635 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 636 ; CHECK: .LBB[[BB1]]: 637 ; CHECK: fmr 5, 6 638 ; CHECK: .LBB[[BB2]]: 639 ; CHECK: fmr 1, 5 640 ; CHECK: blr 641 } 642 643 define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 { 644 entry: 645 %cmp1 = fcmp oeq float %c3, %c4 646 %cmp3tmp = fcmp oeq float %c1, %c2 647 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 648 %cond = select i1 %cmp3, float %a1, float %a2 649 ret float %cond 650 651 ; CHECK-LABEL: @testfloatne 652 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 653 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 654 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 655 ; CHECK: bclr 12, [[REG1]], 0 656 ; CHECK: fmr 1, 6 657 ; CHECK: blr 658 } 659 660 define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 661 entry: 662 %cmp1 = fcmp oeq double %c3, %c4 663 %cmp3tmp = fcmp oeq double %c1, %c2 664 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 665 %cond = select i1 %cmp3, double %a1, double %a2 666 ret double %cond 667 668 ; CHECK-LABEL: @testdoubleslt 669 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 670 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 671 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 672 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 673 ; CHECK: .LBB[[BB1]]: 674 ; CHECK: fmr 5, 6 675 ; CHECK: .LBB[[BB2]]: 676 ; CHECK: fmr 1, 5 677 ; CHECK: blr 678 } 679 680 define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 681 entry: 682 %cmp1 = fcmp oeq double %c3, %c4 683 %cmp3tmp = fcmp oeq double %c1, %c2 684 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 685 %cond = select i1 %cmp3, double %a1, double %a2 686 ret double %cond 687 688 ; CHECK-LABEL: @testdoubleult 689 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 690 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 691 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 692 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 693 ; CHECK: .LBB[[BB1]]: 694 ; CHECK: fmr 5, 6 695 ; CHECK: .LBB[[BB2]]: 696 ; CHECK: fmr 1, 5 697 ; CHECK: blr 698 } 699 700 define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 701 entry: 702 %cmp1 = fcmp oeq double %c3, %c4 703 %cmp3tmp = fcmp oeq double %c1, %c2 704 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 705 %cond = select i1 %cmp3, double %a1, double %a2 706 ret double %cond 707 708 ; CHECK-LABEL: @testdoublesle 709 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 710 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 711 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 712 ; CHECK: bc 12, 2, .LBB[[BB]] 713 ; CHECK: fmr 5, 6 714 ; CHECK: .LBB[[BB]]: 715 ; CHECK: fmr 1, 5 716 ; CHECK: blr 717 } 718 719 define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 720 entry: 721 %cmp1 = fcmp oeq double %c3, %c4 722 %cmp3tmp = fcmp oeq double %c1, %c2 723 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 724 %cond = select i1 %cmp3, double %a1, double %a2 725 ret double %cond 726 727 ; CHECK-LABEL: @testdoubleule 728 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 729 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 730 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 731 ; CHECK: bc 4, 2, .LBB[[BB]] 732 ; CHECK: fmr 5, 6 733 ; CHECK: .LBB[[BB]]: 734 ; CHECK: fmr 1, 5 735 ; CHECK: blr 736 } 737 738 define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 739 entry: 740 %cmp1 = fcmp oeq double %c3, %c4 741 %cmp3tmp = fcmp oeq double %c1, %c2 742 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 743 %cond = select i1 %cmp3, double %a1, double %a2 744 ret double %cond 745 746 ; CHECK-LABEL: @testdoubleeq 747 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 748 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 749 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 750 ; CHECK: bclr 12, [[REG1]], 0 751 ; CHECK: fmr 1, 6 752 ; CHECK: blr 753 } 754 755 define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 756 entry: 757 %cmp1 = fcmp oeq double %c3, %c4 758 %cmp3tmp = fcmp oeq double %c1, %c2 759 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 760 %cond = select i1 %cmp3, double %a1, double %a2 761 ret double %cond 762 763 ; CHECK-LABEL: @testdoublesge 764 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 765 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 766 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 767 ; CHECK: bc 4, 2, .LBB[[BB]] 768 ; CHECK: fmr 5, 6 769 ; CHECK: .LBB[[BB]]: 770 ; CHECK: fmr 1, 5 771 ; CHECK: blr 772 } 773 774 define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 775 entry: 776 %cmp1 = fcmp oeq double %c3, %c4 777 %cmp3tmp = fcmp oeq double %c1, %c2 778 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 779 %cond = select i1 %cmp3, double %a1, double %a2 780 ret double %cond 781 782 ; CHECK-LABEL: @testdoubleuge 783 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 784 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 785 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 786 ; CHECK: bc 12, 2, .LBB[[BB]] 787 ; CHECK: fmr 5, 6 788 ; CHECK: .LBB[[BB]]: 789 ; CHECK: fmr 1, 5 790 ; CHECK: blr 791 } 792 793 define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 794 entry: 795 %cmp1 = fcmp oeq double %c3, %c4 796 %cmp3tmp = fcmp oeq double %c1, %c2 797 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 798 %cond = select i1 %cmp3, double %a1, double %a2 799 ret double %cond 800 801 ; CHECK-LABEL: @testdoublesgt 802 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 803 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 804 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 805 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 806 ; CHECK: .LBB[[BB1]]: 807 ; CHECK: fmr 5, 6 808 ; CHECK: .LBB[[BB2]]: 809 ; CHECK: fmr 1, 5 810 ; CHECK: blr 811 } 812 813 define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 814 entry: 815 %cmp1 = fcmp oeq double %c3, %c4 816 %cmp3tmp = fcmp oeq double %c1, %c2 817 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 818 %cond = select i1 %cmp3, double %a1, double %a2 819 ret double %cond 820 821 ; CHECK-LABEL: @testdoubleugt 822 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 823 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 824 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 825 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 826 ; CHECK: .LBB[[BB1]]: 827 ; CHECK: fmr 5, 6 828 ; CHECK: .LBB[[BB2]]: 829 ; CHECK: fmr 1, 5 830 ; CHECK: blr 831 } 832 833 define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 { 834 entry: 835 %cmp1 = fcmp oeq double %c3, %c4 836 %cmp3tmp = fcmp oeq double %c1, %c2 837 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 838 %cond = select i1 %cmp3, double %a1, double %a2 839 ret double %cond 840 841 ; CHECK-LABEL: @testdoublene 842 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 843 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 844 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 845 ; CHECK: bclr 12, [[REG1]], 0 846 ; CHECK: fmr 1, 6 847 ; CHECK: blr 848 } 849 850 define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 851 entry: 852 %cmp1 = fcmp oeq float %c3, %c4 853 %cmp3tmp = fcmp oeq float %c1, %c2 854 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 855 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 856 ret <4 x float> %cond 857 858 ; CHECK-LABEL: @testv4floatslt 859 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 860 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 861 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 862 ; CHECK: bclr 12, 2, 0 863 ; CHECK: .LBB[[BB]]: 864 ; CHECK: vmr 2, 3 865 ; CHECK: blr 866 } 867 868 define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 869 entry: 870 %cmp1 = fcmp oeq float %c3, %c4 871 %cmp3tmp = fcmp oeq float %c1, %c2 872 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 873 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 874 ret <4 x float> %cond 875 876 ; CHECK-LABEL: @testv4floatult 877 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 878 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 879 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 880 ; CHECK: bclr 4, 2, 0 881 ; CHECK: .LBB[[BB]]: 882 ; CHECK: vmr 2, 3 883 ; CHECK: blr 884 } 885 886 define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 887 entry: 888 %cmp1 = fcmp oeq float %c3, %c4 889 %cmp3tmp = fcmp oeq float %c1, %c2 890 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 891 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 892 ret <4 x float> %cond 893 894 ; CHECK-LABEL: @testv4floatsle 895 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 896 ; CHECK: bclr 4, 2, 0 897 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 898 ; CHECK: bclr 12, 2, 0 899 ; CHECK: vmr 2, 3 900 ; CHECK: blr 901 } 902 903 define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 904 entry: 905 %cmp1 = fcmp oeq float %c3, %c4 906 %cmp3tmp = fcmp oeq float %c1, %c2 907 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 908 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 909 ret <4 x float> %cond 910 911 ; CHECK-LABEL: @testv4floatule 912 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 913 ; CHECK: bclr 12, 2, 0 914 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 915 ; CHECK: bclr 4, 2, 0 916 ; CHECK: vmr 2, 3 917 ; CHECK: blr 918 } 919 920 define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 921 entry: 922 %cmp1 = fcmp oeq float %c3, %c4 923 %cmp3tmp = fcmp oeq float %c1, %c2 924 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 925 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 926 ret <4 x float> %cond 927 928 ; CHECK-LABEL: @testv4floateq 929 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 930 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 931 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 932 ; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]] 933 ; CHECK: vmr 3, 2 934 ; CHECK: .LBB[[BB1]] 935 ; CHECK: vmr 2, 3 936 ; CHECK: blr 937 } 938 939 define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 940 entry: 941 %cmp1 = fcmp oeq float %c3, %c4 942 %cmp3tmp = fcmp oeq float %c1, %c2 943 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 944 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 945 ret <4 x float> %cond 946 947 ; CHECK-LABEL: @testv4floatsge 948 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 949 ; CHECK: bclr 12, 2, 0 950 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 951 ; CHECK: bclr 4, 2, 0 952 ; CHECK: vmr 2, 3 953 ; CHECK: blr 954 } 955 956 define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 957 entry: 958 %cmp1 = fcmp oeq float %c3, %c4 959 %cmp3tmp = fcmp oeq float %c1, %c2 960 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 961 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 962 ret <4 x float> %cond 963 964 ; CHECK-LABEL: @testv4floatuge 965 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 966 ; CHECK: bclr 4, 2, 0 967 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 968 ; CHECK: bclr 12, 2, 0 969 ; CHECK: vmr 2, 3 970 ; CHECK: blr 971 } 972 973 define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 974 entry: 975 %cmp1 = fcmp oeq float %c3, %c4 976 %cmp3tmp = fcmp oeq float %c1, %c2 977 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 978 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 979 ret <4 x float> %cond 980 981 ; CHECK-LABEL: @testv4floatsgt 982 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 983 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 984 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 985 ; CHECK: bclr 4, 2, 0 986 ; CHECK: vmr 2, 3 987 ; CHECK: blr 988 } 989 990 define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 991 entry: 992 %cmp1 = fcmp oeq float %c3, %c4 993 %cmp3tmp = fcmp oeq float %c1, %c2 994 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 995 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 996 ret <4 x float> %cond 997 998 ; CHECK-LABEL: @testv4floatugt 999 ; CHECK: fcmpu {{[0-9]+}}, 3, 4 1000 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1001 ; CHECK: fcmpu {{[0-9]+}}, 1, 2 1002 ; CHECK: bclr 12, 2, 0 1003 ; CHECK: .LBB[[BB]] 1004 ; CHECK: vmr 2, 3 1005 ; CHECK: blr 1006 } 1007 1008 define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 { 1009 entry: 1010 %cmp1 = fcmp oeq float %c3, %c4 1011 %cmp3tmp = fcmp oeq float %c1, %c2 1012 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1013 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1014 ret <4 x float> %cond 1015 1016 ; CHECK-LABEL: @testv4floatne 1017 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1018 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1019 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1020 ; CHECK: bclr 12, [[REG1]], 0 1021 ; CHECK: vmr 2, 3 1022 ; CHECK: blr 1023 } 1024 1025 define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 { 1026 entry: 1027 %cmp1 = fcmp oeq ppc_fp128 %c3, %c4 1028 %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2 1029 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1030 %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2 1031 ret ppc_fp128 %cond 1032 1033 ; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion 1034 ; works, we end up with two blocks with the same predicate. These could be 1035 ; combined. 1036 1037 ; CHECK-LABEL: @testppc_fp128eq 1038 ; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8 1039 ; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7 1040 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4 1041 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3 1042 ; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1043 ; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1044 ; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]] 1045 ; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]] 1046 ; CHECK: fmr 11, 9 1047 ; CHECK: .LBB[[BB1]]: 1048 ; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]] 1049 ; CHECK: fmr 12, 10 1050 ; CHECK: .LBB[[BB2]]: 1051 ; CHECK-DAG: fmr 1, 11 1052 ; CHECK-DAG: fmr 2, 12 1053 ; CHECK: blr 1054 } 1055 1056 define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1057 entry: 1058 %cmp1 = fcmp oeq float %c3, %c4 1059 %cmp3tmp = fcmp oeq float %c1, %c2 1060 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1061 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1062 ret <2 x double> %cond 1063 1064 ; CHECK-LABEL: @testv2doubleslt 1065 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1066 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1067 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1068 ; CHECK: bc 4, 2, .LBB[[BB]] 1069 ; CHECK: .LBB[[BB]]: 1070 ; CHECK: vmr 2, 3 1071 ; CHECK: blr 1072 } 1073 1074 define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1075 entry: 1076 %cmp1 = fcmp oeq float %c3, %c4 1077 %cmp3tmp = fcmp oeq float %c1, %c2 1078 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1079 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1080 ret <2 x double> %cond 1081 1082 ; CHECK-LABEL: @testv2doubleult 1083 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1084 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1085 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1086 ; CHECK: bc 12, 2, .LBB[[BB]] 1087 ; CHECK: .LBB[[BB]]: 1088 ; CHECK: vmr 2, 3 1089 ; CHECK: blr 1090 } 1091 1092 define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1093 entry: 1094 %cmp1 = fcmp oeq float %c3, %c4 1095 %cmp3tmp = fcmp oeq float %c1, %c2 1096 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1097 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1098 ret <2 x double> %cond 1099 1100 ; CHECK-LABEL: @testv2doublesle 1101 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1102 ; CHECK: bclr 4, 2, 0 1103 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1104 ; CHECK: bclr 12, 2, 0 1105 ; CHECK: vmr 2, 3 1106 ; CHECK: blr 1107 } 1108 1109 define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1110 entry: 1111 %cmp1 = fcmp oeq float %c3, %c4 1112 %cmp3tmp = fcmp oeq float %c1, %c2 1113 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1114 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1115 ret <2 x double> %cond 1116 1117 ; CHECK-LABEL: @testv2doubleule 1118 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1119 ; CHECK: bclr 12, 2, 0 1120 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1121 ; CHECK: bclr 4, 2, 0 1122 ; CHECK: vmr 2, 3 1123 ; CHECK: blr 1124 } 1125 1126 define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1127 entry: 1128 %cmp1 = fcmp oeq float %c3, %c4 1129 %cmp3tmp = fcmp oeq float %c1, %c2 1130 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1131 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1132 ret <2 x double> %cond 1133 1134 ; CHECK-LABEL: @testv2doubleeq 1135 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1136 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1137 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1138 ; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]] 1139 ; CHECK: vmr 3, 2 1140 ; CHECK: .LBB[[BB55]] 1141 ; CHECK: vmr 2, 3 1142 ; CHECK: blr 1143 } 1144 1145 define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1146 entry: 1147 %cmp1 = fcmp oeq float %c3, %c4 1148 %cmp3tmp = fcmp oeq float %c1, %c2 1149 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1150 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1151 ret <2 x double> %cond 1152 1153 ; CHECK-LABEL: @testv2doublesge 1154 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1155 ; CHECK: bclr 12, 2, 0 1156 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1157 ; CHECK: bclr 4, 2, 0 1158 ; CHECK: vmr 2, 3 1159 ; CHECK: blr 1160 } 1161 1162 define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1163 entry: 1164 %cmp1 = fcmp oeq float %c3, %c4 1165 %cmp3tmp = fcmp oeq float %c1, %c2 1166 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1167 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1168 ret <2 x double> %cond 1169 1170 ; CHECK-LABEL: @testv2doubleuge 1171 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1172 ; CHECK: bclr 4, 2, 0 1173 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1174 ; CHECK: bclr 12, 2, 0 1175 ; CHECK: vmr 2, 3 1176 ; CHECK: blr 1177 } 1178 1179 define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1180 entry: 1181 %cmp1 = fcmp oeq float %c3, %c4 1182 %cmp3tmp = fcmp oeq float %c1, %c2 1183 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1184 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1185 ret <2 x double> %cond 1186 1187 ; CHECK-LABEL: @testv2doublesgt 1188 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1189 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1190 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1191 ; CHECK: bc 12, 2, .LBB[[BB]] 1192 ; CHECK: .LBB[[BB]] 1193 ; CHECK: vmr 2, 3 1194 ; CHECK: blr 1195 } 1196 1197 define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1198 entry: 1199 %cmp1 = fcmp oeq float %c3, %c4 1200 %cmp3tmp = fcmp oeq float %c1, %c2 1201 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1202 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1203 ret <2 x double> %cond 1204 1205 ; CHECK-LABEL: @testv2doubleugt 1206 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1207 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1208 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1209 ; CHECK: bc 4, 2, .LBB[[BB]] 1210 ; CHECK: .LBB[[BB]] 1211 ; CHECK: vmr 2, 3 1212 ; CHECK: blr 1213 } 1214 1215 define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 { 1216 entry: 1217 %cmp1 = fcmp oeq float %c3, %c4 1218 %cmp3tmp = fcmp oeq float %c1, %c2 1219 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1220 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2 1221 ret <2 x double> %cond 1222 1223 ; CHECK-LABEL: @testv2doublene 1224 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1225 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1226 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1227 ; CHECK: bclr 12, [[REG1]], 0 1228 ; CHECK: vmr 2, 3 1229 ; CHECK: blr 1230 } 1231 1232 define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1233 entry: 1234 %cmp1 = fcmp oeq float %c3, %c4 1235 %cmp3tmp = fcmp oeq float %c1, %c2 1236 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1237 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1238 ret <4 x double> %cond 1239 1240 ; CHECK-LABEL: @testqv4doubleslt 1241 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1242 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1243 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1244 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1245 ; CHECK: .LBB[[BB1]]: 1246 ; CHECK: qvfmr 5, 6 1247 ; CHECK: .LBB[[BB2]]: 1248 ; CHECK: qvfmr 1, 5 1249 ; CHECK: blr 1250 } 1251 1252 define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1253 entry: 1254 %cmp1 = fcmp oeq float %c3, %c4 1255 %cmp3tmp = fcmp oeq float %c1, %c2 1256 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1257 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1258 ret <4 x double> %cond 1259 1260 ; CHECK-LABEL: @testqv4doubleult 1261 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1262 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1263 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1264 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1265 ; CHECK: .LBB[[BB1]]: 1266 ; CHECK: qvfmr 5, 6 1267 ; CHECK: .LBB[[BB2]]: 1268 ; CHECK: qvfmr 1, 5 1269 ; CHECK: blr 1270 } 1271 1272 define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1273 entry: 1274 %cmp1 = fcmp oeq float %c3, %c4 1275 %cmp3tmp = fcmp oeq float %c1, %c2 1276 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1277 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1278 ret <4 x double> %cond 1279 1280 ; CHECK-LABEL: @testqv4doublesle 1281 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1282 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1283 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1284 ; CHECK: bc 12, 2, .LBB[[BB]] 1285 ; CHECK: qvfmr 5, 6 1286 ; CHECK: .LBB[[BB]]: 1287 ; CHECK: qvfmr 1, 5 1288 ; CHECK: blr 1289 } 1290 1291 define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1292 entry: 1293 %cmp1 = fcmp oeq float %c3, %c4 1294 %cmp3tmp = fcmp oeq float %c1, %c2 1295 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1296 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1297 ret <4 x double> %cond 1298 1299 ; CHECK-LABEL: @testqv4doubleule 1300 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1301 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1302 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1303 ; CHECK: bc 4, 2, .LBB[[BB]] 1304 ; CHECK: qvfmr 5, 6 1305 ; CHECK: .LBB[[BB]]: 1306 ; CHECK: qvfmr 1, 5 1307 ; CHECK: blr 1308 } 1309 1310 define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1311 entry: 1312 %cmp1 = fcmp oeq float %c3, %c4 1313 %cmp3tmp = fcmp oeq float %c1, %c2 1314 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1315 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1316 ret <4 x double> %cond 1317 1318 ; CHECK-LABEL: @testqv4doubleeq 1319 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1320 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1321 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1322 ; CHECK: bclr 12, [[REG1]], 0 1323 ; CHECK: qvfmr 1, 6 1324 ; CHECK: blr 1325 } 1326 1327 define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1328 entry: 1329 %cmp1 = fcmp oeq float %c3, %c4 1330 %cmp3tmp = fcmp oeq float %c1, %c2 1331 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1332 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1333 ret <4 x double> %cond 1334 1335 ; CHECK-LABEL: @testqv4doublesge 1336 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1337 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1338 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1339 ; CHECK: bc 4, 2, .LBB[[BB]] 1340 ; CHECK: qvfmr 5, 6 1341 ; CHECK: .LBB[[BB]]: 1342 ; CHECK: qvfmr 1, 5 1343 ; CHECK: blr 1344 } 1345 1346 define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1347 entry: 1348 %cmp1 = fcmp oeq float %c3, %c4 1349 %cmp3tmp = fcmp oeq float %c1, %c2 1350 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1351 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1352 ret <4 x double> %cond 1353 1354 ; CHECK-LABEL: @testqv4doubleuge 1355 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1356 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1357 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1358 ; CHECK: bc 12, 2, .LBB[[BB]] 1359 ; CHECK: qvfmr 5, 6 1360 ; CHECK: .LBB[[BB]]: 1361 ; CHECK: qvfmr 1, 5 1362 ; CHECK: blr 1363 } 1364 1365 define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1366 entry: 1367 %cmp1 = fcmp oeq float %c3, %c4 1368 %cmp3tmp = fcmp oeq float %c1, %c2 1369 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1370 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1371 ret <4 x double> %cond 1372 1373 ; CHECK-LABEL: @testqv4doublesgt 1374 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1375 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1376 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1377 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1378 ; CHECK: .LBB[[BB1]]: 1379 ; CHECK: qvfmr 5, 6 1380 ; CHECK: .LBB[[BB2]]: 1381 ; CHECK: qvfmr 1, 5 1382 ; CHECK: blr 1383 } 1384 1385 define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1386 entry: 1387 %cmp1 = fcmp oeq float %c3, %c4 1388 %cmp3tmp = fcmp oeq float %c1, %c2 1389 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1390 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1391 ret <4 x double> %cond 1392 1393 ; CHECK-LABEL: @testqv4doubleugt 1394 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1395 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1396 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1397 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1398 ; CHECK: .LBB[[BB1]]: 1399 ; CHECK: qvfmr 5, 6 1400 ; CHECK: .LBB[[BB2]]: 1401 ; CHECK: qvfmr 1, 5 1402 ; CHECK: blr 1403 } 1404 1405 define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 { 1406 entry: 1407 %cmp1 = fcmp oeq float %c3, %c4 1408 %cmp3tmp = fcmp oeq float %c1, %c2 1409 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1410 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2 1411 ret <4 x double> %cond 1412 1413 ; CHECK-LABEL: @testqv4doublene 1414 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1415 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1416 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1417 ; CHECK: bclr 12, [[REG1]], 0 1418 ; CHECK: qvfmr 1, 6 1419 ; CHECK: blr 1420 } 1421 1422 define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1423 entry: 1424 %cmp1 = fcmp oeq float %c3, %c4 1425 %cmp3tmp = fcmp oeq float %c1, %c2 1426 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1427 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1428 ret <4 x float> %cond 1429 1430 ; CHECK-LABEL: @testqv4floatslt 1431 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1432 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1433 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1434 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1435 ; CHECK: .LBB[[BB1]]: 1436 ; CHECK: qvfmr 5, 6 1437 ; CHECK: .LBB[[BB2]]: 1438 ; CHECK: qvfmr 1, 5 1439 ; CHECK: blr 1440 } 1441 1442 define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1443 entry: 1444 %cmp1 = fcmp oeq float %c3, %c4 1445 %cmp3tmp = fcmp oeq float %c1, %c2 1446 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1447 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1448 ret <4 x float> %cond 1449 1450 ; CHECK-LABEL: @testqv4floatult 1451 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1452 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1453 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1454 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1455 ; CHECK: .LBB[[BB1]]: 1456 ; CHECK: qvfmr 5, 6 1457 ; CHECK: .LBB[[BB2]]: 1458 ; CHECK: qvfmr 1, 5 1459 ; CHECK: blr 1460 } 1461 1462 define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1463 entry: 1464 %cmp1 = fcmp oeq float %c3, %c4 1465 %cmp3tmp = fcmp oeq float %c1, %c2 1466 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1467 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1468 ret <4 x float> %cond 1469 1470 ; CHECK-LABEL: @testqv4floatsle 1471 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1472 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1473 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1474 ; CHECK: bc 12, 2, .LBB[[BB]] 1475 ; CHECK: qvfmr 5, 6 1476 ; CHECK: .LBB[[BB]]: 1477 ; CHECK: qvfmr 1, 5 1478 ; CHECK: blr 1479 } 1480 1481 define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1482 entry: 1483 %cmp1 = fcmp oeq float %c3, %c4 1484 %cmp3tmp = fcmp oeq float %c1, %c2 1485 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1486 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1487 ret <4 x float> %cond 1488 1489 ; CHECK-LABEL: @testqv4floatule 1490 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1491 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1492 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1493 ; CHECK: bc 4, 2, .LBB[[BB]] 1494 ; CHECK: qvfmr 5, 6 1495 ; CHECK: .LBB[[BB]]: 1496 ; CHECK: qvfmr 1, 5 1497 ; CHECK: blr 1498 } 1499 1500 define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1501 entry: 1502 %cmp1 = fcmp oeq float %c3, %c4 1503 %cmp3tmp = fcmp oeq float %c1, %c2 1504 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1505 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1506 ret <4 x float> %cond 1507 1508 ; CHECK-LABEL: @testqv4floateq 1509 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1510 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1511 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1512 ; CHECK: bclr 12, [[REG1]], 0 1513 ; CHECK: qvfmr 1, 6 1514 ; CHECK: blr 1515 } 1516 1517 define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1518 entry: 1519 %cmp1 = fcmp oeq float %c3, %c4 1520 %cmp3tmp = fcmp oeq float %c1, %c2 1521 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1522 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1523 ret <4 x float> %cond 1524 1525 ; CHECK-LABEL: @testqv4floatsge 1526 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1527 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1528 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1529 ; CHECK: bc 4, 2, .LBB[[BB]] 1530 ; CHECK: qvfmr 5, 6 1531 ; CHECK: .LBB[[BB]]: 1532 ; CHECK: qvfmr 1, 5 1533 ; CHECK: blr 1534 } 1535 1536 define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1537 entry: 1538 %cmp1 = fcmp oeq float %c3, %c4 1539 %cmp3tmp = fcmp oeq float %c1, %c2 1540 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1541 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1542 ret <4 x float> %cond 1543 1544 ; CHECK-LABEL: @testqv4floatuge 1545 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1546 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1547 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1548 ; CHECK: bc 12, 2, .LBB[[BB]] 1549 ; CHECK: qvfmr 5, 6 1550 ; CHECK: .LBB[[BB]]: 1551 ; CHECK: qvfmr 1, 5 1552 ; CHECK: blr 1553 } 1554 1555 define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1556 entry: 1557 %cmp1 = fcmp oeq float %c3, %c4 1558 %cmp3tmp = fcmp oeq float %c1, %c2 1559 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1560 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1561 ret <4 x float> %cond 1562 1563 ; CHECK-LABEL: @testqv4floatsgt 1564 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1565 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1566 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1567 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1568 ; CHECK: .LBB[[BB1]]: 1569 ; CHECK: qvfmr 5, 6 1570 ; CHECK: .LBB[[BB2]]: 1571 ; CHECK: qvfmr 1, 5 1572 ; CHECK: blr 1573 } 1574 1575 define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1576 entry: 1577 %cmp1 = fcmp oeq float %c3, %c4 1578 %cmp3tmp = fcmp oeq float %c1, %c2 1579 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1580 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1581 ret <4 x float> %cond 1582 1583 ; CHECK-LABEL: @testqv4floatugt 1584 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1585 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1586 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1587 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1588 ; CHECK: .LBB[[BB1]]: 1589 ; CHECK: qvfmr 5, 6 1590 ; CHECK: .LBB[[BB2]]: 1591 ; CHECK: qvfmr 1, 5 1592 ; CHECK: blr 1593 } 1594 1595 define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 { 1596 entry: 1597 %cmp1 = fcmp oeq float %c3, %c4 1598 %cmp3tmp = fcmp oeq float %c1, %c2 1599 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1600 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2 1601 ret <4 x float> %cond 1602 1603 ; CHECK-LABEL: @testqv4floatne 1604 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1605 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1606 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1607 ; CHECK: bclr 12, [[REG1]], 0 1608 ; CHECK: qvfmr 1, 6 1609 ; CHECK: blr 1610 } 1611 1612 define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1613 entry: 1614 %cmp1 = fcmp oeq float %c3, %c4 1615 %cmp3tmp = fcmp oeq float %c1, %c2 1616 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1 1617 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1618 ret <4 x i1> %cond 1619 1620 ; CHECK-LABEL: @testqv4i1slt 1621 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1622 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1623 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1624 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1625 ; CHECK: .LBB[[BB1]]: 1626 ; CHECK: qvfmr 5, 6 1627 ; CHECK: .LBB[[BB2]]: 1628 ; CHECK: qvfmr 1, 5 1629 ; CHECK: blr 1630 } 1631 1632 define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1633 entry: 1634 %cmp1 = fcmp oeq float %c3, %c4 1635 %cmp3tmp = fcmp oeq float %c1, %c2 1636 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1 1637 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1638 ret <4 x i1> %cond 1639 1640 ; CHECK-LABEL: @testqv4i1ult 1641 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1642 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1643 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1644 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1645 ; CHECK: .LBB[[BB1]]: 1646 ; CHECK: qvfmr 5, 6 1647 ; CHECK: .LBB[[BB2]]: 1648 ; CHECK: qvfmr 1, 5 1649 ; CHECK: blr 1650 } 1651 1652 define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1653 entry: 1654 %cmp1 = fcmp oeq float %c3, %c4 1655 %cmp3tmp = fcmp oeq float %c1, %c2 1656 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1 1657 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1658 ret <4 x i1> %cond 1659 1660 ; CHECK-LABEL: @testqv4i1sle 1661 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1662 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1663 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1664 ; CHECK: bc 12, 2, .LBB[[BB]] 1665 ; CHECK: qvfmr 5, 6 1666 ; CHECK: .LBB[[BB]]: 1667 ; CHECK: qvfmr 1, 5 1668 ; CHECK: blr 1669 } 1670 1671 define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1672 entry: 1673 %cmp1 = fcmp oeq float %c3, %c4 1674 %cmp3tmp = fcmp oeq float %c1, %c2 1675 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1 1676 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1677 ret <4 x i1> %cond 1678 1679 ; CHECK-LABEL: @testqv4i1ule 1680 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1681 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1682 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1683 ; CHECK: bc 4, 2, .LBB[[BB]] 1684 ; CHECK: qvfmr 5, 6 1685 ; CHECK: .LBB[[BB]]: 1686 ; CHECK: qvfmr 1, 5 1687 ; CHECK: blr 1688 } 1689 1690 define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1691 entry: 1692 %cmp1 = fcmp oeq float %c3, %c4 1693 %cmp3tmp = fcmp oeq float %c1, %c2 1694 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1 1695 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1696 ret <4 x i1> %cond 1697 1698 ; CHECK-LABEL: @testqv4i1eq 1699 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1700 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1701 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1702 ; CHECK: bclr 12, [[REG1]], 0 1703 ; CHECK: qvfmr 1, 6 1704 ; CHECK: blr 1705 } 1706 1707 define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1708 entry: 1709 %cmp1 = fcmp oeq float %c3, %c4 1710 %cmp3tmp = fcmp oeq float %c1, %c2 1711 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1 1712 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1713 ret <4 x i1> %cond 1714 1715 ; CHECK-LABEL: @testqv4i1sge 1716 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1717 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]] 1718 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1719 ; CHECK: bc 4, 2, .LBB[[BB]] 1720 ; CHECK: qvfmr 5, 6 1721 ; CHECK: .LBB[[BB]]: 1722 ; CHECK: qvfmr 1, 5 1723 ; CHECK: blr 1724 } 1725 1726 define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1727 entry: 1728 %cmp1 = fcmp oeq float %c3, %c4 1729 %cmp3tmp = fcmp oeq float %c1, %c2 1730 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1 1731 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1732 ret <4 x i1> %cond 1733 1734 ; CHECK-LABEL: @testqv4i1uge 1735 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1736 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]] 1737 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1738 ; CHECK: bc 12, 2, .LBB[[BB]] 1739 ; CHECK: qvfmr 5, 6 1740 ; CHECK: .LBB[[BB]]: 1741 ; CHECK: qvfmr 1, 5 1742 ; CHECK: blr 1743 } 1744 1745 define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1746 entry: 1747 %cmp1 = fcmp oeq float %c3, %c4 1748 %cmp3tmp = fcmp oeq float %c1, %c2 1749 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 1750 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1751 ret <4 x i1> %cond 1752 1753 ; CHECK-LABEL: @testqv4i1sgt 1754 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1755 ; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]] 1756 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1757 ; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]] 1758 ; CHECK: .LBB[[BB1]]: 1759 ; CHECK: qvfmr 5, 6 1760 ; CHECK: .LBB[[BB2]]: 1761 ; CHECK: qvfmr 1, 5 1762 ; CHECK: blr 1763 } 1764 1765 define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1766 entry: 1767 %cmp1 = fcmp oeq float %c3, %c4 1768 %cmp3tmp = fcmp oeq float %c1, %c2 1769 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 1770 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1771 ret <4 x i1> %cond 1772 1773 ; CHECK-LABEL: @testqv4i1ugt 1774 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1775 ; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]] 1776 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1777 ; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]] 1778 ; CHECK: .LBB[[BB1]]: 1779 ; CHECK: qvfmr 5, 6 1780 ; CHECK: .LBB[[BB2]]: 1781 ; CHECK: qvfmr 1, 5 1782 ; CHECK: blr 1783 } 1784 1785 define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 { 1786 entry: 1787 %cmp1 = fcmp oeq float %c3, %c4 1788 %cmp3tmp = fcmp oeq float %c1, %c2 1789 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1 1790 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2 1791 ret <4 x i1> %cond 1792 1793 ; CHECK-LABEL: @testqv4i1ne 1794 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4 1795 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 1796 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} 1797 ; CHECK: bclr 12, [[REG1]], 0 1798 ; CHECK: qvfmr 1, 6 1799 ; CHECK: blr 1800 } 1801 1802 attributes #0 = { nounwind readnone "target-cpu"="pwr7" } 1803 attributes #1 = { nounwind readnone "target-cpu"="a2q" } 1804 1805
