1 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gep-opt=0 < %s | FileCheck %s 2 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false -ppc-gep-opt=0 < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s 3 target datalayout = "E-m:e-i64:64-n32:64" 4 target triple = "powerpc64-unknown-linux-gnu" 5 6 ; Function Attrs: nounwind 7 define void @jbd2_journal_commit_transaction(i32 %input1, i32* %input2, i32* %input3, i8** %input4) #0 { 8 entry: 9 br label %while.body392 10 11 while.body392: ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph 12 %0 = load i8*, i8** %input4, align 8 13 %add.ptr399 = getelementptr inbounds i8, i8* %0, i64 -72 14 %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64* 15 %ivar = add i32 %input1, 1 16 %tobool.i1316 = icmp eq i32 %input1, 0 17 br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %while.end418 18 19 wait_on_buffer.exit1319: ; preds = %while.body392 20 %1 = load volatile i64, i64* %b_state.i.i1314, align 8 21 %conv.i.i1322 = and i64 %1, 1 22 %lnot404 = icmp eq i64 %conv.i.i1322, 0 23 %.err.4 = select i1 %lnot404, i32 -5, i32 %input1 24 %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #0 25 store i8* %0, i8** %input4, align 8 26 %cmp.i1312 = icmp eq i32* %input2, %input3 27 br i1 %cmp.i1312, label %while.end418, label %while.body392 28 29 while.end418: ; preds = %wait_on_buffer.exit1319, %do.body378 30 %err.4.lcssa = phi i32 [ %ivar, %while.body392 ], [ %.err.4, %wait_on_buffer.exit1319 ] 31 %tobool419 = icmp eq i32 %err.4.lcssa, 0 32 br i1 %tobool419, label %if.end421, label %if.then420 33 34 ; CHECK-LABEL: @jbd2_journal_commit_transaction 35 ; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction 36 ; CHECK: andi. 37 ; CHECK: crmove [[REG:[0-9]+]], 1 38 ; CHECK: stdcx. 39 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] 40 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] 41 ; CHECK-NO-ISEL: ori 7, 8, 0 42 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] 43 ; CHECK-NO-ISEL: [[TRUE]] 44 ; CHECK-NO-ISEL: addi 7, 3, 0 45 46 if.then420: ; preds = %while.end418 47 unreachable 48 49 if.end421: ; preds = %while.end418 50 unreachable 51 52 } 53 54 attributes #0 = { nounwind } 55 56
