1 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ 2 ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ 3 ; RUN: -O3 < %s | FileCheck %s 4 5 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ 6 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 7 ; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ 8 ; RUN: --implicit-check-not xxswapd 9 10 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ 11 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 12 ; RUN: -mattr=-power9-vector < %s | FileCheck %s 13 14 ; These tests verify that VSX swap optimization works when loading a scalar 15 ; into a vector register. 16 17 18 @x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 19 @z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 20 @y = global double 1.780000e+00, align 8 21 22 define void @bar0() { 23 ; CHECK-LABEL: bar0: 24 ; CHECK: # %bb.0: # %entry 25 ; CHECK: addis r3, r2, .LC0@toc@ha 26 ; CHECK: addis r4, r2, .LC1@toc@ha 27 ; CHECK: ld r3, .LC0@toc@l(r3) 28 ; CHECK: addis r3, r2, .LC2@toc@ha 29 ; CHECK: ld r3, .LC2@toc@l(r3) 30 ; CHECK: xxpermdi vs0, vs0, vs1, 1 31 ; CHECK: stxvd2x vs0, 0, r3 32 ; CHECK: blr 33 ; 34 ; CHECK-P9-LABEL: bar0: 35 ; CHECK-P9: # %bb.0: # %entry 36 ; CHECK-P9: addis r3, r2, .LC0@toc@ha 37 ; CHECK-P9: addis r4, r2, .LC1@toc@ha 38 ; CHECK-P9: ld r3, .LC0@toc@l(r3) 39 ; CHECK-P9: ld r4, .LC1@toc@l(r4) 40 ; CHECK-P9: lfd f0, 0(r3) 41 ; CHECK-P9: lxvx vs1, 0, r4 42 ; CHECK-P9: addis r3, r2, .LC2@toc@ha 43 ; CHECK-P9: ld r3, .LC2@toc@l(r3) 44 ; CHECK-P9: xxpermdi vs0, f0, f0, 2 45 ; CHECK-P9: xxpermdi vs0, vs1, vs0, 1 46 ; CHECK-P9: stxvx vs0, 0, r3 47 ; CHECK-P9: blr 48 entry: 49 %0 = load <2 x double>, <2 x double>* @x, align 16 50 %1 = load double, double* @y, align 8 51 %vecins = insertelement <2 x double> %0, double %1, i32 0 52 store <2 x double> %vecins, <2 x double>* @z, align 16 53 ret void 54 } 55 56 define void @bar1() { 57 ; CHECK-LABEL: bar1: 58 ; CHECK: # %bb.0: # %entry 59 ; CHECK: addis r3, r2, .LC0@toc@ha 60 ; CHECK: addis r4, r2, .LC1@toc@ha 61 ; CHECK: ld r3, .LC0@toc@l(r3) 62 ; CHECK: addis r3, r2, .LC2@toc@ha 63 ; CHECK: ld r3, .LC2@toc@l(r3) 64 ; CHECK: xxmrghd vs0, vs1, vs0 65 ; CHECK: stxvd2x vs0, 0, r3 66 ; CHECK: blr 67 ; 68 ; CHECK-P9-LABEL: bar1: 69 ; CHECK-P9: # %bb.0: # %entry 70 ; CHECK-P9: addis r3, r2, .LC0@toc@ha 71 ; CHECK-P9: addis r4, r2, .LC1@toc@ha 72 ; CHECK-P9: ld r3, .LC0@toc@l(r3) 73 ; CHECK-P9: ld r4, .LC1@toc@l(r4) 74 ; CHECK-P9: lfd f0, 0(r3) 75 ; CHECK-P9: lxvx vs1, 0, r4 76 ; CHECK-P9: addis r3, r2, .LC2@toc@ha 77 ; CHECK-P9: ld r3, .LC2@toc@l(r3) 78 ; CHECK-P9: xxpermdi vs0, f0, f0, 2 79 ; CHECK-P9: xxmrgld vs0, vs0, vs1 80 ; CHECK-P9: stxvx vs0, 0, r3 81 ; CHECK-P9: blr 82 entry: 83 %0 = load <2 x double>, <2 x double>* @x, align 16 84 %1 = load double, double* @y, align 8 85 %vecins = insertelement <2 x double> %0, double %1, i32 1 86 store <2 x double> %vecins, <2 x double>* @z, align 16 87 ret void 88 } 89 90
