1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 ; ModuleID = 'ComparisonTestCases/testComparesiequc.c' 9 10 @glob = common local_unnamed_addr global i8 0, align 1 11 12 ; Function Attrs: norecurse nounwind readnone 13 define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) { 14 ; CHECK-LABEL: test_iequc: 15 ; CHECK: # %bb.0: # %entry 16 ; CHECK-NEXT: xor r3, r3, r4 17 ; CHECK-NEXT: cntlzw r3, r3 18 ; CHECK-NEXT: srwi r3, r3, 5 19 ; CHECK-NEXT: blr 20 entry: 21 %cmp = icmp eq i8 %a, %b 22 %conv2 = zext i1 %cmp to i32 23 ret i32 %conv2 24 } 25 26 ; Function Attrs: norecurse nounwind readnone 27 define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) { 28 ; CHECK-LABEL: test_iequc_sext: 29 ; CHECK: # %bb.0: # %entry 30 ; CHECK-NEXT: xor r3, r3, r4 31 ; CHECK-NEXT: cntlzw r3, r3 32 ; CHECK-NEXT: srwi r3, r3, 5 33 ; CHECK-NEXT: neg r3, r3 34 ; CHECK-NEXT: blr 35 entry: 36 %cmp = icmp eq i8 %a, %b 37 %sub = sext i1 %cmp to i32 38 ret i32 %sub 39 } 40 41 ; Function Attrs: norecurse nounwind readnone 42 define signext i32 @test_iequc_z(i8 zeroext %a) { 43 ; CHECK-LABEL: test_iequc_z: 44 ; CHECK: # %bb.0: # %entry 45 ; CHECK-NEXT: cntlzw r3, r3 46 ; CHECK-NEXT: srwi r3, r3, 5 47 ; CHECK-NEXT: blr 48 entry: 49 %cmp = icmp eq i8 %a, 0 50 %conv1 = zext i1 %cmp to i32 51 ret i32 %conv1 52 } 53 54 ; Function Attrs: norecurse nounwind readnone 55 define signext i32 @test_iequc_sext_z(i8 zeroext %a) { 56 ; CHECK-LABEL: test_iequc_sext_z: 57 ; CHECK: # %bb.0: # %entry 58 ; CHECK-NEXT: cntlzw r3, r3 59 ; CHECK-NEXT: srwi r3, r3, 5 60 ; CHECK-NEXT: neg r3, r3 61 ; CHECK-NEXT: blr 62 entry: 63 %cmp = icmp eq i8 %a, 0 64 %sub = sext i1 %cmp to i32 65 ret i32 %sub 66 } 67 68 ; Function Attrs: norecurse nounwind 69 define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) { 70 ; CHECK-LABEL: test_iequc_store: 71 ; CHECK: # %bb.0: # %entry 72 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 73 ; CHECK-NEXT: xor r3, r3, r4 74 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 75 ; CHECK-NEXT: cntlzw r3, r3 76 ; CHECK-NEXT: srwi r3, r3, 5 77 ; CHECK-NEXT: stb r3, 0(r4) 78 ; CHECK-NEXT: blr 79 entry: 80 %cmp = icmp eq i8 %a, %b 81 %conv3 = zext i1 %cmp to i8 82 store i8 %conv3, i8* @glob, align 1 83 ret void 84 } 85 86 ; Function Attrs: norecurse nounwind 87 define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { 88 ; CHECK-LABEL: test_iequc_sext_store: 89 ; CHECK: # %bb.0: # %entry 90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 91 ; CHECK-NEXT: xor r3, r3, r4 92 ; CHECK-NEXT: cntlzw r3, r3 93 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 94 ; CHECK-NEXT: srwi r3, r3, 5 95 ; CHECK-NEXT: neg r3, r3 96 ; CHECK-NEXT: stb r3, 0(r4) 97 ; CHECK-NEXT: blr 98 entry: 99 %cmp = icmp eq i8 %a, %b 100 %conv3 = sext i1 %cmp to i8 101 store i8 %conv3, i8* @glob, align 1 102 ret void 103 } 104 105 ; Function Attrs: norecurse nounwind 106 define void @test_iequc_z_store(i8 zeroext %a) { 107 ; CHECK-LABEL: test_iequc_z_store: 108 ; CHECK: # %bb.0: # %entry 109 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 110 ; CHECK-NEXT: cntlzw r3, r3 111 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 112 ; CHECK-NEXT: srwi r3, r3, 5 113 ; CHECK-NEXT: stb r3, 0(r4) 114 ; CHECK-NEXT: blr 115 entry: 116 %cmp = icmp eq i8 %a, 0 117 %conv2 = zext i1 %cmp to i8 118 store i8 %conv2, i8* @glob, align 1 119 ret void 120 } 121 122 ; Function Attrs: norecurse nounwind 123 define void @test_iequc_sext_z_store(i8 zeroext %a) { 124 ; CHECK-LABEL: test_iequc_sext_z_store: 125 ; CHECK: # %bb.0: # %entry 126 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 127 ; CHECK-NEXT: cntlzw r3, r3 128 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 129 ; CHECK-NEXT: srwi r3, r3, 5 130 ; CHECK-NEXT: neg r3, r3 131 ; CHECK-NEXT: stb r3, 0(r4) 132 ; CHECK-NEXT: blr 133 entry: 134 %cmp = icmp eq i8 %a, 0 135 %conv2 = sext i1 %cmp to i8 136 store i8 %conv2, i8* @glob, align 1 137 ret void 138 } 139
