1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 @glob = common local_unnamed_addr global i32 0, align 4 9 10 define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { 11 ; CHECK-LABEL: test_ilesi: 12 ; CHECK: # %bb.0: # %entry 13 ; CHECK-NEXT: sub r3, r4, r3 14 ; CHECK-NEXT: rldicl r3, r3, 1, 63 15 ; CHECK-NEXT: xori r3, r3, 1 16 ; CHECK-NEXT: blr 17 entry: 18 %cmp = icmp sle i32 %a, %b 19 %conv = zext i1 %cmp to i32 20 ret i32 %conv 21 } 22 23 define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { 24 ; CHECK-LABEL: test_ilesi_sext: 25 ; CHECK: # %bb.0: # %entry 26 ; CHECK-NEXT: sub r3, r4, r3 27 ; CHECK-NEXT: rldicl r3, r3, 1, 63 28 ; CHECK-NEXT: addi r3, r3, -1 29 ; CHECK-NEXT: blr 30 entry: 31 %cmp = icmp sle i32 %a, %b 32 %sub = sext i1 %cmp to i32 33 ret i32 %sub 34 } 35 36 define void @test_ilesi_store(i32 signext %a, i32 signext %b) { 37 ; CHECK-LABEL: test_ilesi_store: 38 ; CHECK: # %bb.0: # %entry 39 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 40 ; CHECK-NEXT: sub r3, r4, r3 41 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 42 ; CHECK-NEXT: rldicl r3, r3, 1, 63 43 ; CHECK-NEXT: xori r3, r3, 1 44 ; CHECK-NEXT: stw r3, 0(r4) 45 ; CHECK-NEXT: blr 46 entry: 47 %cmp = icmp sle i32 %a, %b 48 %conv = zext i1 %cmp to i32 49 store i32 %conv, i32* @glob, align 4 50 ret void 51 } 52 53 define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { 54 ; CHECK-LABEL: test_ilesi_sext_store: 55 ; CHECK: # %bb.0: # %entry 56 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 57 ; CHECK-NEXT: sub r3, r4, r3 58 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 59 ; CHECK-NEXT: rldicl r3, r3, 1, 63 60 ; CHECK-NEXT: addi r3, r3, -1 61 ; CHECK-NEXT: stw r3, 0(r4) 62 ; CHECK-NEXT: blr 63 entry: 64 %cmp = icmp sle i32 %a, %b 65 %sub = sext i1 %cmp to i32 66 store i32 %sub, i32* @glob, align 4 67 ret void 68 } 69
