1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 @glob = common local_unnamed_addr global i64 0, align 8 9 10 define signext i32 @test_ilesll(i64 %a, i64 %b) { 11 ; CHECK-LABEL: test_ilesll: 12 ; CHECK: # %bb.0: # %entry 13 ; CHECK-NEXT: sradi r5, r4, 63 14 ; CHECK-NEXT: rldicl r6, r3, 1, 63 15 ; CHECK-NEXT: subfc r3, r3, r4 16 ; CHECK-NEXT: adde r3, r5, r6 17 ; CHECK-NEXT: blr 18 entry: 19 %cmp = icmp sle i64 %a, %b 20 %conv = zext i1 %cmp to i32 21 ret i32 %conv 22 } 23 24 define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { 25 ; CHECK-LABEL: test_ilesll_sext: 26 ; CHECK: # %bb.0: # %entry 27 ; CHECK-NEXT: sradi r5, r4, 63 28 ; CHECK-NEXT: rldicl r6, r3, 1, 63 29 ; CHECK-NEXT: subfc r3, r3, r4 30 ; CHECK-NEXT: adde r3, r5, r6 31 ; CHECK-NEXT: neg r3, r3 32 ; CHECK-NEXT: blr 33 entry: 34 %cmp = icmp sle i64 %a, %b 35 %sub = sext i1 %cmp to i32 36 ret i32 %sub 37 } 38 39 define signext i32 @test_ilesll_z(i64 %a) { 40 ; CHECK-LABEL: test_ilesll_z: 41 ; CHECK: # %bb.0: # %entry 42 ; CHECK-NEXT: addi r4, r3, -1 43 ; CHECK-NEXT: or r3, r4, r3 44 ; CHECK-NEXT: rldicl r3, r3, 1, 63 45 ; CHECK-NEXT: blr 46 entry: 47 %cmp = icmp slt i64 %a, 1 48 %conv = zext i1 %cmp to i32 49 ret i32 %conv 50 } 51 52 define signext i32 @test_ilesll_sext_z(i64 %a) { 53 ; CHECK-LABEL: test_ilesll_sext_z: 54 ; CHECK: # %bb.0: # %entry 55 ; CHECK-NEXT: addi r4, r3, -1 56 ; CHECK-NEXT: or r3, r4, r3 57 ; CHECK-NEXT: sradi r3, r3, 63 58 ; CHECK-NEXT: blr 59 entry: 60 %cmp = icmp slt i64 %a, 1 61 %sub = sext i1 %cmp to i32 62 ret i32 %sub 63 } 64 65 define void @test_ilesll_store(i64 %a, i64 %b) { 66 ; CHECK-LABEL: test_ilesll_store: 67 ; CHECK: # %bb.0: # %entry 68 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 69 ; CHECK-NEXT: sradi r6, r4, 63 70 ; CHECK-NEXT: ld r5, .LC0@toc@l(r5) 71 ; CHECK-NEXT: subfc r4, r3, r4 72 ; CHECK-NEXT: rldicl r3, r3, 1, 63 73 ; CHECK-NEXT: adde r3, r6, r3 74 ; CHECK-NEXT: std r3, 0(r5) 75 ; CHECK-NEXT: blr 76 entry: 77 %cmp = icmp sle i64 %a, %b 78 %conv1 = zext i1 %cmp to i64 79 store i64 %conv1, i64* @glob, align 8 80 ret void 81 } 82 83 define void @test_ilesll_sext_store(i64 %a, i64 %b) { 84 ; CHECK-LABEL: test_ilesll_sext_store: 85 ; CHECK: # %bb.0: # %entry 86 ; CHECK-NEXT: sradi r6, r4, 63 87 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 88 ; CHECK-NEXT: subfc r4, r3, r4 89 ; CHECK-NEXT: rldicl r3, r3, 1, 63 90 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 91 ; CHECK-NEXT: adde r3, r6, r3 92 ; CHECK-NEXT: neg r3, r3 93 ; CHECK-NEXT: std r3, 0(r4) 94 ; CHECK-NEXT: blr 95 entry: 96 %cmp = icmp sle i64 %a, %b 97 %conv1 = sext i1 %cmp to i64 98 store i64 %conv1, i64* @glob, align 8 99 ret void 100 } 101 102 define void @test_ilesll_z_store(i64 %a) { 103 ; CHECK-LABEL: test_ilesll_z_store: 104 ; CHECK: # %bb.0: # %entry 105 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 106 ; CHECK-NEXT: addi r5, r3, -1 107 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 108 ; CHECK-NEXT: or r3, r5, r3 109 ; CHECK-NEXT: rldicl r3, r3, 1, 63 110 ; CHECK-NEXT: std r3, 0(r4) 111 ; CHECK-NEXT: blr 112 entry: 113 %cmp = icmp slt i64 %a, 1 114 %conv1 = zext i1 %cmp to i64 115 store i64 %conv1, i64* @glob, align 8 116 ret void 117 } 118 119 define void @test_ilesll_sext_z_store(i64 %a) { 120 ; CHECK-LABEL: test_ilesll_sext_z_store: 121 ; CHECK: # %bb.0: # %entry 122 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 123 ; CHECK-NEXT: addi r5, r3, -1 124 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 125 ; CHECK-NEXT: or r3, r5, r3 126 ; CHECK-NEXT: sradi r3, r3, 63 127 ; CHECK-NEXT: std r3, 0(r4) 128 ; CHECK-NEXT: blr 129 entry: 130 %cmp = icmp slt i64 %a, 1 131 %conv1 = sext i1 %cmp to i64 132 store i64 %conv1, i64* @glob, align 8 133 ret void 134 } 135
