1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 7 8 @glob = common local_unnamed_addr global i64 0, align 8 9 10 ; Function Attrs: norecurse nounwind readnone 11 define i64 @test_llgeull(i64 %a, i64 %b) { 12 entry: 13 %cmp = icmp uge i64 %a, %b 14 %conv1 = zext i1 %cmp to i64 15 ret i64 %conv1 16 ; CHECK-LABEL: test_llgeull: 17 ; CHECK: subfc {{r[0-9]+}}, r4, r3 18 ; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 19 ; CHECK-NEXT: addi r3, [[REG1]], 1 20 ; CHECK: blr 21 } 22 23 ; Function Attrs: norecurse nounwind readnone 24 define i64 @test_llgeull_sext(i64 %a, i64 %b) { 25 entry: 26 %cmp = icmp uge i64 %a, %b 27 %conv1 = sext i1 %cmp to i64 28 ret i64 %conv1 29 ; CHECK-LABEL: @test_llgeull_sext 30 ; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 31 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} 32 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]] 33 ; CHECK: blr 34 } 35 36 ; Function Attrs: norecurse nounwind readnone 37 define i64 @test_llgeull_z(i64 %a) { 38 entry: 39 %cmp = icmp uge i64 %a, 0 40 %conv1 = zext i1 %cmp to i64 41 ret i64 %conv1 42 ; CHECK-LABEL: @test_llgeull_z 43 ; CHECK: li r3, 1 44 ; CHECK-NEXT: blr 45 } 46 47 ; Function Attrs: norecurse nounwind readnone 48 define i64 @test_llgeull_sext_z(i64 %a) { 49 entry: 50 %cmp = icmp uge i64 %a, 0 51 %conv1 = sext i1 %cmp to i64 52 ret i64 %conv1 53 ; CHECK-LABEL: @test_llgeull_sext_z 54 ; CHECK: li r3, -1 55 ; CHECK-NEXT: blr 56 } 57 58 ; Function Attrs: norecurse nounwind 59 define void @test_llgeull_store(i64 %a, i64 %b) { 60 entry: 61 %cmp = icmp uge i64 %a, %b 62 %conv1 = zext i1 %cmp to i64 63 store i64 %conv1, i64* @glob 64 ret void 65 ; CHECK-LABEL: test_llgeull_store: 66 ; CHECK: subfc {{r[0-9]+}}, r4, r3 67 ; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 68 ; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 69 ; CHECK: blr 70 } 71 72 ; Function Attrs: norecurse nounwind 73 define void @test_llgeull_sext_store(i64 %a, i64 %b) { 74 entry: 75 %cmp = icmp uge i64 %a, %b 76 %conv1 = sext i1 %cmp to i64 77 store i64 %conv1, i64* @glob 78 ret void 79 ; CHECK-LABEL: @test_llgeull_sext_store 80 ; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 81 ; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} 82 ; CHECK: not [[REG3:r[0-9]+]], [[REG2]] 83 ; CHECK: std [[REG3]] 84 ; CHECK: blr 85 } 86 87 ; Function Attrs: norecurse nounwind 88 define void @test_llgeull_z_store(i64 %a) { 89 entry: 90 %cmp = icmp uge i64 %a, 0 91 %conv1 = zext i1 %cmp to i64 92 store i64 %conv1, i64* @glob 93 ret void 94 ; CHECK-LABEL: @test_llgeull_z_store 95 ; CHECK: li [[REG1:r[0-9]+]], 1 96 ; CHECK: std [[REG1]] 97 ; CHECK: blr 98 } 99 100 ; Function Attrs: norecurse nounwind 101 define void @test_llgeull_sext_z_store(i64 %a) { 102 entry: 103 store i64 -1, i64* @glob 104 ret void 105 ; CHECK-LABEL: @test_llgeull_sext_z_store 106 ; CHECK: li [[REG1:r[0-9]+]], -1 107 ; CHECK: std [[REG1]] 108 ; CHECK: blr 109 } 110 111
