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      1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
      2 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
      3 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
      4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
      5 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
      6 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
      7 
      8 @glob = common local_unnamed_addr global i64 0, align 8
      9 
     10 ; Function Attrs: norecurse nounwind readnone
     11 define i64 @test_llgtsll(i64 %a, i64 %b) {
     12 ; CHECK-LABEL: test_llgtsll:
     13 ; CHECK:       # %bb.0: # %entry
     14 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
     15 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
     16 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
     17 ; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
     18 ; CHECK-NEXT:    xori r3, [[REG4]], 1
     19 ; CHECK-NEXT:    blr
     20 entry:
     21   %cmp = icmp sgt i64 %a, %b
     22   %conv1 = zext i1 %cmp to i64
     23   ret i64 %conv1
     24 }
     25 
     26 ; Function Attrs: norecurse nounwind readnone
     27 define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
     28 ; CHECK-LABEL: test_llgtsll_sext:
     29 ; CHECK:       # %bb.0: # %entry
     30 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
     31 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
     32 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
     33 ; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
     34 ; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
     35 ; CHECK-NEXT:    neg r3, [[REG5]]
     36 ; CHECK-NEXT:    blr
     37 entry:
     38   %cmp = icmp sgt i64 %a, %b
     39   %conv1 = sext i1 %cmp to i64
     40   ret i64 %conv1
     41 }
     42 
     43 ; FIXME
     44 ; Function Attrs: norecurse nounwind readnone
     45 define i64 @test_llgtsll_z(i64 %a) {
     46 ; CHECK-LABEL: test_llgtsll_z:
     47 ; CHECK:       # %bb.0: # %entry
     48 ; CHECK-NEXT:    addi r4, r3, -1
     49 ; CHECK-NEXT:    nor r3, r4, r3
     50 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
     51 ; CHECK-NEXT:    blr
     52 entry:
     53   %cmp = icmp sgt i64 %a, 0
     54   %conv1 = zext i1 %cmp to i64
     55   ret i64 %conv1
     56 }
     57 
     58 ; Function Attrs: norecurse nounwind readnone
     59 define i64 @test_llgtsll_sext_z(i64 %a) {
     60 ; CHECK-LABEL: test_llgtsll_sext_z:
     61 ; CHECK:       addi [[REG1:r[0-9]+]], r3, -1
     62 ; CHECK-NEXT:  nor [[REG2:r[0-9]+]], [[REG1]], r3
     63 ; CHECK-NEXT:  sradi r3, [[REG2]], 63
     64 entry:
     65   %cmp = icmp sgt i64 %a, 0
     66   %conv1 = sext i1 %cmp to i64
     67   ret i64 %conv1
     68 }
     69 
     70 ; Function Attrs: norecurse nounwind
     71 define void @test_llgtsll_store(i64 %a, i64 %b) {
     72 ; CHECK-LABEL: test_llgtsll_store:
     73 ; CHECK:       # %bb.0: # %entry
     74 ; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
     75 ; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
     76 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
     77 ; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
     78 ; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
     79 ; CHECK-NOT:     neg 
     80 entry:
     81   %cmp = icmp sgt i64 %a, %b
     82   %conv1 = zext i1 %cmp to i64
     83   store i64 %conv1, i64* @glob, align 8
     84   ret void
     85 }
     86 
     87 ; Function Attrs: norecurse nounwind
     88 define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
     89 ; CHECK-LABEL: test_llgtsll_sext_store:
     90 ; CHECK:       # %bb.0: # %entry
     91 ; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
     92 ; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
     93 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
     94 ; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
     95 ; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
     96 ; CHECK:         neg {{r[0-9]+}}, [[REG5]]
     97 entry:
     98   %cmp = icmp sgt i64 %a, %b
     99   %conv1 = sext i1 %cmp to i64
    100   store i64 %conv1, i64* @glob, align 8
    101   ret void
    102 }
    103 
    104 ; FIXME
    105 ; Function Attrs: norecurse nounwind
    106 define void @test_llgtsll_z_store(i64 %a) {
    107 ; CHECK-LABEL: test_llgtsll_z_store:
    108 ; CHECK:       # %bb.0: # %entry
    109 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
    110 ; CHECK-NEXT:    addi r5, r3, -1
    111 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
    112 ; CHECK-NEXT:    nor r3, r5, r3
    113 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
    114 ; CHECK-NEXT:    std r3, 0(r4)
    115 ; CHECK-NEXT:    blr
    116 entry:
    117   %cmp = icmp sgt i64 %a, 0
    118   %conv1 = zext i1 %cmp to i64
    119   store i64 %conv1, i64* @glob, align 8
    120   ret void
    121 }
    122 
    123 ; Function Attrs: norecurse nounwind
    124 define void @test_llgtsll_sext_z_store(i64 %a) {
    125 ; CHECK-LABEL: test_llgtsll_sext_z_store:
    126 ; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
    127 ; CHECK:    nor [[REG2:r[0-9]+]], [[REG1]], r3
    128 ; CHECK:    sradi [[REG3:r[0-9]+]], [[REG2]], 63
    129 entry:
    130   %cmp = icmp sgt i64 %a, 0
    131   %conv1 = sext i1 %cmp to i64
    132   store i64 %conv1, i64* @glob, align 8
    133   ret void
    134 }
    135