1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 7 8 @glob = common local_unnamed_addr global i16 0, align 2 9 10 ; Function Attrs: norecurse nounwind readnone 11 define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) { 12 ; CHECK-LABEL: test_llgtus: 13 ; CHECK: # %bb.0: # %entry 14 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 15 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 16 ; CHECK-NEXT: blr 17 entry: 18 %cmp = icmp ugt i16 %a, %b 19 %conv3 = zext i1 %cmp to i64 20 ret i64 %conv3 21 } 22 23 ; Function Attrs: norecurse nounwind readnone 24 define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) { 25 ; CHECK-LABEL: test_llgtus_sext: 26 ; CHECK: # %bb.0: # %entry 27 ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 28 ; CHECK-NEXT: sradi r3, [[REG]], 63 29 ; CHECK-NEXT: blr 30 entry: 31 %cmp = icmp ugt i16 %a, %b 32 %conv3 = sext i1 %cmp to i64 33 ret i64 %conv3 34 } 35 36 ; Function Attrs: norecurse nounwind readnone 37 define i64 @test_llgtus_z(i16 zeroext %a) { 38 ; CHECK-LABEL: test_llgtus_z: 39 ; CHECK: # %bb.0: # %entry 40 ; CHECK-NEXT: cntlzw r3, r3 41 ; CHECK-NEXT: srwi r3, r3, 5 42 ; CHECK-NEXT: xori r3, r3, 1 43 ; CHECK-NEXT: blr 44 entry: 45 %cmp = icmp ne i16 %a, 0 46 %conv2 = zext i1 %cmp to i64 47 ret i64 %conv2 48 } 49 50 ; Function Attrs: norecurse nounwind readnone 51 define i64 @test_llgtus_sext_z(i16 zeroext %a) { 52 ; CHECK-LABEL: test_llgtus_sext_z: 53 ; CHECK: # %bb.0: # %entry 54 ; CHECK-NEXT: cntlzw r3, r3 55 ; CHECK-NEXT: srwi r3, r3, 5 56 ; CHECK-NEXT: xori r3, r3, 1 57 ; CHECK-NEXT: neg r3, r3 58 ; CHECK-NEXT: blr 59 entry: 60 %cmp = icmp ne i16 %a, 0 61 %conv2 = sext i1 %cmp to i64 62 ret i64 %conv2 63 } 64 65 ; Function Attrs: norecurse nounwind 66 define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) { 67 ; CHECK-LABEL: test_llgtus_store: 68 ; CHECK: # %bb.0: # %entry 69 ; CHECK: sub [[REG:r[0-9]+]], r4, r3 70 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 71 entry: 72 %cmp = icmp ugt i16 %a, %b 73 %conv3 = zext i1 %cmp to i16 74 store i16 %conv3, i16* @glob, align 2 75 ret void 76 } 77 78 ; Function Attrs: norecurse nounwind 79 define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) { 80 ; CHECK-LABEL: test_llgtus_sext_store: 81 ; CHECK: # %bb.0: # %entry 82 ; CHECK: sub [[REG:r[0-9]+]], r4, r3 83 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 84 entry: 85 %cmp = icmp ugt i16 %a, %b 86 %conv3 = sext i1 %cmp to i16 87 store i16 %conv3, i16* @glob, align 2 88 ret void 89 } 90 91 ; Function Attrs: norecurse nounwind 92 define void @test_llgtus_z_store(i16 zeroext %a) { 93 ; CHECK-LABEL: test_llgtus_z_store: 94 ; CHECK: # %bb.0: # %entry 95 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 96 ; CHECK-NEXT: cntlzw r3, r3 97 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 98 ; CHECK-NEXT: srwi r3, r3, 5 99 ; CHECK-NEXT: xori r3, r3, 1 100 ; CHECK-NEXT: sth r3, 0(r4) 101 ; CHECK-NEXT: blr 102 entry: 103 %cmp = icmp ne i16 %a, 0 104 %conv2 = zext i1 %cmp to i16 105 store i16 %conv2, i16* @glob, align 2 106 ret void 107 } 108 109 ; Function Attrs: norecurse nounwind 110 define void @test_llgtus_sext_z_store(i16 zeroext %a) { 111 ; CHECK-LABEL: test_llgtus_sext_z_store: 112 ; CHECK: # %bb.0: # %entry 113 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 114 ; CHECK-NEXT: cntlzw r3, r3 115 ; CHECK-NEXT: srwi r3, r3, 5 116 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 117 ; CHECK-NEXT: xori r3, r3, 1 118 ; CHECK-NEXT: neg r3, r3 119 ; CHECK-NEXT: sth r3, 0(r4) 120 ; CHECK-NEXT: blr 121 entry: 122 %cmp = icmp ne i16 %a, 0 123 %conv2 = sext i1 %cmp to i16 124 store i16 %conv2, i16* @glob, align 2 125 ret void 126 } 127 128
