1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 2 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 3 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 5 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 6 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 7 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 8 9 @glob = common local_unnamed_addr global i64 0, align 8 10 11 ; Function Attrs: norecurse nounwind readnone 12 define i64 @test_llltsll(i64 %a, i64 %b) { 13 ; CHECK-LABEL: test_llltsll: 14 ; CHECK: # %bb.0: # %entry 15 ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 16 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 17 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 18 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 19 ; CHECK-NEXT: xori r3, [[REG4]], 1 20 ; CHECK-NEXT: blr 21 entry: 22 %cmp = icmp slt i64 %a, %b 23 %conv1 = zext i1 %cmp to i64 24 ret i64 %conv1 25 } 26 27 ; Function Attrs: norecurse nounwind readnone 28 define i64 @test_llltsll_sext(i64 %a, i64 %b) { 29 ; CHECK-LABEL: test_llltsll_sext: 30 ; CHECK: # %bb.0: # %entry 31 ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 32 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 33 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 34 ; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 35 ; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1 36 ; CHECK-NEXT: neg r3, [[REG5]] 37 ; CHECK-NEXT: blr 38 entry: 39 %cmp = icmp slt i64 %a, %b 40 %conv1 = sext i1 %cmp to i64 41 ret i64 %conv1 42 } 43 44 ; Function Attrs: norecurse nounwind readnone 45 define i64 @test_llltsll_sext_z(i64 %a) { 46 ; CHECK-LABEL: test_llltsll_sext_z: 47 ; CHECK: # %bb.0: # %entry 48 ; CHECK-NEXT: sradi r3, r3, 63 49 ; CHECK-NEXT: blr 50 entry: 51 %cmp = icmp slt i64 %a, 0 52 %sub = sext i1 %cmp to i64 53 ret i64 %sub 54 } 55 56 ; Function Attrs: norecurse nounwind 57 define void @test_llltsll_store(i64 %a, i64 %b) { 58 ; CHECK-LABEL: test_llltsll_store: 59 ; CHECK: # %bb.0: # %entry 60 ; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 61 ; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 62 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 63 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 64 ; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 65 ; CHECK-NOT: neg 66 entry: 67 %cmp = icmp slt i64 %a, %b 68 %conv1 = zext i1 %cmp to i64 69 store i64 %conv1, i64* @glob, align 8 70 ret void 71 } 72 73 ; Function Attrs: norecurse nounwind 74 define void @test_llltsll_sext_store(i64 %a, i64 %b) { 75 ; CHECK-LABEL: test_llltsll_sext_store: 76 ; CHECK: # %bb.0: # %entry 77 ; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 78 ; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 79 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 80 ; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]] 81 ; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1 82 ; CHECK: neg {{r[0-9]+}}, [[REG5]] 83 entry: 84 %cmp = icmp slt i64 %a, %b 85 %conv1 = sext i1 %cmp to i64 86 store i64 %conv1, i64* @glob, align 8 87 ret void 88 } 89 90 ; Function Attrs: norecurse nounwind 91 define void @test_llltsll_sext_z_store(i64 %a) { 92 ; CHECK-LABEL: test_llltsll_sext_z_store: 93 ; CHECK: sradi r3, r3, 63 94 entry: 95 %cmp = icmp slt i64 %a, 0 96 %sub = sext i1 %cmp to i64 97 store i64 %sub, i64* @glob, align 8 98 ret void 99 } 100
